JPS5691430A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS5691430A
JPS5691430A JP16903179A JP16903179A JPS5691430A JP S5691430 A JPS5691430 A JP S5691430A JP 16903179 A JP16903179 A JP 16903179A JP 16903179 A JP16903179 A JP 16903179A JP S5691430 A JPS5691430 A JP S5691430A
Authority
JP
Japan
Prior art keywords
layer
polycrystalline
thin film
film
gaps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16903179A
Other languages
Japanese (ja)
Inventor
Kazunari Shirai
Izumi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16903179A priority Critical patent/JPS5691430A/en
Publication of JPS5691430A publication Critical patent/JPS5691430A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain polycrystalline si layers of fine a width by forming a thin film layer on the part of polycrystalline Si coated all over the surface of a substrate where gaps are to be formed while forming an SiO2 film thicker than the thin film on the part where the polycrystals are to be remained, and selectively removing the polycrystalline Si layer. CONSTITUTION:A polycrystalline Si layer 3 is coated over a substrate 1 via an SiO2 film 2, and on the layer, a thin film layer consisting of an SiO2 film 4 and an Si3N4 film 5 is formed. Further, on part where gaps are to be formed, a resist film mask 6 is coated, and the exposed part of the thin film layer is removed. By oxidizing at high temperatures, a thick SiO2 film 7 is formed on the exposed polycrystalline Si layer, and the remaining thin film layer 4, 5 is removed. By etching the polycrystalline layer next, fine gaps 8 are formed. By so doing, polycrystalline Si layers of high resolving power for fine width wiring, etc., can be formed and the degree of integration can be increased.
JP16903179A 1979-12-25 1979-12-25 Preparation of semiconductor device Pending JPS5691430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16903179A JPS5691430A (en) 1979-12-25 1979-12-25 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16903179A JPS5691430A (en) 1979-12-25 1979-12-25 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5691430A true JPS5691430A (en) 1981-07-24

Family

ID=15879031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16903179A Pending JPS5691430A (en) 1979-12-25 1979-12-25 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5691430A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62105426A (en) * 1985-10-30 1987-05-15 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Formation of mask structure of the extent of sub-microns
JPS62126672A (en) * 1985-11-27 1987-06-08 Mitsubishi Electric Corp Manufacture of charge transfer device
JPS63217630A (en) * 1987-03-06 1988-09-09 Sony Corp Manufacture of semiconductor device
US5219782A (en) * 1992-03-30 1993-06-15 Texas Instruments Incorporated Sublithographic antifuse method for manufacturing

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62105426A (en) * 1985-10-30 1987-05-15 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−ション Formation of mask structure of the extent of sub-microns
JPH0529133B2 (en) * 1985-10-30 1993-04-28 Intaanashonaru Bijinesu Mashiinzu Corp
JPS62126672A (en) * 1985-11-27 1987-06-08 Mitsubishi Electric Corp Manufacture of charge transfer device
JPS63217630A (en) * 1987-03-06 1988-09-09 Sony Corp Manufacture of semiconductor device
US5219782A (en) * 1992-03-30 1993-06-15 Texas Instruments Incorporated Sublithographic antifuse method for manufacturing

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