JPS56111246A - Preparation of semiconductor device - Google Patents

Preparation of semiconductor device

Info

Publication number
JPS56111246A
JPS56111246A JP642880A JP642880A JPS56111246A JP S56111246 A JPS56111246 A JP S56111246A JP 642880 A JP642880 A JP 642880A JP 642880 A JP642880 A JP 642880A JP S56111246 A JPS56111246 A JP S56111246A
Authority
JP
Japan
Prior art keywords
film
mask
layer
alloy
resist mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP642880A
Other languages
Japanese (ja)
Inventor
Masaki Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP642880A priority Critical patent/JPS56111246A/en
Publication of JPS56111246A publication Critical patent/JPS56111246A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain a wiring of high precision, by coating an Al layer with a protective film resistive to an alkaline developing solution and protecting the Al layer from corrosion during the process of developing. CONSTITUTION:An Al-Si alloy layer 15 and an Si3N4 film 16 are stacked on an SiO2 film 13 with an opening on an N<+> layer 12 on a P<-> type Si substrate. Then a resist mask 17 is formed, and the film 16 is etched away by ion etching of CF4+ H2. Thereafter the film 15 is etched away by ion etching of CCl+H2. The resist mask 17 is removed by O2 plasma, the film 16 is removed by CF4+H2 gas and covered with PSG19. A resist mask 20 is again formed and the PSG19 is etched by CF4+O2 for a window. With such an arrangement, because the alloy film 15 does not have direct contact with the developing solution during the formation of the mask 17, the closeness of the alloy film and the mask 17 is not affected and the alloy wiring 18 having the same pattern as the mask 17 can be obtained. Thus by a good resist mask pattern an electrode wiring of high precision and high reliability can be obtained.
JP642880A 1980-01-23 1980-01-23 Preparation of semiconductor device Pending JPS56111246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP642880A JPS56111246A (en) 1980-01-23 1980-01-23 Preparation of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP642880A JPS56111246A (en) 1980-01-23 1980-01-23 Preparation of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56111246A true JPS56111246A (en) 1981-09-02

Family

ID=11638110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP642880A Pending JPS56111246A (en) 1980-01-23 1980-01-23 Preparation of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56111246A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715441A (en) * 1980-07-01 1982-01-26 Fujitsu Ltd Formation of aluminum interconnection
WO2006049736A1 (en) * 2004-10-27 2006-05-11 Lam Research Corporation Etching method including photoresist plasma conditioning step with hydrogen flow rate ramping

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5715441A (en) * 1980-07-01 1982-01-26 Fujitsu Ltd Formation of aluminum interconnection
WO2006049736A1 (en) * 2004-10-27 2006-05-11 Lam Research Corporation Etching method including photoresist plasma conditioning step with hydrogen flow rate ramping
US7682480B2 (en) 2004-10-27 2010-03-23 Lam Research Corporation Photoresist conditioning with hydrogen ramping

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