JPS5529181A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5529181A
JPS5529181A JP10325378A JP10325378A JPS5529181A JP S5529181 A JPS5529181 A JP S5529181A JP 10325378 A JP10325378 A JP 10325378A JP 10325378 A JP10325378 A JP 10325378A JP S5529181 A JPS5529181 A JP S5529181A
Authority
JP
Japan
Prior art keywords
electrode
film
covered
projected
projected electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10325378A
Other languages
Japanese (ja)
Inventor
Genichi Adachi
Nobuki Ibaraki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP10325378A priority Critical patent/JPS5529181A/en
Publication of JPS5529181A publication Critical patent/JPS5529181A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

PURPOSE: To increase the attachment strength of an electrode while sufficiently protecting the surface of a substrate by employing a procedure wherein when providing a projected electrode on a semiconductor substrate on which a given set of elements are formed, the whole surface including the projected electrode is covered with a fluorine resin and only the upper surface of the electrode is exposed.
CONSTITUTION: The order of the step of forming a projected electrode and the step of coating a fluorine resin film is reversed. An Al wiring 13 is first formed through a SiO2 film 12 on a semiconductor substrate 11 on which a given set of elements have been provided, and the entire surface is covered with a PSG film 14 by the CVD process. Then an opening is formed at the portion where the projected electrode has been provide and Cr and Cu are continuously vapor-deposited to provide an intermediate metal layer 15. By masking with a photoresist, a Cu electrode 16 is formed by electric plating. Thereafter, the entire surface is covered with a film 17 consisting of a fluorimated ethylene-propylene copolymer, and by providing an opening in an electrode region 16 by the O2 plasma method, the surface of the electrode 16 is exposed. This permits sufficient protection of the surface of the layer 14, and since the attachment force of the electrode 16 is independent from the film 17, it is strengthened.
COPYRIGHT: (C)1980,JPO&Japio
JP10325378A 1978-08-24 1978-08-24 Production of semiconductor device Pending JPS5529181A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10325378A JPS5529181A (en) 1978-08-24 1978-08-24 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10325378A JPS5529181A (en) 1978-08-24 1978-08-24 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5529181A true JPS5529181A (en) 1980-03-01

Family

ID=14349272

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10325378A Pending JPS5529181A (en) 1978-08-24 1978-08-24 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5529181A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57200591U (en) * 1981-06-12 1982-12-20
JPS60170246A (en) * 1984-02-15 1985-09-03 Toshiba Corp Semiconductor device and manufacture thereof
JPS62173740A (en) * 1986-01-27 1987-07-30 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPS63245942A (en) * 1987-03-31 1988-10-13 Nec Corp Semiconductor device
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US6229209B1 (en) 1995-02-23 2001-05-08 Matsushita Electric Industrial Co., Ltd. Chip carrier

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57200591U (en) * 1981-06-12 1982-12-20
JPS6217509Y2 (en) * 1981-06-12 1987-05-06
JPS60170246A (en) * 1984-02-15 1985-09-03 Toshiba Corp Semiconductor device and manufacture thereof
JPS62173740A (en) * 1986-01-27 1987-07-30 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPS63245942A (en) * 1987-03-31 1988-10-13 Nec Corp Semiconductor device
US5316974A (en) * 1988-12-19 1994-05-31 Texas Instruments Incorporated Integrated circuit copper metallization process using a lift-off seed layer and a thick-plated conductor layer
US6229209B1 (en) 1995-02-23 2001-05-08 Matsushita Electric Industrial Co., Ltd. Chip carrier
US6365499B1 (en) 1995-02-23 2002-04-02 Matsushita Electric Industrial Co., Ltd. Chip carrier and method of manufacturing and mounting the same
US6372547B2 (en) 1995-02-23 2002-04-16 Matsushita Electric Industrial Co., Ltd. Method for manufacturing electronic device with resin layer between chip carrier and circuit wiring board

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