JPS5730345A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5730345A
JPS5730345A JP10531180A JP10531180A JPS5730345A JP S5730345 A JPS5730345 A JP S5730345A JP 10531180 A JP10531180 A JP 10531180A JP 10531180 A JP10531180 A JP 10531180A JP S5730345 A JPS5730345 A JP S5730345A
Authority
JP
Japan
Prior art keywords
metal layer
pattern
whole surface
semiconductor substrate
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10531180A
Other languages
Japanese (ja)
Inventor
Hiroyuki Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP10531180A priority Critical patent/JPS5730345A/en
Publication of JPS5730345A publication Critical patent/JPS5730345A/en
Pending legal-status Critical Current

Links

Landscapes

  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Non-Volatile Memory (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

PURPOSE:To prevent the external light to come into the inner part of a semiconductor substrate by a method wherein an overetching is performed on an insulating film, using the Al wiring pattern selectively formed on the surface of the semiconductor substrate, and then a metal layer is coated on the whole surface of the substrate. CONSTITUTION:The insulating film 19 is formed on the semiconductor substrate 18 and successively an Al layer 20 is formed. Then, a desired pattern is formed using a resist 21, which is sensitive to an electron beam, light, X-rays and the like, and the unnecessary Al is removed in accordance with the said pattern. When a metal 22 such as Al, Cr, Au, Ti, Ni, and the like is evaporated on the whole surface after an overetching has been performed on the insulating layer 19 in accordance with the above pattern, breaking of wire is generated at the stepped section of the metal layer due to the big difference in level at the pattern edge section and a structure, the whole surface of which is covered by the metal layer, can be obtained without having a short-circuit between wirings. Through these procedures, as the whole surface of the substrate is covered by the metal layer of a high light absorbing factor, the incidence of external light can be prevented.
JP10531180A 1980-07-31 1980-07-31 Semiconductor device Pending JPS5730345A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10531180A JPS5730345A (en) 1980-07-31 1980-07-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10531180A JPS5730345A (en) 1980-07-31 1980-07-31 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5730345A true JPS5730345A (en) 1982-02-18

Family

ID=14404151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10531180A Pending JPS5730345A (en) 1980-07-31 1980-07-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5730345A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121082A (en) * 1982-12-22 1984-07-12 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Semiconductor integrated display and manufacture thereof
JPS63239842A (en) * 1986-11-05 1988-10-05 Nec Corp Manufacture of semiconductor device
US4818712A (en) * 1987-10-13 1989-04-04 Northrop Corporation Aluminum liftoff masking process and product
US7285817B2 (en) 2004-09-10 2007-10-23 Seiko Epson Corporation Semiconductor device
US20090039515A1 (en) * 2007-08-10 2009-02-12 International Business Machines Corporation Ionizing radiation blocking in ic chip to reduce soft errors

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538075A (en) * 1978-09-12 1980-03-17 Fujitsu Ltd Wiring

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5538075A (en) * 1978-09-12 1980-03-17 Fujitsu Ltd Wiring

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121082A (en) * 1982-12-22 1984-07-12 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Semiconductor integrated display and manufacture thereof
JPS63239842A (en) * 1986-11-05 1988-10-05 Nec Corp Manufacture of semiconductor device
US4818712A (en) * 1987-10-13 1989-04-04 Northrop Corporation Aluminum liftoff masking process and product
US7285817B2 (en) 2004-09-10 2007-10-23 Seiko Epson Corporation Semiconductor device
US20090039515A1 (en) * 2007-08-10 2009-02-12 International Business Machines Corporation Ionizing radiation blocking in ic chip to reduce soft errors
US8999764B2 (en) * 2007-08-10 2015-04-07 International Business Machines Corporation Ionizing radiation blocking in IC chip to reduce soft errors
US10784200B2 (en) 2007-08-10 2020-09-22 International Business Machines Corporation Ionizing radiation blocking in IC chip to reduce soft errors

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