JPS5793524A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5793524A
JPS5793524A JP17039780A JP17039780A JPS5793524A JP S5793524 A JPS5793524 A JP S5793524A JP 17039780 A JP17039780 A JP 17039780A JP 17039780 A JP17039780 A JP 17039780A JP S5793524 A JPS5793524 A JP S5793524A
Authority
JP
Japan
Prior art keywords
film
alloyed
substrate
etching
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17039780A
Other languages
Japanese (ja)
Other versions
JPS6328336B2 (en
Inventor
Akira Abiru
Yoshiaki Tanimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17039780A priority Critical patent/JPS5793524A/en
Publication of JPS5793524A publication Critical patent/JPS5793524A/en
Publication of JPS6328336B2 publication Critical patent/JPS6328336B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • ing And Chemical Polishing (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain an electrode wiring pattern without the use of a photo resist by subjecting an Al film and a Cu film to laminate forming on a part obtained by providing a window through a PSG film on a substrate, by alloying a desired part with an electron beam and by removing a metal film not alloyed by etching. CONSTITUTION:A PSG film 7 is deposited on an Si substrate 6 obtained by forming a field oxide film 1, an S region 2, a D region 3, a gate oxide film 4 and a gate electrode 5 thereon, and a hole A for connection is bored as a window. An Al layer 8 is evaporated on a substrate, and a metal film 9 of Cu is subjected to laminate forming on said layer 8. Said film 9 is irradiated with an electron beam into a prescribed pattern, and Al is alloyed with Cu. The substrate is subjected to etching using ammonia, and Cu not alloyed is removed. Al is removed by plasma etching taking a part alloyed as a mask, and Al-Cu alloy electrode having a prescribed pattern is obtained. Hereby, an electrode wiring pattern is formed with a simple process without the use of a photo resist film.
JP17039780A 1980-12-03 1980-12-03 Manufacture of semiconductor device Granted JPS5793524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17039780A JPS5793524A (en) 1980-12-03 1980-12-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17039780A JPS5793524A (en) 1980-12-03 1980-12-03 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5793524A true JPS5793524A (en) 1982-06-10
JPS6328336B2 JPS6328336B2 (en) 1988-06-08

Family

ID=15904164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17039780A Granted JPS5793524A (en) 1980-12-03 1980-12-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5793524A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55130141A (en) * 1979-03-30 1980-10-08 Fujitsu Ltd Fabricating method of semiconductor device
JPS56158454A (en) * 1980-05-12 1981-12-07 Mitsubishi Electric Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55130141A (en) * 1979-03-30 1980-10-08 Fujitsu Ltd Fabricating method of semiconductor device
JPS56158454A (en) * 1980-05-12 1981-12-07 Mitsubishi Electric Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS6328336B2 (en) 1988-06-08

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