JPS642339A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS642339A
JPS642339A JP62158064A JP15806487A JPS642339A JP S642339 A JPS642339 A JP S642339A JP 62158064 A JP62158064 A JP 62158064A JP 15806487 A JP15806487 A JP 15806487A JP S642339 A JPS642339 A JP S642339A
Authority
JP
Japan
Prior art keywords
aperture
insulating film
film
bump
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62158064A
Other languages
Japanese (ja)
Other versions
JPH012339A (en
Inventor
Yoshiyuki Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62-158064A priority Critical patent/JPH012339A/en
Priority claimed from JP62-158064A external-priority patent/JPH012339A/en
Publication of JPS642339A publication Critical patent/JPS642339A/en
Publication of JPH012339A publication Critical patent/JPH012339A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125—Reinforcing structures
    • H01L2224/10126—Bump collar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To make the external force to be applied to a bump uniform and to prevent the bump from peeling at the time of bonding by a method wherein an organic insulating film having an aperture is provided on an electrode pad and a metal-plated layer is provided in the aperture of the organic insulating film to form the bump.
CONSTITUTION: A metal layer is deposited on an insulating film 2 provided on a semiconductor substrate 1 and an etching is selectively performed to form an electrode pad 3. Then, an interlayer insulating film 4 is deposited and an etching is selectively performed to form an aperture 5. Then, an intermediate metal layer 6 is laminated and moreover, an organic insulating film (a polyimide resin film) 7 and photo resist films 8 are provided to perform a patterning. Then, an etching is selectively performed using the films 8 as masks to form an aperture 9 larger slightly than the aperture 5 including the aperture 5 and to expose the layer 6 on the outside of the pad 3. Then, a photo resist film 10 is provided on the whole surface to perform a patterning, an aperture 11 larger than the aperture 9 is provided to cover the layer 6 on the outside of the pad 3, then a bump 12 is formed and a metal layer 13 is provided to remove the resist 10 and to cover the end parts of the film 6 with the film 7.
COPYRIGHT: (C)1989,JPO&Japio
JP62-158064A 1987-06-24 Manufacturing method of semiconductor device Pending JPH012339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-158064A JPH012339A (en) 1987-06-24 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-158064A JPH012339A (en) 1987-06-24 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS642339A true JPS642339A (en) 1989-01-06
JPH012339A JPH012339A (en) 1989-01-06

Family

ID=

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04278543A (en) * 1991-03-07 1992-10-05 Nec Corp Semiconductor device and manufacture thereof
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
US5773899A (en) * 1993-09-30 1998-06-30 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Bonding pad for a semiconductor chip
US6593220B1 (en) * 2002-01-03 2003-07-15 Taiwan Semiconductor Manufacturing Company Elastomer plating mask sealed wafer level package method
WO2014070926A1 (en) * 2012-11-02 2014-05-08 Qualcomm Incorporated A conductive interconnect including an inorganic collar

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5244833A (en) * 1989-07-26 1993-09-14 International Business Machines Corporation Method for manufacturing an integrated circuit chip bump electrode using a polymer layer and a photoresist layer
JPH04278543A (en) * 1991-03-07 1992-10-05 Nec Corp Semiconductor device and manufacture thereof
US5773899A (en) * 1993-09-30 1998-06-30 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Bonding pad for a semiconductor chip
US5869357A (en) * 1993-09-30 1999-02-09 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Metallization and wire bonding process for manufacturing power semiconductor devices
US6593220B1 (en) * 2002-01-03 2003-07-15 Taiwan Semiconductor Manufacturing Company Elastomer plating mask sealed wafer level package method
WO2014070926A1 (en) * 2012-11-02 2014-05-08 Qualcomm Incorporated A conductive interconnect including an inorganic collar

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