JPS5768035A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5768035A
JPS5768035A JP14392580A JP14392580A JPS5768035A JP S5768035 A JPS5768035 A JP S5768035A JP 14392580 A JP14392580 A JP 14392580A JP 14392580 A JP14392580 A JP 14392580A JP S5768035 A JPS5768035 A JP S5768035A
Authority
JP
Japan
Prior art keywords
layer
film
etched
metallic
metallic layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14392580A
Other languages
Japanese (ja)
Inventor
Shinobu Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14392580A priority Critical patent/JPS5768035A/en
Publication of JPS5768035A publication Critical patent/JPS5768035A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To accurately form the desired tapering angle of the first metallic layer forming the multilayer wire of a semconductor device by forming in advance a hole for controlling the tapering angle at the second metallic layer when the first layer is etched to form a taper. CONSTITUTION:An oxidized film 12 is covered on a semiconductor substrate 11, holes are opened correspondingly to the base, emitter and collector regions a1-c1 formed on the sunstrate 11, and the metallic layer 13 of the first layer wire made of aluminum or Si-Cu alloy covered on the overall surface. Then, the second metallic layer 14 made of Mo or the like having faster etching rate and good adherence than the layer 13 is laminated under the same conditions, and a photoresist film 15a having holes corresponding to the electrode forming parts is formed thereon. Subsequently, only the exposed part of the layer 14 is etched and removed, unnecessary film 15a is removed, and resist film 15b of the prescribed pattern is formed while burying the exposed part of the layer 13. Then, with the film as a mask the layer 14 and then the layer 13 are etched to sidewisely etch only the layer 14, and the layer 13 having a desired taper can be obtained.
JP14392580A 1980-10-15 1980-10-15 Manufacture of semiconductor device Pending JPS5768035A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14392580A JPS5768035A (en) 1980-10-15 1980-10-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14392580A JPS5768035A (en) 1980-10-15 1980-10-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5768035A true JPS5768035A (en) 1982-04-26

Family

ID=15350278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14392580A Pending JPS5768035A (en) 1980-10-15 1980-10-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5768035A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136935A (en) * 1983-01-27 1984-08-06 Nec Corp Manufacture of semiconductor device
US4943539A (en) * 1989-05-09 1990-07-24 Motorola, Inc. Process for making a multilayer metallization structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136935A (en) * 1983-01-27 1984-08-06 Nec Corp Manufacture of semiconductor device
JPH0148652B2 (en) * 1983-01-27 1989-10-20 Nippon Electric Co
US4943539A (en) * 1989-05-09 1990-07-24 Motorola, Inc. Process for making a multilayer metallization structure

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