JPS57208145A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57208145A
JPS57208145A JP9314481A JP9314481A JPS57208145A JP S57208145 A JPS57208145 A JP S57208145A JP 9314481 A JP9314481 A JP 9314481A JP 9314481 A JP9314481 A JP 9314481A JP S57208145 A JPS57208145 A JP S57208145A
Authority
JP
Japan
Prior art keywords
film
etched
plasma sin
pattern
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9314481A
Other languages
Japanese (ja)
Inventor
Masaaki Inada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9314481A priority Critical patent/JPS57208145A/en
Publication of JPS57208145A publication Critical patent/JPS57208145A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To facilitate forming of fine wirings and to improve integration degree as well as reliability by a method wherein the pattern dimension is determined based on a side-etching amount of a plasma SiN film. CONSTITUTION:An Al film 2 is coated on a semiconductor film 1 and a plasma SiN film 3 is coat4d thereon. Then, a photoregist film 4 is applied in the desired pattern and the film 3 is etched using the film 4 as a mask. Then, only the surface of the Al film 2 is transformed using both plasma SiN film 5 and film 4 as masks. Then, the film 5 is side-etched using the film 4 as a mask to expose the Al film and subsequently the film 4 is removed. Then, thus exposed Al film is etched to be removed using a transformed film 6 and a side-etched plasma SiN film 5' as masks. Then, a metal is applied all over the surface so as to coat metal films separated completely from one another with a pattern 7 in the form eaves. Then, the metal 8 is removed concurrently at the time of etching the Al film, so that a metal pattern 8' is attained which has a dimension corresponding to an side-etching amount of the plasma SiN film.
JP9314481A 1981-06-17 1981-06-17 Manufacture of semiconductor device Pending JPS57208145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9314481A JPS57208145A (en) 1981-06-17 1981-06-17 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9314481A JPS57208145A (en) 1981-06-17 1981-06-17 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS57208145A true JPS57208145A (en) 1982-12-21

Family

ID=14074329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9314481A Pending JPS57208145A (en) 1981-06-17 1981-06-17 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS57208145A (en)

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