JPS5460582A - Electrode wiring and its forming method in semiconductor device - Google Patents

Electrode wiring and its forming method in semiconductor device

Info

Publication number
JPS5460582A
JPS5460582A JP12683877A JP12683877A JPS5460582A JP S5460582 A JPS5460582 A JP S5460582A JP 12683877 A JP12683877 A JP 12683877A JP 12683877 A JP12683877 A JP 12683877A JP S5460582 A JPS5460582 A JP S5460582A
Authority
JP
Japan
Prior art keywords
film
groove
wiring
electrode wiring
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12683877A
Other languages
Japanese (ja)
Other versions
JPS6041461B2 (en
Inventor
Tatsu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12683877A priority Critical patent/JPS6041461B2/en
Publication of JPS5460582A publication Critical patent/JPS5460582A/en
Publication of JPS6041461B2 publication Critical patent/JPS6041461B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To aviod the incomplete coat of the wiring protective film by forming the gold plated wiring layer within the groove of the insulating film and securing a flat electrode wiring structure.
CONSTITUTION: Si3N47 is laminated on SiO24 after formation of the element region, and platinum silicide layer 8 is formed with the opening drilled. The coat of PSG9 is given, and groove 10 and 11 are provided into the wiring pattern. Then PIQ14a and 14b are formed within the groove after coating with Ti12 and pt13. The exposed film 13 is removed via PIQ mask, and then PIQ is removed via resist mask 15. An electroplating is given via film 12 to form gold layer 16a and 16b on exposed film 13 within the groove. The plate mask 15 is then removed and the Ti film on film 9 is etched away. Thus, the electrode wiring of gold is formed buried within the groove. Then SiO217 is coated. In this constitution, film 17 can be formed easily and assuredly owing to the flat surface, and also the gold plated wiring pattern can be formed in a micro size
COPYRIGHT: (C)1979,JPO&Japio
JP12683877A 1977-10-24 1977-10-24 Method for forming electrode wiring in semiconductor devices Expired JPS6041461B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12683877A JPS6041461B2 (en) 1977-10-24 1977-10-24 Method for forming electrode wiring in semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12683877A JPS6041461B2 (en) 1977-10-24 1977-10-24 Method for forming electrode wiring in semiconductor devices

Publications (2)

Publication Number Publication Date
JPS5460582A true JPS5460582A (en) 1979-05-16
JPS6041461B2 JPS6041461B2 (en) 1985-09-17

Family

ID=14945136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12683877A Expired JPS6041461B2 (en) 1977-10-24 1977-10-24 Method for forming electrode wiring in semiconductor devices

Country Status (1)

Country Link
JP (1) JPS6041461B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582044A (en) * 1981-06-26 1983-01-07 Seiko Epson Corp Manufacture of semiconductor device
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
US5059555A (en) * 1990-08-20 1991-10-22 National Semiconductor Corporation Method to fabricate vertical fuse devices and Schottky diodes using thin sacrificial layer

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04114962U (en) * 1991-03-27 1992-10-12 アイホン株式会社 Opening/closing structure of the housing door

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582044A (en) * 1981-06-26 1983-01-07 Seiko Epson Corp Manufacture of semiconductor device
JPH0423417B2 (en) * 1981-06-26 1992-04-22 Seiko Epson Corp
US4822753A (en) * 1988-05-09 1989-04-18 Motorola, Inc. Method for making a w/tin contact
US5059555A (en) * 1990-08-20 1991-10-22 National Semiconductor Corporation Method to fabricate vertical fuse devices and Schottky diodes using thin sacrificial layer

Also Published As

Publication number Publication date
JPS6041461B2 (en) 1985-09-17

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