JPS5555546A - Method of wiring semiconductor device - Google Patents

Method of wiring semiconductor device

Info

Publication number
JPS5555546A
JPS5555546A JP12783378A JP12783378A JPS5555546A JP S5555546 A JPS5555546 A JP S5555546A JP 12783378 A JP12783378 A JP 12783378A JP 12783378 A JP12783378 A JP 12783378A JP S5555546 A JPS5555546 A JP S5555546A
Authority
JP
Japan
Prior art keywords
layer
exposed surface
sio
semiconductor device
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12783378A
Other languages
Japanese (ja)
Inventor
Iwao Yamazaki
Junichi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12783378A priority Critical patent/JPS5555546A/en
Publication of JPS5555546A publication Critical patent/JPS5555546A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To improve the reliability of a semiconductor device by coating a conductive member layer in thickness deeper than the groove of a wiring pattern and cuttinh the exposed surface to the degree coincident to an insulating layer.
CONSTITUTION: An opening 3 is formed at a SiO2 layer 2 on a silicon substrate 1, and a wiring metal layer is deposited thereon to thereby form a wiring pattern 24. The exposed surface is lapped to be equalized to the exposed surface of an electric insulating layer. Then, SiO2 layer 22 is coated on the exposed surface, SiO2 layer 32 is further coated thereon, and second wiring metal layer is formed in predetermined shape of groove pattern.
COPYRIGHT: (C)1980,JPO&Japio
JP12783378A 1978-10-19 1978-10-19 Method of wiring semiconductor device Pending JPS5555546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12783378A JPS5555546A (en) 1978-10-19 1978-10-19 Method of wiring semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12783378A JPS5555546A (en) 1978-10-19 1978-10-19 Method of wiring semiconductor device

Publications (1)

Publication Number Publication Date
JPS5555546A true JPS5555546A (en) 1980-04-23

Family

ID=14969782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12783378A Pending JPS5555546A (en) 1978-10-19 1978-10-19 Method of wiring semiconductor device

Country Status (1)

Country Link
JP (1) JPS5555546A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59940A (en) * 1982-06-25 1984-01-06 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPS62102545A (en) * 1985-10-28 1987-05-13 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Formation of conductor pattern

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59940A (en) * 1982-06-25 1984-01-06 Agency Of Ind Science & Technol Manufacture of semiconductor device
JPS62102545A (en) * 1985-10-28 1987-05-13 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Formation of conductor pattern

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