JPS56150831A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56150831A
JPS56150831A JP5466980A JP5466980A JPS56150831A JP S56150831 A JPS56150831 A JP S56150831A JP 5466980 A JP5466980 A JP 5466980A JP 5466980 A JP5466980 A JP 5466980A JP S56150831 A JPS56150831 A JP S56150831A
Authority
JP
Japan
Prior art keywords
film
wiring
substrate
oxide film
wiring passage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5466980A
Other languages
Japanese (ja)
Inventor
Masaharu Yorikane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5466980A priority Critical patent/JPS56150831A/en
Publication of JPS56150831A publication Critical patent/JPS56150831A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To enable to obtain the wiring passage having a stabilized excellent electric connection by a method wherein an interlayer insulating layer is constituted by an Si oxide film and an Si nitriding film. CONSTITUTION:An Si oxide film 302 is coated on the surface of an Si substrate 301. An aperture 303 is provided on the film 302 and a wiring passage 304 is formed adjoining to the aperture 303. Then, an Si oxide film 305 and an Si nitride film 306 are coated on the substrate 301 successively. Then, the film 306 is selectively removed down to the film 305 by performing an etching. With the etching performed at this time, the speed of etching performed on the Si oxide film is sufficiently slow as compared with the Si nitriding film, so the surface of the wiring passage 304 is not exposed while the film 306 is being etched. Then, the film 304 is etched as deep as to the wiring 304. Then, photoresist is exfoliated and a wiring 308 is formed on the substrate 301 including the conducting hole 307. As a result, the conductive hole having a stabilized and excellent electric connection can be obtained.
JP5466980A 1980-04-24 1980-04-24 Semiconductor device Pending JPS56150831A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5466980A JPS56150831A (en) 1980-04-24 1980-04-24 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5466980A JPS56150831A (en) 1980-04-24 1980-04-24 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56150831A true JPS56150831A (en) 1981-11-21

Family

ID=12977177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5466980A Pending JPS56150831A (en) 1980-04-24 1980-04-24 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56150831A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5135292A (en) * 1974-09-20 1976-03-25 Matsushita Electric Ind Co Ltd Handotaisochi oyobi sonoseizohoho
JPS52104062A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Production of surface protection film of electronic parts
JPS5455388A (en) * 1977-10-12 1979-05-02 Matsushita Electric Ind Co Ltd Production of mos type semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5135292A (en) * 1974-09-20 1976-03-25 Matsushita Electric Ind Co Ltd Handotaisochi oyobi sonoseizohoho
JPS52104062A (en) * 1976-02-27 1977-09-01 Hitachi Ltd Production of surface protection film of electronic parts
JPS5455388A (en) * 1977-10-12 1979-05-02 Matsushita Electric Ind Co Ltd Production of mos type semiconductor device

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