JPS57177558A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS57177558A JPS57177558A JP6214381A JP6214381A JPS57177558A JP S57177558 A JPS57177558 A JP S57177558A JP 6214381 A JP6214381 A JP 6214381A JP 6214381 A JP6214381 A JP 6214381A JP S57177558 A JPS57177558 A JP S57177558A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- laminated
- etching
- coated
- auxiliary layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 238000005530 etching Methods 0.000 abstract 5
- 239000000945 filler Substances 0.000 abstract 3
- 101000617723 Homo sapiens Pregnancy-specific beta-1-glycoprotein 8 Proteins 0.000 abstract 2
- 102100022018 Pregnancy-specific beta-1-glycoprotein 8 Human genes 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 239000000654 additive Substances 0.000 abstract 1
- 230000000996 additive effect Effects 0.000 abstract 1
- 238000005260 corrosion Methods 0.000 abstract 1
- 230000007797 corrosion Effects 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To provide the electrode structure and the multilayer wiring with high reliability by a method wherein the auxiliary layer with high etching ratio is laminated on the conductive layer coated with an insulating film with a hole opened down to the conductive layer which is simultaneously coated with the filler layer to be etched at low etching ratio and after removing said auxiliary layer coated with said filler layer by means of etching, further laminated on another conductive layer. CONSTITUTION:The MOSFET is formed on the P type Si substrate 1 as usual and coated with PSG8. Then the Si auxiliary layer 9 added with phosphorus is laminated on the MOSFET and after forming an electrode hole, the poly Si 10 without the additive and with th same thickness as the width of said hole is laminated by means of the CVD process. The auxiliary layer 9 with high etching ratio prevents the etching speed from being accelerated abruptly by means of the CCl4 reacting ion etching making the filler layer 10 flush with the layer 8. Next Al 11 is, after evaporation and patterning, low temperature processed in N2+H2 to be alloyed. In this constitution, Al 11 may be formed into a fine electrode with high reliability because it is never disconnected without corrosion due to the application of PSG8 with low concentration.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6214381A JPS57177558A (en) | 1981-04-24 | 1981-04-24 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6214381A JPS57177558A (en) | 1981-04-24 | 1981-04-24 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57177558A true JPS57177558A (en) | 1982-11-01 |
Family
ID=13191574
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6214381A Pending JPS57177558A (en) | 1981-04-24 | 1981-04-24 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57177558A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62176147A (en) * | 1985-10-03 | 1987-08-01 | ビュル エス.アー. | Method for forming multilayer metal wiring network for mutual connection between components ofhigh density integrated circuit and integrated circuit formed by the method |
JPH01102938A (en) * | 1987-09-25 | 1989-04-20 | American Teleph & Telegr Co <Att> | Manufacture of semiconductor integrated circuit |
JPH0634965U (en) * | 1992-09-09 | 1994-05-10 | 本村製本株式会社 | Book |
US8640973B2 (en) | 2006-09-07 | 2014-02-04 | Briggs And Stratton Corporation | Pressure washer wand having a nozzle selector |
-
1981
- 1981-04-24 JP JP6214381A patent/JPS57177558A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62176147A (en) * | 1985-10-03 | 1987-08-01 | ビュル エス.アー. | Method for forming multilayer metal wiring network for mutual connection between components ofhigh density integrated circuit and integrated circuit formed by the method |
JPH01102938A (en) * | 1987-09-25 | 1989-04-20 | American Teleph & Telegr Co <Att> | Manufacture of semiconductor integrated circuit |
JPH0634965U (en) * | 1992-09-09 | 1994-05-10 | 本村製本株式会社 | Book |
US8640973B2 (en) | 2006-09-07 | 2014-02-04 | Briggs And Stratton Corporation | Pressure washer wand having a nozzle selector |
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