JPS57181123A - Manufcture of semiconductor device - Google Patents
Manufcture of semiconductor deviceInfo
- Publication number
- JPS57181123A JPS57181123A JP6595781A JP6595781A JPS57181123A JP S57181123 A JPS57181123 A JP S57181123A JP 6595781 A JP6595781 A JP 6595781A JP 6595781 A JP6595781 A JP 6595781A JP S57181123 A JPS57181123 A JP S57181123A
- Authority
- JP
- Japan
- Prior art keywords
- taper
- oxide film
- shaped
- etching
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 238000005530 etching Methods 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
PURPOSE:To form the opening section of an insulating film having a taper by conducting dry etching by using a mask having a taper. CONSTITUTION:A SiO2 layer 32 is formed onto a Si substrate 31, and a resist 33 is shaped as a lift-off material. A SiO2 layer 34 is further shaped through plasma CVD, but the layer 34 is formed as shown in (b) when the surface is etched by HF because the speed of etching is faster in a section A through the method. When the resist 33 is remoed, the oxide film 34 is also removed. When the whole surface is etched by RIE, the opening section is widened as shown in (e) with the progress of etching because the taper is formed in the oxide film 34 as the mask while the thickness of the oxide film 34 is also decreased gradually. The opening is formed as shown in (d), and a wiring layer having high reliability free of steo disconnection is shaped when Al 35 is evaporated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6595781A JPS57181123A (en) | 1981-04-30 | 1981-04-30 | Manufcture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6595781A JPS57181123A (en) | 1981-04-30 | 1981-04-30 | Manufcture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57181123A true JPS57181123A (en) | 1982-11-08 |
Family
ID=13301968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6595781A Pending JPS57181123A (en) | 1981-04-30 | 1981-04-30 | Manufcture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57181123A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59104130A (en) * | 1982-12-07 | 1984-06-15 | Fujitsu Ltd | Formation of fine pattern |
-
1981
- 1981-04-30 JP JP6595781A patent/JPS57181123A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59104130A (en) * | 1982-12-07 | 1984-06-15 | Fujitsu Ltd | Formation of fine pattern |
| JPH0473290B2 (en) * | 1982-12-07 | 1992-11-20 | Fujitsu Ltd |
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