JPS57164563A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS57164563A
JPS57164563A JP55175648A JP17564880A JPS57164563A JP S57164563 A JPS57164563 A JP S57164563A JP 55175648 A JP55175648 A JP 55175648A JP 17564880 A JP17564880 A JP 17564880A JP S57164563 A JPS57164563 A JP S57164563A
Authority
JP
Japan
Prior art keywords
layer
polycrystal
etching
electrode
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55175648A
Other languages
Japanese (ja)
Other versions
JPS5953710B2 (en
Inventor
Keiji Nishimoto
Masanao Itoga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55175648A priority Critical patent/JPS5953710B2/en
Publication of JPS57164563A publication Critical patent/JPS57164563A/en
Publication of JPS5953710B2 publication Critical patent/JPS5953710B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To avoid short circuit between electrodes when multi-layer electrodes of polycrystal Si is manufactured by a method wherein residual polycrystal Si layer adhering to the end of a lower layer polycrystal Si electrode of the region which corresponds to the gap portion of an upper layer polycrystal Si electrode is separated and removed by etching. CONSTITUTION:A thin SiO2 film for etching stopper is formed and then the first polycrystal Si layer 16' is formed on an Si substrate on which a field oxide film 11 has been formed. Then an SiO2 film 17 for layer insulation is formed by thermal oxidation of the surface of the layer 16' and resist pattern 19 is formed on the surface. Then the film 17 and the polycrystal Si 16 are removed by wet- etching with HF and by dry-etching with plasma. After that a thin SiO2 film 22 of thickness approximately 1,000Angstrom is formed on the end surface of the lower layer polycrystal Si electrode 16' and the second polycrystal Si layer 23 is piled on the whole surface. Finally the polycrystal Si layer 23 is patterned and the required multi-layer electrodes composition is obtained.
JP55175648A 1980-12-12 1980-12-12 Manufacturing method of semiconductor device Expired JPS5953710B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55175648A JPS5953710B2 (en) 1980-12-12 1980-12-12 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55175648A JPS5953710B2 (en) 1980-12-12 1980-12-12 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS57164563A true JPS57164563A (en) 1982-10-09
JPS5953710B2 JPS5953710B2 (en) 1984-12-26

Family

ID=15999763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55175648A Expired JPS5953710B2 (en) 1980-12-12 1980-12-12 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5953710B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142531U (en) * 1984-02-28 1985-09-20 株式会社明電舎 Gate turn-off thyristor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60142531U (en) * 1984-02-28 1985-09-20 株式会社明電舎 Gate turn-off thyristor
JPH0448024Y2 (en) * 1984-02-28 1992-11-12

Also Published As

Publication number Publication date
JPS5953710B2 (en) 1984-12-26

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