JPS5953710B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for preventing short circuits between upper polycrystalline silicon electrodes when manufacturing a semiconductor device having a multilayer structure of polycrystalline silicon electrodes.

A multilayer structure of polycrystalline silicon electrodes is often used in semiconductor integrated circuit devices such as random access memories (RAMs).

In these semiconductor integrated circuit devices, when forming polycrystalline silicon electrodes in multiple layers, conventionally, a lower layer electrode is formed of a first polycrystalline silicon layer whose surface is covered with an insulating film such as silicon dioxide (SiO0). Then, a second polycrystalline silicon layer is deposited, and the second polycrystalline silicon layer is selectively etched using, for example, a reactive sputter etching method with high etching accuracy, so that the end face of the lower polycrystalline silicon electrode is etched. Then, by separating the insulating film, for example, two parallel strip-shaped upper polycrystalline silicon electrodes intersecting at right angles were formed. However, in the conventional method, the cross-sectional view of FIG.
As shown in Figure b, SiO is deposited on the lower polycrystalline silicon electrode 1 made of the first polycrystalline silicon layer.

Upper polycrystalline silicon electrodes 3a and 3b are formed of a second polycrystalline silicon layer having, for example, two strips parallel to each other and perpendicular to the end surface of the lower polycrystalline silicon electrode 1, with the film 2 separated.
When forming using a reactive sputter etching method, etching is performed under conditions suitable for the thickness of the second polycrystalline silicon layer to form a lower polycrystalline silicon electrode between upper polycrystalline silicon electrodes 3a and 3b. SiO on 1. In the state where the film 2 is exposed, the second polycrystalline silicon layer formed on the end surface of the polycrystalline silicon electrode 1 beneath the upper polycrystalline silicon electrodes 3a and 3b cannot be completely removed; The remaining polycrystalline silicon layer 4 of No. 2 remains. This is because the vertical thickness of the second polycrystalline silicon layer at the end face of the lower polycrystalline silicon electrode 1 is large, and this is due to the reactivity that has an etching direction perpendicular to the surface of the substrate to be processed. This phenomenon is unavoidable as long as sputter etching is used.
The second residual polycrystalline silicon layer 4 causes a short circuit between the upper polycrystalline silicon electrodes 3a and 3b, impairing the performance of the device.
The second remaining polycrystalline silicon layer 4 was removed under a large over-etching condition when patterning the second polycrystalline silicon layer 4. (In FIGS. 1a and 1b, 6 indicates a field insulating film made of silicon dioxide (SiO2), 7 indicates a gate insulating film also made of silicon dioxide, 8 indicates a channel cut region, and 9 indicates a silicon substrate.) Even with this kind of over-etching,
The second polycrystalline silicon residual layer 4 filling the undercut portion 5 formed at the bottom of the lower polycrystalline silicon electrode 1 remains, which causes the problem of lowering the manufacturing yield of semiconductor integrated circuit devices. Moreover, when the above-mentioned large over-etching is performed, the mask pattern made of photoresist is also etched and becomes thinner, so that the upper layer polycrystalline silicon electrodes 3a and 3b having the desired width can be formed.
In order to form this, it is necessary to form a mask pattern having a wider width in advance, which poses a problem in that the degree of integration of the element is reduced. In view of the above-mentioned problems, the present invention provides an etching step for preliminarily dividing and removing the second residual polycrystalline silicon layer adhering to the end surface of the lower polycrystalline silicon electrode in the region corresponding to the gap between the upper polycrystalline silicon electrodes, Provided is a method for manufacturing a semiconductor device that prevents short circuits between upper layer polycrystalline silicon electrodes that will be patterned in subsequent steps.

That is, the present invention provides a method for manufacturing a semiconductor device, in which a lower electrode made of a first polycrystalline silicon layer whose surface is covered with an insulating film is formed on an insulating film provided on a surface of a semiconductor substrate, and then the A second polycrystalline silicon layer is deposited on an insulating film covering the first polycrystalline silicon layer, and then a second polycrystalline silicon layer is formed using the second polycrystalline silicon layer. forming a photoresist pattern having an etching window across the end surface of the lower electrode in a region corresponding to the gap between the plurality of parallel stripes of the upper electrode intersecting the end surface of the lower electrode; Using the photoresist pattern as a mask, the second polycrystalline silicon layer exposed within the etching window of the photoresist pattern is selectively etched away, and then the second polycrystalline silicon layer is patterned. The method is characterized by comprising the step of forming an upper layer electrode.

The present invention will be described in detail below with reference to process sectional views of an embodiment shown in FIGS. 2a to 2e and process top views of the same embodiment shown in FIGS. 3a to 3d.

In order to form a semiconductor device having a multilayer structure of polycrystalline silicon electrodes using the method of the present invention, for example, a conventional method is used to form a field silicon dioxide (SiO2) film 11 and a channel.・Silicon (Si) with element formation region 13 separated by cut region 12
On the element formation region 13 of the substrate to be processed consisting of the substrate 14,
First, a thin SiO2 film 15 for an etching stopper with a thickness of about 5,000 to 1,000 layers is formed using a thermal oxidation method, and then a thin SiO2 film 15 with a thickness of about 4,000 to 1,000 layers is formed on the substrate to be processed using a chemical vapor deposition (CVD) method. The first polycrystalline silicon layer 16 is deposited to a thickness of about 5,000 [people], and then the surface of the first polycrystalline silicon layer 16 is thermally oxidized to form a layer of about 2,000 [people] thick on the first polycrystalline silicon layer 16. A SiO2 film 17 for interlayer insulation of about 2,500 [persons] is formed.

Next, as shown in FIG. 2b and FIG. 3a, a photoresist pattern 19 is formed on the interlayer insulating SiO2 film 17 to cover the lower electrode formation region 18, and the photoresist pattern 19 is masked. First, the surface of the substrate to be processed is treated with a hydrofluoric acid (HF) based etching solution to dissolve and remove the interlayer insulating SiO2 film 17 in the area exposed from the photo register pattern 19. Plasma etching is performed using an etching gas made of carbon fluoride (CF4), etc., and the first polycrystalline silicon layer 16 exposed in the above process is etched away, and an SiO2 film 17 for interlayer insulation is formed on the upper layer. After forming a lower polycrystalline silicon electrode (drain electrode) 16'' consisting of a polycrystalline silicon layer 16 having
Dissolve and remove. As shown in the figure, due to the side etching during the plasma etching, the end surface of the lower polycrystalline silicon electrode 16'' is exposed to the interlayer insulating SiO2 film 17.
is formed slightly backward from the end face of the element forming region 13.
When removing the thin SiO2 film 15, a shallow undercut 20 is formed at the bottom of the end face of the lower polycrystalline silicon electrode 16''.Then, as shown in FIGS. 2C and 3B, the photoresist film 16 is removed. The substrate to be processed from which the pattern has been removed is thermally oxidized to form a gate SiO2 film 21 on the semiconductor substrate surface exposed in the element formation region 13. At the same time, 1000 [people] After forming a relatively thin SiO2 film 22, a second polycrystalline silicon layer 23 having a thickness of approximately 4,000 to 5,000 layers is deposited on the substrate to be processed using the CVD method.

Then, using a normal photo process, a region corresponding to the gap between two parallel upper polycrystalline silicon electrodes formed by the second polycrystalline silicon layer 23 is formed on the second polycrystalline silicon layer 23. In the above, the interlayer insulation SiO2
A photoresist pattern 26 having a desired length of, for example, a rectangular etched window 25 across the end surface 24 of the membrane 17 is formed. Thereafter, the second polycrystalline silicon layer 23 exposed within the etching window 25 is selectively etched away by a normal plasma etching method using an etching gas such as CF4. 3
As shown in FIG. , and a rectangular window 27, for example, exposing the field SiO2 film 11. Next, on the second polycrystalline silicon layer 23, an end surface of the lower polycrystalline silicon electrode 16'' is formed with the rectangular window 27 in between. For example, after forming two parallel photoresist patterns that intersect at right angles, a reactive sputtering process is performed using a chlorine-based etching gas such as carbon tetrachloride (CCl4) using the photoresist pattern as a mask.・The second polycrystalline silicon layer is patterned by etching, and as shown in FIG. 2e and FIG. Separate the SiO2 film 22 and form two parallel upper polycrystalline silicon electrodes (
Gate electrodes) 28a and 28b are formed.

After the patterning of the upper polycrystalline silicon electrodes 28a and 28b is completed, the lower polycrystalline silicon electrode 16'' covered with the thin SiO2 film 22 is placed at the end of the interlayer insulating SiO2 film 17 as described above. The second polycrystalline silicon residual layer 23'' remains at the end portion of the upper layer and the undercut portion 20 at the bottom of the end surface, but in this embodiment, the upper polycrystalline silicon electrode is formed by the rectangular window 27 as described above. Since the second polycrystalline silicon layer 23 in the region between 28a and 28b including a part of the end face of the lower polycrystalline silicon electrode 16'' has been removed in advance, the second polycrystalline silicon residual layer is left in this region. 23'' is not formed, therefore, as shown in the figure, a cutout portion 29 is formed in the second polycrystalline silicon residual layer 23'' formed between the upper layer polycrystalline silicon electrodes 28a and 28b. A short circuit between crystalline silicon electrodes 28a and 28b is prevented.

As explained above, according to the present invention, in the manufacturing process of a semiconductor device having a multilayer structure of polycrystalline silicon electrodes, a large overetching process is performed when patterning an upper layer polycrystalline silicon electrode. Since short circuits between upper layer polycrystalline silicon interconnections are completely prevented without
It is possible to improve the manufacturing yield and degree of integration of semiconductor integrated circuit devices having a polycrystalline silicon electrode multilayer structure such as the above.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view a of a semiconductor device having a multilayer structure of polycrystalline silicon electrodes formed by a conventional method, and a cross-sectional view b taken along the line A-N, and FIGS. In the process sectional views, FIGS. 3A to 3D are process top views in the same embodiment. In the figure, 11 is a field insulating film, 12 is a channel.
A cut region, 13 is an element formation area, 14 is a silicon substrate, 15 and 22 are thin SiO2 films, 16 is a first polycrystalline silicon layer, 16'' is a lower polycrystalline silicon electrode (drain electrode), 17 is for interlayer insulation SiO2 film, 18 is a lower electrode formation region, 19 and 26 are photoresist patterns, 20 is an undercut portion, 21 is a gate insulating film,
23 is the second polycrystalline silicon layer, 24 is Si for interlayer insulation.
The end face of the O2 membrane, 25 is an etching window, 27 is a rectangular window,
28a and 28b are upper polycrystalline silicon electrodes (gate electrodes), and 29 is a cutout portion.

Claims (1)

[Claims] 1. A lower electrode made of a first polycrystalline silicon layer whose surface is covered with an insulating film is formed on an insulating film provided on the surface of the semiconductor substrate, and then a lower electrode is formed on the insulating film covering the first polycrystalline silicon layer. A second polycrystalline silicon layer is deposited, and then a parallel layer is formed on the second polycrystalline silicon layer, which intersects with the end face of the lower electrode to be formed using the second polycrystalline silicon layer. A photoresist pattern having an etching window crossing the end face of the lower electrode is formed in a region corresponding to the gap between the plurality of upper layer electrodes, and then the photoresist pattern is etched using the photoresist pattern as a mask. It is characterized by comprising the step of selectively etching away the second polycrystalline silicon layer exposed within the etching window of the pattern, and then patterning the second polycrystalline silicon layer to form an upper layer electrode. A method for manufacturing a semiconductor device.