JPS5953709B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS5953709B2 JPS5953709B2 JP55173600A JP17360080A JPS5953709B2 JP S5953709 B2 JPS5953709 B2 JP S5953709B2 JP 55173600 A JP55173600 A JP 55173600A JP 17360080 A JP17360080 A JP 17360080A JP S5953709 B2 JPS5953709 B2 JP S5953709B2
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline silicon
- electrode
- film
- layer
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 95
- 238000000034 method Methods 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 50
- 239000010410 layer Substances 0.000 description 47
- 239000000377 silicon dioxide Substances 0.000 description 25
- 235000012239 silicon dioxide Nutrition 0.000 description 25
- 229910052681 coesite Inorganic materials 0.000 description 23
- 229910052906 cristobalite Inorganic materials 0.000 description 23
- 229910052682 stishovite Inorganic materials 0.000 description 23
- 229910052905 tridymite Inorganic materials 0.000 description 23
- 239000011229 interlayer Substances 0.000 description 10
- 238000009413 insulation Methods 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000992 sputter etching Methods 0.000 description 4
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に係り、特に多結晶シリ
コン電極の多層構造を有する半導体装置を製造する際に
於ける上層電極間の短絡防止方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for preventing short circuits between upper layer electrodes when manufacturing a semiconductor device having a multilayer structure of polycrystalline silicon electrodes.
ランダム・アクセス・メモリー（ＲＡＭ）等の半導体集
積回路装置に於ては、多結晶シリコン電極の多層構造が
多く用いられる。A multilayer structure of polycrystalline silicon electrodes is often used in semiconductor integrated circuit devices such as random access memories (RAMs).
そしてこれら半導体集積回路装置に於ける多結晶シリコ
ン電極を多層に形成するに際しては、従来上面及び端面
が二酸化シリコン（ＳｉＯ０）等の絶縁膜で覆われた下
層即ち第１の多結晶シリコン電極上に、第２の多結晶シ
リコン層を被着し、該第２の多結晶シリコン層をエッチ
ング精度の高い例えば反応性スパッタ・エッチシダ法に
より選択エッチングを行つて、下層の第１の多結晶シリ
コン電極の端面と、前記絶縁膜をへだてて例えば直角に
交差する二本の平行した帯状を有する上層即ち第２の多
結晶シリコン電極を形成していた。然し該従来方法に於
ては第１図ａの断面図及び第１図ａＣ７）Ａ−Ａ’矢視
断面を表わした第１図ｂに示すように、第１の多結晶シ
リコン電極１上にＳｉＯ２膜２をへだてて第１の多結晶
シリコン電極１の端面と直交する平行な２ 〔本〕の帯
状を有する第２の多結晶シリコン電極３ａ及び３ｂを、
第２の多結晶シリコン層の厚さに見合つた条件で反応性
スパッタ・エッチングを行つてパターニングし、第２の
多結晶シリコン電極３ａ、３ｂ間に第１の多結晶シリコ
ン電極１の上面のＳｉＯ。When forming polycrystalline silicon electrodes in multiple layers in these semiconductor integrated circuit devices, conventionally, the top surface and end surfaces are covered with an insulating film such as silicon dioxide (SiO0) on the lower layer, that is, on the first polycrystalline silicon electrode. , a second polycrystalline silicon layer is deposited, and the second polycrystalline silicon layer is selectively etched using a highly accurate etching method, for example, a reactive sputter etch fern method, so that the underlying first polycrystalline silicon electrode is etched. An upper layer, that is, a second polycrystalline silicon electrode, having two parallel band shapes intersecting at right angles, for example, was formed apart from the end face and the insulating film. However, in this conventional method, as shown in the cross-sectional view of FIG. 1a and FIG. Separating the SiO2 film 2, second polycrystalline silicon electrodes 3a and 3b having two parallel strips perpendicular to the end surface of the first polycrystalline silicon electrode 1 are formed.
Patterning is performed by reactive sputter etching under conditions suitable for the thickness of the second polycrystalline silicon layer, and SiO2 on the upper surface of the first polycrystalline silicon electrode 1 is formed between the second polycrystalline silicon electrodes 3a and 3b. .
膜を表’出せしめた状態では、第２の多結晶シリコン電
極３ａと３ｂの間の第１の多結晶シリコン電極１端面に
形成されている第２の多結晶シリコン層はそのまま除去
されずに第２の多結晶シリコン残留層４となる。これは
該第１の多結晶シリコン電極１・端面に於ける第２の多
結晶シリコン層の縦方向の厚さが厚いために、被処理基
板面に対して垂直な方向性を有する反応性スパッタ・エ
ッチング法を用いる限り避けられない問題である。そし
て上記第２の多結晶シリコン残留層４は第２の多結晶シ
リコン電極３ａと３ｂ間を短絡せしめ、素子の性能をそ
こなうので、従来は該第２の多結晶シリコン電極３ａ，
３ｂをパターニングする際のエツチング条件を大幅なオ
ーバ・エツチング条件として前記第２の多結晶シリコン
残留層４の除去を行つていた。（第１図ａ及びｂに於て
６はフイールドＳｉＯ２膜、８はチヤネル・カツト領域
、９はシリコン基板を示す。）然しこのようなオーバ・
エツチングを行つても第１の多結晶シリコン電極１の下
部に形成されているアンダ・カツト部５に満たされてい
る第２の多結晶シリコン残留層４は残り勝ちで、半導体
集積回路装置の製造歩留まりが低下するという問題があ
り、又上記のように大幅なオーバ・エツチングを行うと
フオト・レジストからなるマスク・パターンもエツチン
グされて細くなるので、所望の幅を有する第２の多結晶
シリコン電極３ａ，３ｂを形成するには、予め更に広い
幅のマスク・パターンを形成しておく必要があり、その
ために素子の集積度が低下するという問題があつた。In the state where the film is exposed, the second polycrystalline silicon layer formed on the end face of the first polycrystalline silicon electrode 1 between the second polycrystalline silicon electrodes 3a and 3b is not removed as it is. This becomes a second polycrystalline silicon residual layer 4. This is due to the thick vertical thickness of the second polycrystalline silicon layer at the end surface of the first polycrystalline silicon electrode 1, which causes reactive sputtering that has a direction perpendicular to the surface of the substrate to be processed. - This is an unavoidable problem as long as the etching method is used. The second polycrystalline silicon residual layer 4 causes a short circuit between the second polycrystalline silicon electrodes 3a and 3b, impairing the performance of the device.
The second residual polycrystalline silicon layer 4 was removed under conditions of large overetching when patterning 3b. (In Figures 1a and 1b, 6 indicates the field SiO2 film, 8 indicates the channel cut region, and 9 indicates the silicon substrate.)
Even if etching is performed, the second polycrystalline silicon residual layer 4 filled in the undercut portion 5 formed under the first polycrystalline silicon electrode 1 remains, and is used for manufacturing semiconductor integrated circuit devices. There is a problem that the yield decreases, and if the above-mentioned large over-etching is performed, the mask pattern made of photoresist will also be etched and become thinner. In order to form 3a and 3b, it is necessary to form a wider mask pattern in advance, which poses a problem of lowering the degree of integration of the device.
本発明は上記問題点に鑑み、第２の多結晶シリコン電極
間の第１の多結晶シリコン電極の端面に被着している第
２の多結晶シリコン層の一部を切断除去するエツチング
工程を設け、第２の多結晶シリコン電極間の短絡を防止
する半導体装置の製造方法を提供する。In view of the above problems, the present invention includes an etching process for cutting and removing a part of the second polycrystalline silicon layer adhering to the end face of the first polycrystalline silicon electrode between the second polycrystalline silicon electrodes. Provided is a method for manufacturing a semiconductor device that prevents short circuits between second polycrystalline silicon electrodes.
即ち本発明は半導体装置の製造方法に於て、半導体基板
面に設けられた絶縁膜上に、上面及び端面に絶縁膜を有
する第１の多結晶シリコン電極が形成されてなる被処理
基板上に第２の多結晶シリコン層を形成し、次いで該第
２の多結晶シリコン層を選択的にエツチング除去して、
前記第１の多結晶シリコン電極と絶縁膜をへだてて交差
する複数条の第２の多結晶シリコン電極を形成し、次い
で該被処理基板上にフオト・レジスト膜を形成し、次い
で該フオト・レジスト膜の前記第２の多結晶シリコン電
極間に、絶縁膜を有する第１の多結晶シリコン電極端面
の一部を含む領域を表出する窓を形成し、次いで該フオ
ト・レジスト膜をマスクとしてエツチングを行い、前記
窓内に表出する第１の多結晶シリコン電極端面の絶縁膜
に被着している第２の多結晶シリコン層を選択的に除去
令フ
する工程を有することを特徴とする。That is, the present invention provides a method for manufacturing a semiconductor device, in which a first polycrystalline silicon electrode is formed on an insulating film provided on a surface of a semiconductor substrate, and a first polycrystalline silicon electrode having an insulating film on an upper surface and an end surface is formed. forming a second polycrystalline silicon layer and then selectively etching away the second polycrystalline silicon layer;
forming a plurality of second polycrystalline silicon electrodes that intersect with the first polycrystalline silicon electrode across an insulating film, then forming a photoresist film on the substrate to be processed; A window is formed between the second polycrystalline silicon electrodes of the film to expose a region including a part of the end face of the first polycrystalline silicon electrode having an insulating film, and then etching is performed using the photoresist film as a mask. and selectively removing the second polycrystalline silicon layer adhering to the insulating film on the end surface of the first polycrystalline silicon electrode exposed within the window. .
以下本発明を実施例により詳細に説明する。The present invention will be explained in detail below using examples.
第２図ａ乃至ｆは本発明の一実施例の工程断面図、第３
図ａ乃至Ｃは同実施例の工程上面図、第４図ａ乃至Ｃは
他の一実施例の工程断面図、第５図ａ及びｂは同実施例
の工程上面図である。本発明の方法を適用して多結晶シ
リコン電極の多層構造を形成する一実施例に於ては、上
層の多結晶シリコン電極のパターニングまでの工程は従
来の方法が用いられる。即ち例えば第２図ａに示すよう
にフイールドＳｉＯ２膜１１及びチヤネル・カツト領域
１２により素子形成領域１３が分離形成されたＳｉ基板
１４からなる被処理基板の素子形成領域１３上に熱酸化
法により５００〜１０００〔人〕程度の薄いＳｉＯ２膜
１５を形成し、次いで該被処理基板上に化学気相成長（
ＣＶＤ）法により３０００〜４０００〔人〕程度の厚さ
の第１の多結晶シリコン層１６を形成し、次いで熱酸化
法により該第１の多結晶シリコン層１６上に２０００〜
２５００〔人〕程度の厚さの層間絶縁用ＳｉＯ２膜１７
を形成する。次いで第２図ｂに示すように該層間絶縁用
ＳｉＯ２膜１７上に所望の領域を覆うフオト・レジスト
・パターン１８を形成し、該フオト・レジスト・パター
ン１８をマスクとして先ず弗酸（ＨＦ）系のエツチング
液により表出している層間絶縁用ＳｉＯ２膜１７を溶解
除去し、続いて四弗化炭素（ＣＦ４）等からなるエツチ
ング・ガスを用いてプラズマ・エツチングを行い、前記
工程に於て表出せしめられた第１の多結晶シリコン層１
４をエツチング除去し、次いでＨＦ系のエツチング液に
より素子形成領域１３上の薄いＳｉＯ２膜１５を除去す
る。なお上記工程により形成された第１の多結晶シリコ
ン層１６からなる下層多結晶シリコン電極（ドレイン電
極）１６″の端面は、プラズマ・エツチングの際のサイ
ド・エツチングにより図に示すように層間絶縁膜１７の
端面より多少後退して形成され、又素子領域の薄いＳｉ
Ｏ２膜１５を除去する際に下層多結晶シリコン電極１６
″の端面下部に浅いアンダカツト部１９が形成される。
次いで第２図Ｃに示すように、熱酸化により該被処理基
板面の素子形成領域］３上にゲートＳｉＯ２膜２０を形
成すると同時に、前記下層多結晶シリコン電極１６″の
端部表出面に１０００〔人〕程度の薄いＳｉＯ２膜２１
を形成し、次いでＣＶＤ法を用いて該被処理基板上に４
０００〜５０００〔人〕程度の第２の多結晶シリコン層
２２を堆積形成し、次いで該第２の多結晶シリコン層２
２上に前記下層多結晶シリコン電極１６″の端面と直交
する２〔本〕の平行した帯状のポジ・レジスト・パター
ン２３を形成し、該ポジ・レジスト・パターン２３をマ
スクとして前記第２の多結晶シリコン層２２を、四塩化
炭素（ＣＣｌ４）等の塩素（Ｃｌ）系のエツチング・ガ
スを用いる反応性スパッタ・エツチング法によりエツチ
ングして、第２図ｄ及び第３図ａに示すように第１の多
結晶シリコン層１６からなる下層多結晶シリコン電極１
６″の端面と直交する２〔本〕の平行した帯状の第２の
多結晶シリコン層２２からなる上層多結晶シリコン電極
（ゲート電極）２２″を形成する。なお此の際前述した
ように上層多結晶シリコン電極２２″間に表出する層間
ＳｉＯ２膜１７及び下層多結晶シリコン電極１６″端面
の薄いＳｌＯ２膜２１上には４０００〜５０００〔人〕
程度の厚さの第２の多結晶シリコン残留層２２″″が残
る。本発明の方法に於ては上記のような従来方法により
上層多結晶シリコン電極２２″を形成した後、第２図ｅ
及び第３図ｂに示すように、該被処理基板上にフオト・
レジスト膜２３を塗布形成し、通常のフオト・プロセス
により該フオト・レジスト膜２３に於ける上層多結晶シ
リコン電極２２″の間隙部を覆う領域に、層間絶縁用Ｓ
ｉＯ２膜１７の端面を所望の幅で横切り、該端面に被着
している第２の多結晶シリコン残層２２″″を表出する
所望の長さのエツチング用窓２４を形成し、該フオト・
レジスト膜２３をマスクとして、ＣＦ４を主成分とする
エツチング・ガスを用いてプラズマ・エツチングを行つ
てエツチング用窓２４内に存在する第２の多結晶シリコ
ン残留層２２″″を完全にエツチング除去する。FIGS. 2a to 2f are process sectional views of an embodiment of the present invention;
4A to 4C are process sectional views of another embodiment, and FIGS. 5A and 5B are process top views of the same embodiment. In one embodiment in which a multilayer structure of polycrystalline silicon electrodes is formed by applying the method of the present invention, conventional methods are used for the steps up to patterning of the upper layer polycrystalline silicon electrode. That is, as shown in FIG. 2a, for example, 500 yen is deposited by a thermal oxidation method on the element forming area 13 of the substrate to be processed, which is a Si substrate 14 with an element forming area 13 separated by a field SiO2 film 11 and a channel cut region 12. A thin SiO2 film 15 of ~1000 [people] is formed, and then chemical vapor deposition (chemical vapor deposition) is performed on the substrate to be processed.
A first polycrystalline silicon layer 16 with a thickness of approximately 3,000 to 4,000 [layers] is formed by a CVD method, and then a layer of approximately 2,000 to 4,000 layers is formed on the first polycrystalline silicon layer 16 by a thermal oxidation method.
SiO2 film 17 for interlayer insulation with a thickness of about 2500 [people]
form. Next, as shown in FIG. 2b, a photoresist pattern 18 covering a desired area is formed on the interlayer insulating SiO2 film 17, and using the photoresist pattern 18 as a mask, first a hydrofluoric acid (HF)-based The exposed interlayer insulating SiO2 film 17 is dissolved and removed using an etching solution, and then plasma etching is performed using an etching gas made of carbon tetrafluoride (CF4), etc. first polycrystalline silicon layer 1
4 is removed by etching, and then the thin SiO2 film 15 on the element forming region 13 is removed using an HF-based etching solution. Note that the end face of the lower polycrystalline silicon electrode (drain electrode) 16'' made of the first polycrystalline silicon layer 16 formed by the above process is etched by side etching during plasma etching to form an interlayer insulating film as shown in the figure. 17, and is formed slightly backward from the end face of the element region.
When removing the O2 film 15, the lower polycrystalline silicon electrode 16
A shallow undercut portion 19 is formed at the bottom of the end surface of ``.
Next, as shown in FIG. 2C, a gate SiO2 film 20 is formed by thermal oxidation on the element formation region 3 on the surface of the substrate to be processed, and at the same time, a 1000 nm film is formed on the exposed end surface of the lower polycrystalline silicon electrode 16''. SiO2 film 21 as thin as a [person]
4 is formed on the substrate to be processed using the CVD method.
A second polycrystalline silicon layer 22 of about 000 to 5000 [people] is deposited, and then the second polycrystalline silicon layer 2
2, two parallel band-shaped positive resist patterns 23 are formed perpendicularly to the end face of the lower polycrystalline silicon electrode 16'', and the second polycrystalline silicon electrode 23 is formed using the positive resist patterns 23 as a mask. The crystalline silicon layer 22 is etched by a reactive sputter etching method using a chlorine (Cl) based etching gas such as carbon tetrachloride (CCl4) to form a pattern as shown in FIGS. 2d and 3a. A lower polycrystalline silicon electrode 1 consisting of a polycrystalline silicon layer 16 of
An upper polycrystalline silicon electrode (gate electrode) 22'' is formed of two parallel band-shaped second polycrystalline silicon layers 22 that are perpendicular to the end face of the polycrystalline silicon layer 6''. In this case, as mentioned above, 4,000 to 5,000 people were deposited on the interlayer SiO2 film 17 exposed between the upper polycrystalline silicon electrodes 22'' and the thin SlO2 film 21 on the end face of the lower polycrystalline silicon electrode 16''.
A second polycrystalline silicon residual layer 22"" of a certain thickness remains. In the method of the present invention, after forming the upper layer polycrystalline silicon electrode 22'' by the conventional method as described above,
And as shown in FIG. 3b, a photo film is placed on the substrate to be processed.
A resist film 23 is coated and formed, and S for interlayer insulation is applied to a region of the photo resist film 23 covering the gap between the upper polycrystalline silicon electrodes 22'' using a normal photo process.
An etching window 24 of a desired length is formed across the end face of the iO2 film 17 with a desired width and exposes the second remaining polycrystalline silicon layer 22'' attached to the end face.・
Using the resist film 23 as a mask, plasma etching is performed using an etching gas mainly composed of CF4 to completely remove the second polycrystalline silicon residual layer 22'' existing within the etching window 24. .
そして該プラズマ・エツチングに於ては多結晶シリコン
のエツチング・レートがＳｉＯ２に比べて大幅に大きい
ので、エツチング用窓２４内に表出する層間絶縁用Ｓｉ
Ｏ２膜１７及びフイールドＳｉＯ２膜１１は殆んどエツ
チングされない。なお第２図ｆおよび第３図Ｃは上記本
発明の工程を行つて下層多結晶シリコン電極（ドレイン
電極）１６″上に上層多結晶シリコン電極（ゲート電極
） ２２″を形成した状態を示し、該状態に於て上層多
結晶シリコン電極２２″間に被着している第２の多結晶
シリコン残留層２２″″は前記フオト・レジスト膜のエ
ツチング窓に相当する幅で切除されているので、２〔本
〕の第２の多結晶シリコン電極（ゲート電極）２２″の
短絡が防止される。本発明の方法の他の一実施例は上記
第２の多結晶シリコン残留層を除去する際に反応性スパ
ツタエツチングを用いる方法で、該実施例の方法は第４
図ａに示すように薄いＳｉＯ２膜２１で覆われた下層多
結晶シリコン電極（ドレイン電極）１６″の端部が、層
間絶縁用ＳｉＯ２膜１７端面より突出した階段状を有し
、下層多結晶シリコン電極１６″下部のアンダ・カツト
部１９が深く形成されており、前記実施例の方法では該
アンダ・カツト部１９内の第２の多結晶シリコン残留層
２２″″が除去しきれない際に適用される。In the plasma etching, since the etching rate of polycrystalline silicon is much higher than that of SiO2, the interlayer insulation Si exposed in the etching window 24 is
The O2 film 17 and the field SiO2 film 11 are hardly etched. Note that FIG. 2F and FIG. 3C show a state in which an upper layer polycrystalline silicon electrode (gate electrode) 22'' is formed on a lower layer polycrystalline silicon electrode (drain electrode) 16'' by performing the above-described process of the present invention, In this state, the second polycrystalline silicon residual layer 22'' that is deposited between the upper polycrystalline silicon electrodes 22'' is removed to a width corresponding to the etching window of the photoresist film. Short-circuiting of the two second polycrystalline silicon electrodes (gate electrodes) 22'' is prevented. Another embodiment of the method of the present invention is a method of using reactive sputter etching in removing the second polycrystalline silicon residual layer;
As shown in FIG. This method is applied when the undercut portion 19 at the bottom of the electrode 16'' is formed deeply and the second polycrystalline silicon residual layer 22'' in the undercut portion 19 cannot be removed by the method of the embodiment described above. be done.
（図に於て１１はフイーノレドＳｉＯ２膜、１２はチ
ヤネノレ・カツト領域、１４はシリコン基板、２０はゲ
ートＳｉＯ２膜、２２は上層多結晶シリコン電極を示す
。）即本実施例に於ては第４図ｂ及び第５図ａに示すよ
うに、上記のような被処理基板上にフオト・レジスト膜
２３を塗布形成し、該フオト・レジスト膜２３をマスク
として、ＣＣｌ４等のＣｌ系のエツチング・ガスを用い
る反応性スパツタ・エツチング法により前記エツチング
窓２４内に存在する薄いＳｉＯ２膜２１．下層多結晶シ
リコン電極２２″を前記アンダ・カツト部の第２の多結
晶シリコン残留層２２″″と共にエツチング除去する。
従つて上記工程を完了した状態に於ては、第４図Ｃ及び
第５図ｂに示すように前記エツチングを行つた領域の層
間絶縁用ＳｉＯ２膜１７と下層多結晶シリコン電極１６
″の端面２５は段差のない平面状に形成される。以上説
明したように本発明の方法によれば、多結晶シリコン電
極の多層構造を形成する際に、下層多結晶シリコン電極
及び層間絶縁用ＳｉＯ２膜により生ずる段差部及び下層
多結晶シリコン電極下部に生ずるアンダ・カツト部に残
留する上層多結晶シリコンの残留層を、所要の幅に切除
することができるので、上層多結晶シリコン電極の短絡
が完全に防止される。(In the figure, 11 is a final SiO2 film, 12 is a channel cut region, 14 is a silicon substrate, 20 is a gate SiO2 film, and 22 is an upper layer polycrystalline silicon electrode.) As shown in FIG. 5B and FIG. The thin SiO2 film 21. present in the etching window 24 is etched by a reactive sputter etching method using . The lower polycrystalline silicon electrode 22'' is etched away together with the second remaining polycrystalline silicon layer 22'' in the undercut.
Therefore, in the state where the above process is completed, as shown in FIGS. 4C and 5B, the interlayer insulation SiO2 film 17 and the lower polycrystalline silicon electrode 16 in the etched region
The end face 25 of `` is formed in a planar shape with no steps.As explained above, according to the method of the present invention, when forming a multilayer structure of polycrystalline silicon electrodes, the lower polycrystalline silicon electrode and the interlayer insulation The residual layer of the upper polycrystalline silicon remaining in the step part caused by the SiO2 film and the undercut part created under the lower polycrystalline silicon electrode can be removed to the required width, thereby preventing short circuits in the upper polycrystalline silicon electrode. Completely prevented.
従つて等速呼び出し記憶装置（ＲＡＭ）等の多結晶シリ
コン電極の多層構造を用いる半導体集積回路の製造歩留
まりを向上せしめることができる。Therefore, it is possible to improve the manufacturing yield of semiconductor integrated circuits using a multilayer structure of polycrystalline silicon electrodes, such as constant-speed access memory devices (RAM).
第１図は従来方法で形成した多結晶シリコン電極多層構
造を有する半導体装置の断面図ａ及びＡ一Ａ″矢視断面
図ｂ、第２図ａ乃至ｆは本発明の一実施例の工程断面図
、第３図ａ乃至Ｃは同実施例の工程上面図、第４図ａ乃
至Ｃは本発明の他の一実施例の工程断面図で第５図ａ及
びｂは同実施例の工程上面図である。
図に於て、１１はフイールドＳｉＯ２膜、１２はチヤネ
ル・カツト領域、１３は素子形成領域、１４はシリコン
基板、］５及び２］は薄いＳｉＯ２膜、１６は第１の多
結晶シリコン層、１６″は多結晶シリコン下層電極（ド
レイン電極）、１７は層間絶縁用ＳｉＯ２膜、１８及び
２３はフオト・レジスト・パターン、］９はアンダ・カ
ツト音１Ｓ．２０はゲートＳｉＯ２膜、２２は第２の多
結晶シリコン層、２２″は上層多結晶シリコン電極（ゲ
ート電極）、２２″は第２の多結晶シリコン残留層、２
４はエツチング用窓、２５は端面を示ず。FIG. 1 is a cross-sectional view a of a semiconductor device having a multilayer structure of polycrystalline silicon electrodes formed by a conventional method, and a cross-sectional view b taken along arrows A-A'', and FIGS. 2 a to f are process cross-sections of an embodiment of the present invention. 3A to 3C are process top views of the same embodiment, FIGS. 4A to C are process sectional views of another embodiment of the present invention, and FIGS. 5A and 5B are process top views of the same embodiment. In the figure, 11 is a field SiO2 film, 12 is a channel cut region, 13 is an element formation region, 14 is a silicon substrate, ]5 and 2] are thin SiO2 films, and 16 is a first polycrystalline film. silicon layer, 16'' is a polycrystalline silicon lower layer electrode (drain electrode), 17 is an SiO2 film for interlayer insulation, 18 and 23 are photoresist patterns,] 9 is an undercut sound 1S. 20 is a gate SiO2 film, 22 is a second polycrystalline silicon layer, 22'' is an upper layer polycrystalline silicon electrode (gate electrode), 22'' is a second polycrystalline silicon residual layer, 2
4 is an etching window, and 25 does not show an end surface.
Claims (1)
面に絶縁膜を有する第１の多結晶シリコン電極が形成さ
れてなる被処理基板上に第２の多結晶シリコン層を形成
し、次いで該第２の多結晶シリコン層を選択的にエッチ
ング除去して前記第１の多結晶シリコン電極と絶縁膜を
へだてて交差する複数条の第２の多結晶シリコン電極を
形成し、次いで該被処理基板上にフォト・レジスト膜を
形成し、次いで該フォトレジスト膜の前記第２の多結晶
シリコン電極間に、絶縁膜を有する第１の多結晶シリコ
ン電極端面の一部を含む領域を表出する窓を形成し、次
いで該フォト・レジスト膜をマスクとしてエッチングを
行い、前記窓内に表出する第１の多結晶シリコン電極端
面の絶縁膜に被着している第２の多結晶シリコン層を選
択的に除去する工程を有することを特徴とする半導体装
置の製造方法。1. A second polycrystalline silicon layer is formed on a substrate to be processed, in which a first polycrystalline silicon electrode having an insulating film on the top surface and end surfaces is formed on an insulating film provided on the semiconductor substrate surface, and then selectively etching and removing the second polycrystalline silicon layer to form a plurality of second polycrystalline silicon electrodes crossing the first polycrystalline silicon electrode and the insulating film; forming a photoresist film on the substrate, and then exposing a region including a part of the end surface of the first polycrystalline silicon electrode having an insulating film between the second polycrystalline silicon electrodes of the photoresist film; A window is formed, and then etching is performed using the photoresist film as a mask to remove the second polycrystalline silicon layer adhering to the insulating film on the end surface of the first polycrystalline silicon electrode exposed within the window. A method for manufacturing a semiconductor device, comprising a step of selectively removing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55173600A JPS5953709B2 (en) | 1980-12-09 | 1980-12-09 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55173600A JPS5953709B2 (en) | 1980-12-09 | 1980-12-09 | Manufacturing method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5796564A JPS5796564A (en) | 1982-06-15 |
| JPS5953709B2 true JPS5953709B2 (en) | 1984-12-26 |
Family
ID=15963601
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55173600A Expired JPS5953709B2 (en) | 1980-12-09 | 1980-12-09 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5953709B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01106014U (en) * | 1988-01-08 | 1989-07-17 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760855A (en) * | 1980-09-30 | 1982-04-13 | Nec Corp | Manufacture of semiconductor device |
-
1980
- 1980-12-09 JP JP55173600A patent/JPS5953709B2/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5760855A (en) * | 1980-09-30 | 1982-04-13 | Nec Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01106014U (en) * | 1988-01-08 | 1989-07-17 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5796564A (en) | 1982-06-15 |
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