JPS5953709B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for preventing short circuits between upper layer electrodes when manufacturing a semiconductor device having a multilayer structure of polycrystalline silicon electrodes.

A multilayer structure of polycrystalline silicon electrodes is often used in semiconductor integrated circuit devices such as random access memories (RAMs).

When forming polycrystalline silicon electrodes in multiple layers in these semiconductor integrated circuit devices, conventionally, the top surface and end surfaces are covered with an insulating film such as silicon dioxide (SiO0) on the lower layer, that is, on the first polycrystalline silicon electrode. , a second polycrystalline silicon layer is deposited, and the second polycrystalline silicon layer is selectively etched using a highly accurate etching method, for example, a reactive sputter etch fern method, so that the underlying first polycrystalline silicon electrode is etched. An upper layer, that is, a second polycrystalline silicon electrode, having two parallel band shapes intersecting at right angles, for example, was formed apart from the end face and the insulating film. However, in this conventional method, as shown in the cross-sectional view of FIG. 1a and FIG. Separating the SiO2 film 2, second polycrystalline silicon electrodes 3a and 3b having two parallel strips perpendicular to the end surface of the first polycrystalline silicon electrode 1 are formed.
Patterning is performed by reactive sputter etching under conditions suitable for the thickness of the second polycrystalline silicon layer, and SiO2 on the upper surface of the first polycrystalline silicon electrode 1 is formed between the second polycrystalline silicon electrodes 3a and 3b. .

In the state where the film is exposed, the second polycrystalline silicon layer formed on the end face of the first polycrystalline silicon electrode 1 between the second polycrystalline silicon electrodes 3a and 3b is not removed as it is. This becomes a second polycrystalline silicon residual layer 4. This is due to the thick vertical thickness of the second polycrystalline silicon layer at the end surface of the first polycrystalline silicon electrode 1, which causes reactive sputtering that has a direction perpendicular to the surface of the substrate to be processed. - This is an unavoidable problem as long as the etching method is used. The second polycrystalline silicon residual layer 4 causes a short circuit between the second polycrystalline silicon electrodes 3a and 3b, impairing the performance of the device.
The second residual polycrystalline silicon layer 4 was removed under conditions of large overetching when patterning 3b. (In Figures 1a and 1b, 6 indicates the field SiO2 film, 8 indicates the channel cut region, and 9 indicates the silicon substrate.)
Even if etching is performed, the second polycrystalline silicon residual layer 4 filled in the undercut portion 5 formed under the first polycrystalline silicon electrode 1 remains, and is used for manufacturing semiconductor integrated circuit devices. There is a problem that the yield decreases, and if the above-mentioned large over-etching is performed, the mask pattern made of photoresist will also be etched and become thinner. In order to form 3a and 3b, it is necessary to form a wider mask pattern in advance, which poses a problem of lowering the degree of integration of the device.

In view of the above problems, the present invention includes an etching process for cutting and removing a part of the second polycrystalline silicon layer adhering to the end face of the first polycrystalline silicon electrode between the second polycrystalline silicon electrodes. Provided is a method for manufacturing a semiconductor device that prevents short circuits between second polycrystalline silicon electrodes.

That is, the present invention provides a method for manufacturing a semiconductor device, in which a first polycrystalline silicon electrode is formed on an insulating film provided on a surface of a semiconductor substrate, and a first polycrystalline silicon electrode having an insulating film on an upper surface and an end surface is formed. forming a second polycrystalline silicon layer and then selectively etching away the second polycrystalline silicon layer;
forming a plurality of second polycrystalline silicon electrodes that intersect with the first polycrystalline silicon electrode across an insulating film, then forming a photoresist film on the substrate to be processed; A window is formed between the second polycrystalline silicon electrodes of the film to expose a region including a part of the end face of the first polycrystalline silicon electrode having an insulating film, and then etching is performed using the photoresist film as a mask. and selectively removing the second polycrystalline silicon layer adhering to the insulating film on the end surface of the first polycrystalline silicon electrode exposed within the window. .

The present invention will be explained in detail below using examples.

FIGS. 2a to 2f are process sectional views of an embodiment of the present invention;
4A to 4C are process sectional views of another embodiment, and FIGS. 5A and 5B are process top views of the same embodiment. In one embodiment in which a multilayer structure of polycrystalline silicon electrodes is formed by applying the method of the present invention, conventional methods are used for the steps up to patterning of the upper layer polycrystalline silicon electrode. That is, as shown in FIG. 2a, for example, 500 yen is deposited by a thermal oxidation method on the element forming area 13 of the substrate to be processed, which is a Si substrate 14 with an element forming area 13 separated by a field SiO2 film 11 and a channel cut region 12. A thin SiO2 film 15 of ~1000 [people] is formed, and then chemical vapor deposition (chemical vapor deposition) is performed on the substrate to be processed.
A first polycrystalline silicon layer 16 with a thickness of approximately 3,000 to 4,000 [layers] is formed by a CVD method, and then a layer of approximately 2,000 to 4,000 layers is formed on the first polycrystalline silicon layer 16 by a thermal oxidation method.
SiO2 film 17 for interlayer insulation with a thickness of about 2500 [people]
form. Next, as shown in FIG. 2b, a photoresist pattern 18 covering a desired area is formed on the interlayer insulating SiO2 film 17, and using the photoresist pattern 18 as a mask, first a hydrofluoric acid (HF)-based The exposed interlayer insulating SiO2 film 17 is dissolved and removed using an etching solution, and then plasma etching is performed using an etching gas made of carbon tetrafluoride (CF4), etc. first polycrystalline silicon layer 1
4 is removed by etching, and then the thin SiO2 film 15 on the element forming region 13 is removed using an HF-based etching solution. Note that the end face of the lower polycrystalline silicon electrode (drain electrode) 16'' made of the first polycrystalline silicon layer 16 formed by the above process is etched by side etching during plasma etching to form an interlayer insulating film as shown in the figure. 17, and is formed slightly backward from the end face of the element region.
When removing the O2 film 15, the lower polycrystalline silicon electrode 16
A shallow undercut portion 19 is formed at the bottom of the end surface of ``.
Next, as shown in FIG. 2C, a gate SiO2 film 20 is formed by thermal oxidation on the element formation region 3 on the surface of the substrate to be processed, and at the same time, a 1000 nm film is formed on the exposed end surface of the lower polycrystalline silicon electrode 16''. SiO2 film 21 as thin as a [person]
4 is formed on the substrate to be processed using the CVD method.
A second polycrystalline silicon layer 22 of about 000 to 5000 [people] is deposited, and then the second polycrystalline silicon layer 2
2, two parallel band-shaped positive resist patterns 23 are formed perpendicularly to the end face of the lower polycrystalline silicon electrode 16'', and the second polycrystalline silicon electrode 23 is formed using the positive resist patterns 23 as a mask. The crystalline silicon layer 22 is etched by a reactive sputter etching method using a chlorine (Cl) based etching gas such as carbon tetrachloride (CCl4) to form a pattern as shown in FIGS. 2d and 3a. A lower polycrystalline silicon electrode 1 consisting of a polycrystalline silicon layer 16 of
An upper polycrystalline silicon electrode (gate electrode) 22'' is formed of two parallel band-shaped second polycrystalline silicon layers 22 that are perpendicular to the end face of the polycrystalline silicon layer 6''. In this case, as mentioned above, 4,000 to 5,000 people were deposited on the interlayer SiO2 film 17 exposed between the upper polycrystalline silicon electrodes 22'' and the thin SlO2 film 21 on the end face of the lower polycrystalline silicon electrode 16''.
A second polycrystalline silicon residual layer 22"" of a certain thickness remains. In the method of the present invention, after forming the upper layer polycrystalline silicon electrode 22'' by the conventional method as described above,
And as shown in FIG. 3b, a photo film is placed on the substrate to be processed.
A resist film 23 is coated and formed, and S for interlayer insulation is applied to a region of the photo resist film 23 covering the gap between the upper polycrystalline silicon electrodes 22'' using a normal photo process.
An etching window 24 of a desired length is formed across the end face of the iO2 film 17 with a desired width and exposes the second remaining polycrystalline silicon layer 22'' attached to the end face.・
Using the resist film 23 as a mask, plasma etching is performed using an etching gas mainly composed of CF4 to completely remove the second polycrystalline silicon residual layer 22'' existing within the etching window 24. .

In the plasma etching, since the etching rate of polycrystalline silicon is much higher than that of SiO2, the interlayer insulation Si exposed in the etching window 24 is
The O2 film 17 and the field SiO2 film 11 are hardly etched. Note that FIG. 2F and FIG. 3C show a state in which an upper layer polycrystalline silicon electrode (gate electrode) 22'' is formed on a lower layer polycrystalline silicon electrode (drain electrode) 16'' by performing the above-described process of the present invention, In this state, the second polycrystalline silicon residual layer 22'' that is deposited between the upper polycrystalline silicon electrodes 22'' is removed to a width corresponding to the etching window of the photoresist film. Short-circuiting of the two second polycrystalline silicon electrodes (gate electrodes) 22'' is prevented. Another embodiment of the method of the present invention is a method of using reactive sputter etching in removing the second polycrystalline silicon residual layer;
As shown in FIG. This method is applied when the undercut portion 19 at the bottom of the electrode 16'' is formed deeply and the second polycrystalline silicon residual layer 22'' in the undercut portion 19 cannot be removed by the method of the embodiment described above. be done.

(In the figure, 11 is a final SiO2 film, 12 is a channel cut region, 14 is a silicon substrate, 20 is a gate SiO2 film, and 22 is an upper layer polycrystalline silicon electrode.) As shown in FIG. 5B and FIG. The thin SiO2 film 21. present in the etching window 24 is etched by a reactive sputter etching method using . The lower polycrystalline silicon electrode 22'' is etched away together with the second remaining polycrystalline silicon layer 22'' in the undercut.
Therefore, in the state where the above process is completed, as shown in FIGS. 4C and 5B, the interlayer insulation SiO2 film 17 and the lower polycrystalline silicon electrode 16 in the etched region
The end face 25 of `` is formed in a planar shape with no steps.As explained above, according to the method of the present invention, when forming a multilayer structure of polycrystalline silicon electrodes, the lower polycrystalline silicon electrode and the interlayer insulation The residual layer of the upper polycrystalline silicon remaining in the step part caused by the SiO2 film and the undercut part created under the lower polycrystalline silicon electrode can be removed to the required width, thereby preventing short circuits in the upper polycrystalline silicon electrode. Completely prevented.

Therefore, it is possible to improve the manufacturing yield of semiconductor integrated circuits using a multilayer structure of polycrystalline silicon electrodes, such as constant-speed access memory devices (RAM).

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view a of a semiconductor device having a multilayer structure of polycrystalline silicon electrodes formed by a conventional method, and a cross-sectional view b taken along arrows A-A'', and FIGS. 2 a to f are process cross-sections of an embodiment of the present invention. 3A to 3C are process top views of the same embodiment, FIGS. 4A to C are process sectional views of another embodiment of the present invention, and FIGS. 5A and 5B are process top views of the same embodiment. In the figure, 11 is a field SiO2 film, 12 is a channel cut region, 13 is an element formation region, 14 is a silicon substrate, ]5 and 2] are thin SiO2 films, and 16 is a first polycrystalline film. silicon layer, 16'' is a polycrystalline silicon lower layer electrode (drain electrode), 17 is an SiO2 film for interlayer insulation, 18 and 23 are photoresist patterns,] 9 is an undercut sound 1S. 20 is a gate SiO2 film, 22 is a second polycrystalline silicon layer, 22'' is an upper layer polycrystalline silicon electrode (gate electrode), 22'' is a second polycrystalline silicon residual layer, 2
4 is an etching window, and 25 does not show an end surface.

Claims (1)

[Claims] 1. A second polycrystalline silicon layer is formed on a substrate to be processed, in which a first polycrystalline silicon electrode having an insulating film on the top surface and end surfaces is formed on an insulating film provided on the semiconductor substrate surface, and then selectively etching and removing the second polycrystalline silicon layer to form a plurality of second polycrystalline silicon electrodes crossing the first polycrystalline silicon electrode and the insulating film; forming a photoresist film on the substrate, and then exposing a region including a part of the end surface of the first polycrystalline silicon electrode having an insulating film between the second polycrystalline silicon electrodes of the photoresist film; A window is formed, and then etching is performed using the photoresist film as a mask to remove the second polycrystalline silicon layer adhering to the insulating film on the end surface of the first polycrystalline silicon electrode exposed within the window. A method for manufacturing a semiconductor device, comprising a step of selectively removing.