JPS59141232A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59141232A JPS59141232A JP1585183A JP1585183A JPS59141232A JP S59141232 A JPS59141232 A JP S59141232A JP 1585183 A JP1585183 A JP 1585183A JP 1585183 A JP1585183 A JP 1585183A JP S59141232 A JPS59141232 A JP S59141232A
- Authority
- JP
- Japan
- Prior art keywords
- polycrystalline
- layer
- doped
- layers
- etched
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 19
- 239000011229 interlayer Substances 0.000 abstract description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000001947 vapour-phase growth Methods 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008033 biological extinction Effects 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法、特に多結晶シＩＪコ
ン膜のエツチングされた側壁部の形状を改良し、その上
を被う層間絶縁膜と電極・配線材料の被覆性を良好にす
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a method for manufacturing a semiconductor device, in particular, to improve the shape of the etched sidewall of a polycrystalline silicon IJ film, and to improve the shape of the interlayer insulating film and electrode/wiring material covering it. This improves coverage.
第１図は、従来の半導体累子の一部を断面模式図で示し
たものである。３はゲート電極または配線材料として用
いられている多結晶シリコｙ （ｓ ｔ）である。この
上に、上部配線と絶縁を持たせるために眉間絶縁膜４（
たとえば、ＯＶＤ、ＳｉＯ。FIG. 1 is a schematic cross-sectional view of a part of a conventional semiconductor transponder. 3 is polycrystalline silicon y (st) used as a gate electrode or wiring material. On top of this, a glabella insulating film 4 (
For example, OVD, SiO.
で形成する）を被着させる。さらに、その上に、電極・
配線材料であるアルミニウム（Ａｎ）５を形成する。こ
の時、多結晶８１の側壁部６の傾斜θが４５’以上あり
、しかも側壁肩部７も同様に険しい為、層間絶縁膜４の
被覆性が悪くなり、その上を横切るａ［配線５が、第１
図に示すように段差部８で薄くなり、時には断線する事
もある。(formed with). Furthermore, on top of that, electrodes
Aluminum (An) 5, which is a wiring material, is formed. At this time, since the slope θ of the side wall portion 6 of the polycrystal 81 is 45' or more, and the side wall shoulder portion 7 is also steep, the coverage of the interlayer insulating film 4 is poor, and the , 1st
As shown in the figure, the wire becomes thinner at the stepped portion 8, and sometimes breaks.
本発明は、多結晶ｓ１のエツチング速度が多結晶臼ｉ中
の不純物濃度によって異なるという性質を応用して、多
結晶Ｓ１のエツチング形状を改良し、上記の問題点を解
決する方法を提供するものである。The present invention provides a method for solving the above problems by improving the etching shape of polycrystalline S1 by applying the property that the etching rate of polycrystalline s1 varies depending on the impurity concentration in polycrystalline die i. It is.
以下、図面に基づいて本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below based on the drawings.
第２図は、本発明で製造される多結晶臼ｉ中のＰ濃度と
多結晶Ｓ１のエツチング速度の関係を示したものである
。エツチング方法として、ＯＦ４ガスによるドライエツ
チングの場合を示している。FIG. 2 shows the relationship between the P concentration in the polycrystalline die i produced according to the present invention and the etching rate of the polycrystalline S1. As the etching method, dry etching using OF4 gas is shown.
第２図におけるように、多結晶Ｓ１のＰ濃度を増加させ
るとともにエツチング速度も増加する。このエツチング
％性を応用して、多結晶Ｓ１のエツチング形状をなめら
かにする方法を、以下に説明する。As shown in FIG. 2, as the P concentration of polycrystalline S1 increases, the etching rate also increases. A method of smoothing the etched shape of polycrystalline S1 by applying this etching percentage will be described below.
第５図は、本発明の製造方法の第１の工程で、８１基板
上のシリコン酸化膜上に多結晶日１を積層した構造を示
す。多結晶Ｓ１は、たとえば化学的気相成長法で形成し
、第１層目を不純物全ドープしない、いわゆるノンドー
プ多結晶５１１０で形成し、ついで連続的に、不純物元
素であるリンＣＰ：ｌドープした、いわゆるリンドープ
多結晶５１１１を形成し、所望の厚みを有した多結晶８
１を積層する。FIG. 5 shows a structure in which polycrystalline silicon 1 is laminated on a silicon oxide film on a substrate 81 in the first step of the manufacturing method of the present invention. The polycrystal S1 is formed by, for example, a chemical vapor deposition method, and the first layer is formed of so-called non-doped polycrystal 5110, which is not completely doped with impurities, and then continuously doped with phosphorus CP:l, which is an impurity element. , a so-called phosphorus-doped polycrystal 5111 is formed, and a polycrystalline 8 having a desired thickness is formed.
Layer 1.
次に、不純物濃度の異なった２種類の多結晶Ｓｉ勿所望
のパターンにエツチングするためのマスクを、たとえば
フォトレジスト１２で形成する。Next, a mask for etching two types of polycrystalline Si having different impurity concentrations into a desired pattern is formed using, for example, a photoresist 12.
第４図（本４発明の製造方法の第２の工程）に示すよう
に、この半導体素子をたとえば、ＯＦ４ ガスを含むド
ライエツチングガスでエツチングすると、不純物である
Ｐを含むＰドープ多結晶Ｓ１層１１は、ノンドープ多結
晶Ｓ１よりもエツチング速度が速いため、Ｐドープ多結
晶Ｓ１の横方向エツチングが進む。多結晶Ｓ１のエツチ
ングが終了した後の形状は、Ｐドープ多結晶５１１１の
傾斜θ２がノンドープ多結晶Ｓ１の傾斜θ１よりも小さ
い２段傾斜のものとなる。第１図の多結晶Ｓ１６と比較
すると、θ２θ１〉θ３であり、多結晶Ｓ１の上部がゆ
るやかな段差となっている。As shown in FIG. 4 (second step of the manufacturing method of the fourth invention), when this semiconductor element is etched with a dry etching gas containing OF4 gas, a P-doped polycrystalline S1 layer containing P as an impurity is etched. Since the etching rate of No. 11 is faster than that of the non-doped polycrystalline S1, the lateral etching of the P-doped polycrystalline S1 progresses. After the etching of the polycrystal S1 is completed, the shape becomes a two-step slope in which the slope θ2 of the P-doped polycrystal 5111 is smaller than the slope θ1 of the non-doped polycrystal S1. When compared with polycrystalline S16 in FIG. 1, θ2θ1>θ3, and the upper part of polycrystalline S1 has a gentle step.
第５図（本発明の製造方法の第３の工程）は、第４図の
２段傾斜を有する多結晶Ｓ１の上に、層間絶縁膜１３を
被着させるとθｌ〉θ２であるため、層間絶縁膜がなだ
らかに被覆する様子を示している。従って、配線材料で
あるＡＩ！、１４（ｉ７被着しても段差部１５で断線す
る事もなくなり、信頼性の高い半導体素子を得る事がで
きる。FIG. 5 (third step of the manufacturing method of the present invention) shows that when the interlayer insulating film 13 is deposited on the polycrystalline S1 having the two-step slope shown in FIG. This shows how the insulating film is gently covered. Therefore, the wiring material AI! , 14 (i7), there is no disconnection at the stepped portion 15, and a highly reliable semiconductor element can be obtained.
以上の具体例は、不純物濃度の異なる２種類の多結晶Ｓ
１の場合であるが、多層多結晶構造すなわち、第１１ｉ
から順次不純物濃度の濃くなるような層を多層に積層し
た構造にしても、良好な段差を有スるエツチング形状と
なる。また、不純物元素はリン（Ｐ）だけでなく、ヒ素
（Ａｓ）ｔ アンチモン（ｓｂ）および臭素（Ｂ）ｅ含
む多結晶ｓ１でも、同様な効果が得られる。第２図には
、ＯＦ４プラズマによる多結晶Ｓ１のエツチング速度を
示したが、同様な特性は、弗酸・硝酸系エツチング液（
ＨＦ＠ＨＮＯｓ系）の場合にも得られる為、このＨＦ・
ＨＮＯ，系ウェットエツチング液で多層多結晶ｓ１をエ
ツチングすることにより、良好な段差形状を形成する事
が可能である。The above specific example shows two types of polycrystalline S with different impurity concentrations.
1, the multilayer polycrystalline structure, i.e., the 11i-th
Even if a multi-layered structure is formed in which layers with progressively higher impurity concentrations are formed, an etched shape with good steps can be obtained. Further, the same effect can be obtained by using not only phosphorus (P) as the impurity element but also polycrystalline s1 containing arsenic (As), antimony (sb), and bromine (B)e. Figure 2 shows the etching rate of polycrystalline S1 using OF4 plasma, but similar characteristics were obtained using a hydrofluoric acid/nitric acid based etching solution (
HF@HNOs system), so this HF・
By etching the multilayer polycrystalline s1 with an HNO-based wet etching solution, it is possible to form a good step shape.
第１図は、従来技術による方法で多結晶Ｓ１を形成した
場合の半導体素子の断面構造図。
第２図は、本発明で製造される多結晶５ｉｔｌ−エツチ
ングした場合の多結晶Ｓｉ中のリン（Ｐ）濃度とエツチ
ング速度との関係を示した図。
５−
第３図は、本発明の製造方法の第１工程を示し、Ｐ＠度
の異なる多結晶Ｓ１を二層積層した断面図。
第４図は、本発明の製造方法の第２工程を示し、レジス
トをマスクにして多結晶Ｓｉｆ：ＯＦ４ プラズマでド
ライエツチングした時の模式断面図。
第５図は、本発明の製造方法の第６の工程を示し、パタ
ーンングされた多結晶８１上に眉間絶縁膜とｈｎを積層
した場合の断面図である。
１・・・８１基板 ２・・・シリコン酸化膜５
・・・多結晶Ｓｉ ４・・・層間絶縁膜５・・
・ｈｎ
６・・・多結晶Ｓ１の側壁部
７・・・多結晶日１の側壁肩部
８・・・Ａλ段差部
９・・・エツチング速度曲線
１０・・・リンドープ多結晶５１
１２・・・フォトレジスト １３・・・層間絶縁膜１４
・・・Ａλ配線 １５・・・ｈｉｔ配線段差部
６−
第１図
第２図
物鯖晶Ｓｉ中のｐＨ裏度（ｃｔ、都／滅す第３図
第４図
第５図
、−７−％＼
１５−）Ｊ ”ｙ
ノＡテ／ 〜
ｌ ら
７／ ＼＼
−″゛）FIG. 1 is a cross-sectional structural diagram of a semiconductor device in which polycrystalline S1 is formed by a method according to the prior art. FIG. 2 is a diagram showing the relationship between the phosphorus (P) concentration in polycrystalline Si and the etching rate when polycrystalline Si produced by the present invention is etched at 5 itl. 5- FIG. 3 is a sectional view showing the first step of the manufacturing method of the present invention, in which two layers of polycrystalline S1 having different P@ degrees are laminated. FIG. 4 is a schematic cross-sectional view showing the second step of the manufacturing method of the present invention, when dry etching is performed using polycrystalline Sif:OF4 plasma using a resist as a mask. FIG. 5 shows the sixth step of the manufacturing method of the present invention, and is a cross-sectional view when a glabella insulating film and hn are laminated on a patterned polycrystalline 81. 1...81 substrate 2...Silicon oxide film 5
...Polycrystalline Si 4...Interlayer insulating film 5...
・hn 6... Side wall portion of polycrystalline S1 7... Sidewall shoulder portion of polycrystalline day 1 8... Aλ step portion 9... Etching rate curve 10... Phosphorus-doped polycrystalline 51 12... Photoresist 13...Interlayer insulating film 14
...Aλ wiring 15...hit wiring step part
6- Fig. 1 Fig. 2 pH value in crystalline Si (ct, capital/extinction Fig. 3 Fig. 4 Fig. 5, -7-%\15-)J ”y
ノ A te / ~ l et al 7 / ＼＼ -″゛）
Claims (1)
結晶シリコンから、順次その下層よりも高い不純物濃度
をもつ多結晶シリコンを積層した少なくとも２層以上か
ら成る多層多結晶シリコンを形成する工程と、それらの
多層多結晶シリコン膜ヲ所望のパターンにエツチングす
る事により段差側壁部を下層より順次なだらかな傾斜を
有する構造にエツチングする工程とからなる半導体装置
の製造方法。The semiconductor substrate 1ti is formed by forming multilayer polycrystalline silicon consisting of at least two layers of polycrystalline silicon with a low impurity concentration and then polycrystalline silicon with a higher impurity concentration than the layer below it on an insulating thin film. A method for manufacturing a semiconductor device comprising the steps of: etching the multilayer polycrystalline silicon film into a desired pattern, thereby etching the stepped sidewall portions into a structure having a gradual slope from the bottom layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1585183A JPS59141232A (en) | 1983-02-02 | 1983-02-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1585183A JPS59141232A (en) | 1983-02-02 | 1983-02-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59141232A true JPS59141232A (en) | 1984-08-13 |
Family
ID=11900315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1585183A Pending JPS59141232A (en) | 1983-02-02 | 1983-02-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59141232A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4718973A (en) * | 1986-01-28 | 1988-01-12 | Northern Telecom Limited | Process for plasma etching polysilicon to produce rounded profile islands |
| US5068707A (en) * | 1990-05-02 | 1991-11-26 | Nec Electronics Inc. | DRAM memory cell with tapered capacitor electrodes |
| US5225376A (en) * | 1990-05-02 | 1993-07-06 | Nec Electronics, Inc. | Polysilicon taper process using spin-on glass |
| US5258332A (en) * | 1987-08-28 | 1993-11-02 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices including rounding of corner portions by etching |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50118673A (en) * | 1974-03-01 | 1975-09-17 | ||
| JPS5421289A (en) * | 1977-07-19 | 1979-02-17 | Mitsubishi Electric Corp | Manufacture for semiconductor device |
| JPS5923522A (en) * | 1982-07-29 | 1984-02-07 | Matsushita Electronics Corp | Dry etching method |
-
1983
- 1983-02-02 JP JP1585183A patent/JPS59141232A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50118673A (en) * | 1974-03-01 | 1975-09-17 | ||
| JPS5421289A (en) * | 1977-07-19 | 1979-02-17 | Mitsubishi Electric Corp | Manufacture for semiconductor device |
| JPS5923522A (en) * | 1982-07-29 | 1984-02-07 | Matsushita Electronics Corp | Dry etching method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4718973A (en) * | 1986-01-28 | 1988-01-12 | Northern Telecom Limited | Process for plasma etching polysilicon to produce rounded profile islands |
| US5258332A (en) * | 1987-08-28 | 1993-11-02 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices including rounding of corner portions by etching |
| US5068707A (en) * | 1990-05-02 | 1991-11-26 | Nec Electronics Inc. | DRAM memory cell with tapered capacitor electrodes |
| US5225376A (en) * | 1990-05-02 | 1993-07-06 | Nec Electronics, Inc. | Polysilicon taper process using spin-on glass |
| US5354716A (en) * | 1990-05-02 | 1994-10-11 | Nec Electronics, Inc. | Method for forming a DRAM memory cell with tapered capacitor electrodes |
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| JPS61113258A (en) | Manufacture of semiconductor device |