WO2023092811A1 - Double patterning method and semiconductor structure - Google Patents

Abstract

In the double patterning method of the present invention, a layer to be etched, a first mask layer and a second mask layer which are sequentially stacked from bottom to top are provided, wherein the layer to be etched comprises an interconnection region and a peripheral non-interconnection region, the interconnection region comprises first regions and second regions which are alternately arranged in a first axial direction, some of the second regions comprise second parts, and the second parts protrude out of the boundaries of adjacent first regions in a second axial direction; several shielding layer grooves are formed in the second mask layer on the non-interconnection region, wherein the shielding layer grooves are arranged in the first axial direction, and some of the shielding layer grooves are distributed on the side edges of the second parts; the shielding layer grooves are filled to form shielding layers; a photoresist layer is formed on the second mask layer, wherein the photoresist layer is provided with etching openings corresponding to the second regions and auxiliary openings corresponding to the shielding layers. In a photolithography process, a manufacturing process window for the etching openings corresponding to the second parts is increased. The semiconductor structure of the present invention is manufactured by means of the patterning method.

Description

Patterning method and semiconductor structure of double patterning

cross reference

[Corrected 14.01.2022 under Rule 91]
The present invention claims the priority of the Chinese patent application with application number 202111407232.5 filed on November 24, 2021. The content of the above application is incorporated herein by reference.

technical field

The invention relates to the technical field of semiconductors, in particular to a double-patterning patterning method and a semiconductor structure.

technical background

At the node of 10nm and below, there are more and more process weaknesses (Weak points) brought about by the increase of graphics complexity; double patterning technology (Double Patterning, DP) is usually used to overcome the above process weaknesses. 1 to 3 are schematic plan views of different semiconductor structures. Referring to Figures 1 to 3, the isolated groove pattern (isolated line) endpoint in Figure 1, the head-to-head pattern (head to head) in Figure 2, and the multi-line bridge structure (bridge) in Figure 3 are passed through the photolithography process It is formed directly with the etching process. In the photolithography process, the weak point pattern of the process directly forms a patterned defect, resulting in poor performance of the semiconductor device.

Summary of the invention

The invention provides a double-patterning patterning method and a semiconductor structure, which can increase the process window for making isolated region patterns and improve the performance of semiconductor devices.

In order to achieve the above object, the present invention provides a double-patterning patterning method on the one hand, comprising: providing a layer to be etched, a first mask layer and a second mask layer stacked sequentially from bottom to top; The etch layer includes an interconnected area and a non-interconnected area. The non-interconnected area is located on the periphery of the interconnected area. The interconnected area includes several first areas and several second areas alternately arranged along the first axis. The first area and the The second regions are all extended along the second axis, and the second axis is perpendicular to the first axis; the second regions each include a first part, and the first part is adjacent to the first The regions are adjacent; part of the second region includes a second part, the first part and the second part corresponding to the same second region are arranged along the second axial direction, and the second part protrudes from the adjacent The boundary of the first region; etching the second mask layer and stopping on the upper surface of the first mask layer, forming a A plurality of shielding layer grooves arranged in the first axial direction; the shielding layer grooves are all extended along the second axial direction and distributed on the side of the second part, and are in the same position as the second part The projections of the second axial direction are at least partially overlapped; filling the grooves of the shielding layer to form several shielding layers; forming a photoresist layer on the second mask layer, and the photoresist layer has the The etching opening corresponding to the second area and the auxiliary opening corresponding to the shielding layer; and using the photoresist layer and the shielding layer as a mask, etching the second mask layer to form a plurality of second A groove, the second groove corresponds to the second region, and the bottom of which exposes the upper surface of the first mask layer.

Optionally, while forming the shielding layer groove in the second mask layer on the non-interconnected region, a second mask layer is formed in part of the second region on the second mask layer A division groove, the second division groove divides the corresponding second region along the second axial direction.

Optionally, before forming the barrier layer grooves, the patterning method includes: removing the second mask layer on the first region, forming several first grooves, and the first grooves The bottom part of the upper surface of the first mask layer is exposed.

Optionally, the width of the shielding layer groove along the first axis is smaller than or equal to the width of the second dividing groove along the second axis.

Optionally, the method for filling the shielding layer groove to form the shielding layer includes: forming a filling layer, the filling layer covering the first groove, the second dividing groove and the shielding layer groove. The inner surface and the upper surface of the second mask layer; the filling layer is etched back until the upper surface of the second mask layer and the first groove located at the bottom surface of the first groove are exposed. The upper surface of the mask layer retains the filling layer on the sidewall of the first groove as a sidewall, and remains in the second division groove as the second division mask layer, and remains in the shielding layer groove The filling layer is used as the shielding layer.

Optionally, after etching the second mask layer to form the second groove, the patterning method includes: removing the photoresist layer; using the second split mask layer, the The sidewall, the shielding layer and the remaining second mask layer are masks, and the first mask layer and the layer to be etched are sequentially etched and stopped at the layer to be etched, so as to Corresponding graphics are formed in the first area and the second area.

Optionally, the width of the shielding layer groove along the first axis is greater than the width of the second dividing groove along the second axis.

Optionally, some of the second regions only include the first part, and at least part of the shielding layer grooves correspond to the positions of the second regions that only include the first part, and are arranged on the side of the end of the corresponding second region.

Optionally, the first part and the second part corresponding to the same second zone are connected; or, the first part and the second part corresponding to the same second zone are arranged at intervals along the second axial direction.

Another aspect of the present invention provides a semiconductor structure, which is formed by using the above-mentioned patterning method of double patterning.

Description of drawings

1 to 3 are schematic plan views of different semiconductor structures.

4 to 7 are schematic structural diagrams of a process of fabricating a semiconductor structure using a patterning method.

FIG. 8 is a schematic flowchart of a double-patterning graphics method according to an embodiment of the present invention.

FIG. 9 to FIG. 21 are schematic structural diagrams of the process of fabricating a semiconductor structure by using the patterning method of double patterning according to an embodiment of the present invention.

Contents of the invention

The double-patterning patterning method and semiconductor structure proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in very simplified form and use inaccurate scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

4 to 7 are schematic structural diagrams of a process of fabricating a semiconductor structure using a patterning method. 4 to 7 are top views of semiconductor structures. The graphical method includes:

Step 1, referring to FIG. 4 , provides a layer to be etched, a first mask layer 20 and a second mask layer 30 stacked sequentially from bottom to top (that is, along the direction perpendicular to the surface of the paper in FIG. 4 ). The layer to be etched includes an interconnected area and a non-interconnected area, the non-interconnected area is located at the periphery of the interconnected area, and the interconnected area includes several first areas (not shown in Figure 4) and several second areas 102, the first area and The second regions 102 are alternately arranged along a first axis (eg, X axis), and all extend along a second axis (eg, Y axis) perpendicular to the first axis. The second regions 102 each include a first portion 102a, and part of the second region 102 includes a second portion 102b, the first portion 102a and the second portion 102b corresponding to the same second region 102 are arranged in sequence along the second axial direction, and the second portion 102b Beyond the boundary of the first zone adjacent to the second zone 102 .

Step 2, referring to FIG. 4, removing the second mask layer 20 on the first region (not shown in FIG. 4) to form a first groove 301, the bottom of the first groove 301 exposes the bottom of the first mask layer 20. upper surface.

Step 3, as shown in FIG. 4, etching the second mask layer 30 and stopping on the upper surface of the first mask layer 20, forming a second dividing groove 302 on part of the second region 102, the second dividing groove 302 is along the The second axis divides the second zone 102 .

Step 4, as shown in FIG. 5 , deposit a filling layer on the inner surfaces of the first groove 301 and the second dividing groove 302, and etch back the filling layer in the first groove 301, so as to A sidewall 303 is formed on a sidewall of a groove 301 and a second division mask layer 302 a is formed in the second division groove 302 .

In step five, as shown in FIG. 6 , a first division mask layer 304 is formed in part of the first groove 301 , and the first division mask layer 304 divides the first groove 301 along the second axis.

In step six, as shown in FIG. 7 , the remaining second mask layer 30 on the second region 102 is removed through photolithography and etching processes to form a plurality of second grooves 305 .

Step 7, using the sidewall 303, the second split mask layer 302a, the first split mask layer 304 and the remaining second mask layer 30 on the first mask layer 20 as a mask, etch the first The mask layer 20 and the layer to be etched are stopped in the layer to be etched, and corresponding patterns are formed in the first region and the second region 102 of the layer to be etched.

Since the second part 102b exceeds the boundary of the adjacent first area, that is, the second part 102b is a relatively isolated area, the pattern of the second part 102b is not affected by the side wall 303 and other figures on the first area during the formation process. However, it is directly formed by the photolithography process and the etching process, so that the process window for the pattern production of the second part 102b is relatively narrow, and the pattern of the second part 102b is likely to have a weak point in the process, which will cause the process in the photolithography process Weak points directly lead to patterning defects, which in turn lead to poor performance of semiconductor devices.

In order to increase the process window for patterning the isolated region (ie, the second part of the second region) and improve the performance of the semiconductor device, FIG. 8 is a schematic flowchart of a patterning method for double patterning according to an embodiment of the present invention. As shown in Figure 8, the graphical method of the double composition includes:

S1, providing a layer to be etched, a first mask layer, and a second mask layer stacked sequentially from bottom to top; the layer to be etched includes an interconnected area and a non-interconnected area, and the non-interconnected area is located at the periphery of the interconnected area , the interconnected area includes a number of first areas and a number of second areas alternately arranged along the first axis, the first area and the second area are all extended along the second axis, the second axis shown perpendicular to the first axial direction; each of the second regions includes a first portion, and the first portion is adjacent to the adjacent first region; part of the second region includes a second portion, the same as the second The first part and the second part corresponding to the zone are arranged along the second axial direction, and the second part protrudes beyond the boundary of the adjacent first zone;

S2. Etching the second mask layer and stopping on the upper surface of the first mask layer, forming rows along the first axial direction in the second mask layer on the non-interconnected region Several shielding layer grooves of the cloth; the shielding layer grooves are all extended along the second axial direction and distributed on the side of the second part, and are in the second axial direction with the second part The projections of are at least partially overlapping;

S3, filling the grooves of the shielding layer to form several shielding layers;

S4, forming a photoresist layer on the second mask layer, the photoresist layer has etching openings corresponding to the second region and auxiliary openings corresponding to the shielding layer;

S5, using the photoresist layer and the shielding layer as a mask, etching the second mask layer to form second grooves respectively corresponding to the second regions, the bottom of the second grooves exposing the upper surface of the first mask layer.

FIG. 9 to FIG. 21 are schematic structural diagrams of the process of fabricating a semiconductor structure by using the patterning method of double patterning according to an embodiment of the present invention. FIG. 9 shows a schematic plan view of a layer to be etched in a semiconductor structure. Referring to FIG. 9 , in step S1 , a layer 10 to be etched is firstly provided. The layer to be etched 10 includes an interconnected area and a non-interconnected area, and the non-interconnected area is located at the periphery 103 of the interconnected area. As an example, the non-interconnected region may surround the interconnected region. In one embodiment, the layer to be etched 10 is formed on a semiconductor substrate. In one embodiment, the layer to be etched 10 is a part of a semiconductor substrate.

The layer 10 to be etched can be a single layer, or a multi-layer structure stacked with different materials. Preferably, the layer 10 to be etched may include a first material layer and a second material layer, the second material layer is located on the first material layer, and the dielectric constant is higher than that of the first material layer. Constant, in the subsequent process of etching the layer to be etched, the etching loss of the second material layer is small, and can be used as an etching stop layer for the first material layer, and the pattern in the second material layer is transferred to the first material layer In the process of layering, the stability of pattern transfer is relatively high, which improves the overall pattern accuracy of the layer 10 to be etched.

Specifically, the material of the first material layer may include silicon oxide, a low dielectric constant material with a dielectric constant (K) less than or equal to 3.9. The material of the second material layer may be a hard mask material, such as silicon nitride, titanium nitride or silicon oxynitride.

The interconnected region includes several first regions 101 and several second regions 102, and the first regions 101 and the second regions 102 are alternately arranged along the first axis (for example, the X axis), and are all along the The second axis is extended from the second axis (for example, the Y axis), and the second axis is perpendicular to the first axis. In this embodiment, along the first axis, the arrangement order of the interconnected regions may be: first region 101 , second region 102 , first region 101 , . . . , second region 102 , first region 101 . In other embodiments, along the first axis, the arrangement order of the interconnection regions may be: second region 102 , first region 101 , second region 102 , . . . , first region 101 , second region 102 .

Each of the second regions 102 includes a first portion 102a, and the first portion 102a is adjacent to the adjacent first region 101. As an example, when the second region 102 is located between two first regions 101, the first part 102a is adjacent (connected) to two adjacent first regions 101; when only one side of the second region 102 is provided with the first In the area 101, the first portion 102a is adjacent to the first area 101 on its side. Part of the second region 102 includes a second portion 102b, and the first portion 102a and the second portion 102b of the same second region 102 are arranged sequentially along the second axis (as shown in FIG. 4 , from left to right), and The second portion 102b is beyond the boundary of the first area 101 adjacent to the second area 102 , that is, the second portion 102b is a relatively isolated area. It should be noted that, in this embodiment, part of the second region 102 only includes the first part 102a without the second part 102b.

In this embodiment, the first part 102a and the second part 102b of the same second region 102 may be connected. In another embodiment, the first portion 102a and the second portion 102b of the same second zone 102 may be arranged at intervals along the second axis, that is, the first portion 102a and the second portion 102b are not connected.

FIG. 10 is a schematic cross-sectional view of the semiconductor structure after the first mask layer and the second mask layer are formed on the layer to be etched 10 . As shown in FIG. 10, on the layer to be etched 10, a first mask layer 20 and a second mask layer 30 are sequentially stacked and formed, the first mask layer 20 covers the upper surface of the layer to be etched 10, and the second mask layer The film layer 30 covers the upper surface of the first mask layer 20 .

The first mask layer 20 can be a single layer, or a stacked multi-layer structure. The first mask layer 20 may include at least one of a polysilicon layer, an amorphous silicon layer, a silicon dioxide layer, a silicon nitride layer, a titanium oxide layer, and a titanium nitride layer. The second mask layer 30 can be a single layer, or a stacked multi-layer structure. The second mask layer 30 may include at least one of a polysilicon layer, an amorphous silicon layer, a silicon dioxide layer, a silicon nitride layer, a titanium oxide layer, and a titanium nitride layer.

It should be noted that when both the first mask layer 20 and the second mask layer 30 are single layers, the materials of the first mask layer 20 and the second mask layer 30 are different. When both the first mask layer 20 and the second mask layer 30 have a multi-layer structure, the bottom layer of the first mask layer 20 and the bottom layer of the second mask layer 30 may be made of different materials.

In this embodiment, both the first mask layer 20 and the second mask layer 30 can be formed by methods such as chemical vapor deposition (CVD) and/or furnace tube technology, and the chemical vapor deposition method can be, for example, low-temperature chemical vapor deposition ( LTCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD). But not limited thereto, the present invention does not limit the formation methods of the first mask layer 20 and the second mask layer 30 .

FIG. 11 is a schematic plan view of the semiconductor structure after the first groove is formed in the second mask layer. As shown in FIG. 11 , after step S1 and before step S2, the patterning method of double patterning may include: removing the second mask layer 30 on the first region 101 to form a first groove 301 , the bottom of the first groove 301 exposes part of the upper surface of the first mask layer 20 .

Specifically, the method for forming the first groove 301 may include: forming a first patterned photoresist layer (not shown in the figure) on the second mask layer 30, using the first patterned photoresist layer is a mask, etch the second mask layer 30 and stop on the upper surface of the first mask layer 20 to form a first groove 301 corresponding to the first region 101, the first groove 301 The bottom exposes part of the upper surface of the first mask layer 20 .

FIG. 12 is a schematic plan view of the semiconductor structure after forming a plurality of shielding layer grooves in the second mask layer. As shown in FIG. 12 , after the first groove 301 is formed, step S2 is performed to etch the second mask layer 30 and stop on the upper surface of the first mask layer 20 , on the non-interconnected region 103 The shielding layer grooves 306 arranged along the first axis (X axis) are formed in the second mask layer 30; the shielding layer grooves 306 are all along the second axis (Y axis) extended, distributed on the side of the second portion 102b, and at least partially overlap with the projection of the second portion 102b on the second axis.

In one embodiment, each of the shielding layer grooves 306 and the projection of the second portion 102b on the second axis at least partially overlap. In one embodiment, the projection of part of the blocking layer groove 306 and the second portion 102b on the second axial direction at least partially overlaps. Preferably, the blocking layer groove 306 close to the second portion 102b and the second portion 102b are in the The axial projections at least partially overlap.

9 and 12, part of the second zone 102 includes only the first portion 102a, and the first portion 102a is adjacent to the first zone 101, for example, along the X axis, the first/fourth second zone 102 only includes the first portion 102a, And the second/third second region 102 includes a first portion 102a and a second portion 102b. In this embodiment, at least part of the shielding layer groove 306 may correspond to the position of the second region 102 that only includes the first part, and is disposed on the end side of the corresponding second region 102, and is connected to the second region that only includes the first part. The arrangement period of the regions 102 along the first axis is the same, and then in the subsequent step S4, along the first axis, the arrangement period of the etching openings and auxiliary patterns corresponding to the second part 102b is the same as the arrangement period of the second region 102 The period is the same, increasing the manufacturing process window of the pattern (etching opening) corresponding to the second part 102b, improving the precision of the pattern corresponding to the second part 102b, and further improving the pattern precision of the second part 102b.

In this embodiment, as shown in FIG. 12 , while etching the second mask layer 30 and stopping on the upper surface of the first mask layer 20 to form the blocking layer groove 306 , it can be A second division groove 302 is formed in the second mask layer 30 on the second region 102 , and the second division groove 302 divides the corresponding second region 102 along the second axis. That is to say, in this embodiment, while forming the second dividing groove 302 for dividing the second region 102, the shielding layer groove 306 is formed at the same time, neither increasing the manufacturing process nor adding an additional photomask, let alone increasing production time. It should be noted that, generally along the second axis, the final pattern of part of the second region 102 is not continuous, so it is necessary to form the second dividing groove 302, so as to form the second dividing mask layer 302a in order to divide the corresponding District 2 102.

FIG. 13 is a schematic plan view of a semiconductor structure after forming several shielding layers according to an embodiment of the present invention. As shown in FIG. 13 , after the shielding layer groove 306 is formed, step S3 is performed to fill the shielding layer groove 306 to form a shielding layer 307 .

In one embodiment, the width of the shielding layer groove 306 along the first axis is smaller than or equal to the width of the second dividing groove 302 along the second axis. As shown in FIG. 13 , while filling the shielding layer groove 306 to form a shielding layer 307 , a sidewall 303 can be formed on the sidewall of the first groove 301 and a sidewall 303 can be formed in the second dividing groove 302 . The second split mask layer 302a simplifies the manufacturing process and saves the production cost.

FIG. 14 is a cross-sectional view of the semiconductor structure of FIG. 13 along line AA. Referring to FIG. 13 and FIG. 14, the method for forming the shielding layer 307, the sidewall 303 and the second segmentation mask layer 302a may include: depositing and forming a filling layer covering the inner surface of the first groove 301 and the inner surface of the first groove 301. the upper surface of the second mask layer 30, and fill the second dividing groove 302 and the shielding layer groove 306; etch back the filling layer until the second mask layer 30 is exposed The upper surface and the upper surface of the first mask layer 20 located at the bottom surface of the first groove 301 retain the filling layer on the side wall of the first groove 301 as the side wall 303, and retain the filling layer located at the second dividing groove 302. and the filling layer in the shielding layer groove 306 to serve as the second segmentation mask layer 302a and the shielding layer 307 respectively. It should be noted that, when the width of the shielding layer groove 306 is narrow (that is, less than or equal to the width of the second dividing groove 302 along the second axial direction), the shielding layer groove 306 can be filled up at one time.

FIG. 15 is a schematic plan view of a semiconductor structure after forming a shielding layer in another embodiment of the present invention. In another embodiment, as shown in FIG. 15 , the width of the shielding layer groove 306 along the first axial direction is greater than the width of the second dividing groove 302 along the second axial direction, and the shielding layer groove can be filled multiple times. Grooves 306 form the blocking layer 307 to ensure that the blocking layer grooves 306 are filled.

FIG. 16 is a schematic cross-sectional view of the semiconductor structure shown in FIG. 15 along line BB. Referring to FIGS. 15 and 16 , filling the shielding layer groove 306 with a larger width (for example, the width of the shielding layer groove 306 is greater than the width of the second region 102), the method for forming the shielding layer 307 may include: forming a first filling layer 307a, the first filling layer 307a covers the inner surface of the first groove 301, the inner surface of the barrier layer groove 306 and the upper surface of the second mask layer 30, and fills up the second Separation groove 302, wherein, the first filling layer 307a does not fill the barrier layer groove 306; forming a patterned layer 308 covering the upper surface of the first filling layer 307a, the patterned layer 308 has a first opening, The first opening exposes the upper surface of the first filling layer 307a located on the shielding layer groove 306; continue to deposit to form a second filling layer 307b, and the second filling layer 307b fills up the shielding layer groove 306; Etch back once until the upper surface of the first filling layer 307a corresponding to the first opening is exposed; remove the patterned layer 308; etch back a second time until the upper surface of the second mask layer 30 is exposed On the upper surface and the upper surface of the first mask layer 20 at the bottom of the first groove 301, the first filling layer 307a on the side wall of the first groove 301 is reserved as the side wall 303, and the first filling layer 307a in the second dividing groove 302 is reserved. The filling layer 307 a serves as the second division mask layer 302 a , and the second filling layer 307 b and the remaining first filling layer 307 a in the shielding layer groove 306 together serve as the shielding layer 307 .

The patterned layer 308 may be a multi-layer structure, for example, comprising a first patterned layer 308a, a second patterned layer 308b and a third patterned layer 308c formed successively on the filling layer 307a; The patterned layer 308a can be an oxide layer; the second patterned layer 308b can be used as a bottom anti-reflection layer, and its material can be a polymer with high carbon content; the third patterned layer 308c can be a photoresist layer, The accuracy of the formed first opening is improved, and the shielding effect when etching back the second filling layer 307b is improved.

FIG. 17 is a schematic plan view of the semiconductor structure after forming the first split mask layer according to an embodiment of the present invention. After forming the shielding layer 307 (specifically, after forming the sidewall 303, the second segmentation mask layer 302a, and the shielding layer 307), the patterning method of the double patterning may further include: forming in part of the first groove 301 The first split mask layer 304 , along the second axis, the first split mask layer 304 splits the corresponding first groove 301 . It should be noted that, generally, along the second axis, the final pattern of the first regions 101 is not continuous, therefore, a first segmentation mask layer 304 needs to be formed to segment the corresponding first regions 101 .

In this embodiment, the method for forming the first split mask layer 304 may include: forming a mask covering the upper surface of the second mask layer 30 and filling the first groove 301; A first dividing groove is formed in the mask in the groove 301, and the first dividing groove exposes the upper surface of the first mask layer 20; the first dividing groove is filled to form the first dividing mask layer 304; and the mask is removed.

After the first split mask layer 304 is formed in part of the first groove 301, step S4 is performed to form a photoresist layer (hereinafter referred to as the second photoresist layer) on the second mask layer 30, so that The second photoresist layer has a plurality of etching openings corresponding to the second region 102 and a plurality of auxiliary openings corresponding to the shielding layer 307 .

18 is a schematic cross-sectional view of a semiconductor structure after forming a second photoresist layer according to an embodiment of the present invention. As shown in FIG. 18 , the second photoresist layer 309 has several etching openings 310 and several auxiliary openings 311 , the etching openings 310 are located above the corresponding second region 102 , and the auxiliary openings 311 are located above the corresponding shielding layer 307 .

In the process of patterning the second photoresist layer 309 (including exposure and development), a pattern corresponding to the second region 102 (including the first part 102a and the second part 102b) is formed in the second photoresist layer 309. At the same time as the etching opening 310 of the shielding layer 307, a number of auxiliary openings 311 (that is, auxiliary patterns) corresponding to the shielding layer 307 are also formed. In this way, in the photolithography process, the pattern corresponding to the second part 102b (etching openings 310 and The manufacturing process window of the part corresponding to the second part 102b is to overcome the process weakness of the pattern corresponding to the second part 102b and improve the precision of the etching opening 310 corresponding to the second part 102b.

FIG. 19 is a schematic plan view of the second groove formed on the semiconductor structure according to an embodiment of the present invention. After step S4, step S5 is performed, using the second photoresist layer 309 and the shielding layer 307 as a mask, etching the second mask layer 30 to form regions corresponding to the second regions 102 respectively. The second groove 305 , the bottom of the second groove 305 exposes the upper surface of the first mask layer 20 . Since the etching opening 310 corresponding to the second portion 102b in the second photoresist layer 309 has higher precision, the pattern corresponding to the second portion 102b in the second groove 305 formed by etching the second mask layer 30 is improved. accuracy.

In this embodiment, in the process of etching the second mask layer 30 to form the second groove 305, in addition to using the second photoresist layer 309 and the shielding layer 307 as masks, the first division mask layer is also used 304, the second division mask layer 302a and the sidewalls 303 are masks.

FIG. 20 is a schematic plan view of the semiconductor structure after etching the first mask layer according to an embodiment of the present invention. After etching the second mask layer 30 to form the second groove 305, as shown in FIG. 20, the patterning method of the double patterning may further include: removing the second photoresist layer 309; A split mask layer 304, a second split mask layer 30, sidewalls 303, a shielding layer 307 and the rest of the second mask layer 30 are masks, and the first mask layer 20 is etched and stopped at the The upper surface of the layer 10 to be etched, so that the pattern formed by the first segmentation mask layer 304, the second segmentation mask layer 30, the sidewall 303, the shielding layer 307 and the remaining second mask layer 30 can be transferred to In the first mask layer 20 .

After etching the first mask layer 20, continue to etch the layer 10 to be etched downward and stop at the layer 10 to be etched, so that the pattern in the first mask layer 20 is transferred to the layer 10 to be etched, to Corresponding patterns are formed in the first area 101 and the second area 102 .

FIG. 21 is a schematic plan view of the semiconductor structure after removing the first mask layer and the second mask layer according to an embodiment of the present invention. As shown in FIG. 21, after the etch layer 10 is etched, a first etch groove 101' is formed in the first region 101, and a second etch groove 102' is formed in the second region 102, wherein some of the first The second etching groove 102' may include a first sub-etching groove 102a' and a second sub-etching groove 102b', and the to-be-etched layer 10 under the sidewall 303 and the first split mask layer 304 in the first region 101 is not is etched, the layer 10 to be etched under the second division mask layer 302 a in the second region 102 is not etched, and the position corresponding to the shielding layer 307 in the non-interconnection region 103 is not etched.

After the etching of the layer to be etched 10 is completed, the patterning method may further include: removing the second mask layer 30 on the layer to be etched 10, the first mask layer 20, the sidewalls 303, the first division mask The film layer 304 , the second segmentation mask layer 302 a and the shielding layer 307 ; the first etching groove 101 ′ and the second etching groove 102 ′ are filled with conductive material to form an interconnection structure in the layer to be etched 10 . The conductive material may be metal materials such as aluminum, copper, silver or tungsten. But not limited thereto, the conductive material may also be other materials such as conductive metal alloys.

This embodiment also provides a semiconductor structure, which is manufactured by the above-mentioned patterning method of double patterning. The semiconductor structure may be any semiconductor structure formed during the above-mentioned patterning method of double patterning.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of rights of the present invention. Any person skilled in the art may make any form of technical solution and technical content disclosed in the present invention without departing from the spirit and scope of the present invention. Changes such as equivalent replacement or modification, etc., all belong to the content that does not deviate from the technical solution of the present invention, and still belong to the protection scope of the present invention.

Claims (10)

1. A graphical method for dual composition, characterized in that it includes:

   Provide a layer to be etched, a first mask layer, and a second mask layer stacked sequentially from bottom to top; the layer to be etched includes an interconnected area and a non-interconnected area, and the non-interconnected area shown is located at the periphery of the interconnected area, so The interconnected area includes a number of first areas and a number of second areas alternately arranged along the first axis, the first areas and the second areas are all extended along the second axis, and the second axis is perpendicular to The first axial direction; the second zone includes a first part, and the first part is adjacent to the adjacent first zone; part of the second zone includes a second part, corresponding to the same second zone The first part and the second part are arranged along the second axial direction, and the second part protrudes beyond the boundary of the adjacent first zone;

   etching the second mask layer and stopping on the upper surface of the first mask layer, forming The shielding layer grooves; the shielding layer grooves are all extended along the second axial direction, distributed on the side of the second part, and at least the projection of the second part on the second axial direction partially overlap;

   filling the grooves of the shielding layer to form several shielding layers;

   forming a photoresist layer on the second mask layer, the photoresist layer has an etching opening corresponding to the second region, and an auxiliary opening corresponding to the shielding layer; and

   Using the photoresist layer and the shielding layer as a mask, etch the second mask layer to form a plurality of second grooves, the second grooves correspond to the second region, and the bottom of the first groove is exposed. the upper surface of the mask layer.
2. The patterning method according to claim 1, characterized in that, while forming the shielding layer groove in the second mask layer on the non-interconnected region, part of the second region on the A second dividing groove is formed in the second mask layer, and the second dividing groove divides the corresponding second region along the second axial direction.
3. The patterning method according to claim 2, characterized in that, before forming the shielding layer groove, the patterning method comprises:

   The second mask layer on the first region is removed to form a plurality of first grooves, and the bottoms of the first grooves expose part of the upper surface of the first mask layer.
4. The patterning method according to claim 3, wherein the width of the shielding layer groove along the first axis is smaller than or equal to the width of the second dividing groove along the second axis.
5. The patterning method according to claim 4, wherein the method of filling the recess of the shielding layer to form the shielding layer comprises:

   forming a filling layer, the filling layer covers the inner surface of the first groove and the upper surface of the second mask layer, and fills up the second dividing groove and the barrier layer groove;

   The filling layer is etched back until the upper surface of the second mask layer and the upper surface of the first mask layer located at the bottom of the first groove are exposed, and the first groove is retained. The filling layer on the sidewall is used as a sidewall, and the filling layer in the shielding layer groove is kept as the shielding layer while remaining in the second division groove as a second division mask layer.
6. The patterning method according to claim 5, wherein after etching the second mask layer to form the second groove, the patterning method comprises:

   removing the photoresist layer;

   Using the second split mask layer, the sidewall, the shielding layer and the remaining second mask layer as masks, sequentially etch the first mask layer and the layer to be etched And stop at the layer to be etched, so as to form corresponding patterns in the first area and the second area.
7. The patterning method according to claim 2, wherein the width of the shielding layer groove along the first axis is greater than the width of the second dividing groove along the second axis.
8. The patterning method according to claim 1, wherein part of the second area only includes the first part, and at least part of the recesses of the shielding layer correspond to the positions of the second area only including the first part, and are arranged in corresponding positions. The end side of the second zone.
9. The patterning method according to claim 1, wherein the first part and the second part corresponding to the same second area are connected; or, the first part and the second part corresponding to the same second area are connected along the The second axis is arranged at intervals.
10. A semiconductor structure, characterized in that it is formed by using the patterning method of double patterning as claimed in any one of claims 1 to 9.

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