CN116169013A - Patterning method and semiconductor structure - Google Patents

Patterning method and semiconductor structure Download PDF

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Publication number
CN116169013A
CN116169013A CN202211111843.XA CN202211111843A CN116169013A CN 116169013 A CN116169013 A CN 116169013A CN 202211111843 A CN202211111843 A CN 202211111843A CN 116169013 A CN116169013 A CN 116169013A
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layer
grooves
mask layer
region
regions
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陈海华
侯永强
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Shanghai IC R&D Center Co Ltd
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Shanghai IC R&D Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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Abstract

In the patterning method, a layer to be etched, a first mask layer and a second mask layer which are sequentially stacked from bottom to top are provided, wherein the layer to be etched comprises an interconnection area and a peripheral non-interconnection area, the interconnection area comprises first areas and second areas which are alternately arranged along a first axial direction, and a part of second areas comprise second parts protruding out of the boundary of adjacent first areas along a second axial direction; forming a plurality of shielding layer grooves which are distributed along the first axial direction in a second mask layer on the non-interconnection area, wherein the plurality of shielding layer grooves are distributed on the side edge of the second part; filling a plurality of shielding layer grooves to form a plurality of shielding layers; and forming a photoresist layer on the second mask layer, wherein the photoresist layer is provided with a plurality of etching openings corresponding to the second areas and a plurality of auxiliary openings corresponding to the shielding layers, so that a manufacturing process window of the etching openings corresponding to the second parts can be increased in the photoetching process. The semiconductor structure of the invention is manufactured by the patterning method.

Description

Patterning method and semiconductor structure
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a patterning method and a semiconductor structure.
Background
In the process of semiconductor device fabrication, a lithographic process is typically used to transfer a pattern from a reticle to a substrate. The patterning process of semiconductor devices generally includes: providing a substrate; forming a photoresist layer on a substrate; exposing and developing the photoresist layer to form a patterned photoresist layer, so that the pattern on the mask plate is transferred into the photoresist layer; etching the substrate by taking the patterned photoresist layer as a mask, so that the pattern on the photoresist layer is transferred into the substrate; the photoresist is removed.
As feature sizes of semiconductor devices continue to shrink and integration density continues to increase, patterning processes face a number of challenges, such as increasing number of process weaknesses in the lithographic process due to increased pattern complexity.
Fig. 1-3 are schematic plan views of different semiconductor structures. As shown in fig. 1 to 3, the semiconductor structure includes an interconnection region and a non-interconnection region 103 located at the periphery of the interconnection region, the interconnection region includes a plurality of first regions 101 and a plurality of second regions 102, and the first regions 101 and the second regions 102 are alternately arranged in the X direction. The partial number of second regions 102 comprises a first portion 102a and a second portion 102b, wherein the first portion 102a of the second region adjoins two adjacent first regions 101 and the second portion 102b of the second region does not adjoin the first regions 101, i.e. the second portion 102b may be referred to as island. In patterning the first region 101 and the second region 102, the process window for patterning the second portion 102b of the second region is narrower than the first portion 102a of the first region 101 and the second region, i.e., the second portion 102b of the second region is susceptible to a process weakness. Referring to the figures in the dashed boxes in fig. 1 to 3, as an example, the process weak points of the isolated groove figure end points in fig. 1, the head-to-head figure in fig. 2, the multi-line bridge structure in fig. 3, etc. exist, and these figures are not affected by the surrounding figures during the patterning process, but are directly formed through the photolithography process and the etching process, which causes the process weak point figures in the photolithography process to directly form patterning defects, thereby resulting in poor performance of the semiconductor device.
Disclosure of Invention
The invention provides a patterning method which can enlarge a process window for manufacturing an isolated area pattern and improve the performance of a semiconductor device. The invention provides a semiconductor structure manufactured by the patterning method.
In order to achieve the above object, an aspect of the present invention provides a patterning method. The patterning method comprises the following steps:
providing a layer to be etched, a first mask layer and a second mask layer which are sequentially overlapped from bottom to top; the layer to be etched comprises an interconnection region and a non-interconnection region which is positioned at the periphery of the interconnection region, the interconnection region comprises a plurality of first regions and a plurality of second regions which are alternately arranged along a first axial direction, and the first regions and the second regions are elongated along a second axial direction which is perpendicular to the first axial direction; the plurality of second regions each include a first portion that adjoins an adjacent first region; a partial number of the second regions include second portions, the first and second portions of the same second region being arranged along the second axis, and the second portions protruding from the boundary of adjacent first regions;
etching the second mask layer and stopping on the upper surface of the first mask layer, and forming a plurality of shielding layer grooves which are arranged along the first axial direction in the second mask layer on the non-interconnection area; the plurality of shielding layer grooves are elongated along the second axis and distributed on the side edge of the second part, and projections of the shielding layer grooves and the second part on the second axis are at least partially overlapped;
filling the plurality of shielding layer grooves to form a plurality of shielding layers;
forming a photoresist layer on the second mask layer, wherein the photoresist layer is provided with a plurality of etching openings corresponding to the second areas and a plurality of auxiliary openings corresponding to the shielding layers; and
and etching the second mask layer by taking the photoresist layer and the shielding layers as masks to form a plurality of second grooves respectively corresponding to the second areas, wherein the bottoms of the second grooves are exposed out of the upper surface of the first mask layer.
Optionally, a second dividing groove is formed in the second mask layer on a part of the second areas while forming the plurality of shielding layer grooves in the second mask layer on the non-interconnection area, and the second dividing groove divides the corresponding second area in the second axial direction.
Optionally, before forming the plurality of shielding layer grooves, the patterning method includes: and removing the second mask layers on the first areas to form a plurality of first grooves, wherein the bottoms of the first grooves are exposed out of the upper surfaces of the first mask layers.
Optionally, the width of the shielding layer groove in the first axial direction is smaller than or equal to the width of the second dividing groove in the second axial direction.
Optionally, the method for filling the plurality of shielding layer grooves to form the plurality of shielding layers includes:
forming a filling material layer, wherein the filling material layer covers the inner surfaces of the first grooves, the second dividing grooves and the shielding layer grooves and the upper surface of the second mask layer;
and etching back the filling material layer until the upper surfaces of the second mask layer and the upper surfaces of the first mask layers positioned on the bottom surfaces of the first grooves are exposed, reserving the filling material layer on the side walls of the first grooves as side walls, and reserving the filling material layer positioned in the second dividing grooves and the shielding layer grooves as a second dividing mask layer and the shielding layers respectively.
Optionally, after etching the second mask layer to form the plurality of second grooves, the patterning method includes:
removing the photoresist layer;
and sequentially etching the first mask layer, the layer to be etched and stopping in the layer to be etched by taking the second divided mask layer, the side walls, the plurality of shielding layers and the rest second mask layer as masks so as to form corresponding patterns in the first region and the second region.
Optionally, the width of the shielding layer groove in the first axial direction is greater than the width of the second dividing groove in the second axial direction.
Optionally, a part of the second areas include only the first portions, and at least a part of the shielding layer grooves correspond to the positions of the second areas including only the first portions and are disposed at the end sides of the corresponding second areas.
Optionally, the first portion and the second portion of the same said second region are connected; alternatively, the first and second portions of the same said second region are spaced apart in said second axis.
Another aspect of the present invention provides a semiconductor structure formed using the patterning method described above.
In the patterning method, in an interconnection region of a layer to be etched, a second part of a second region exceeds a boundary of a first region adjacent to the second region, namely, the second part of the second region is isolated from the first region and the first part of the second region, a plurality of shielding layer grooves are formed in a second mask layer on a non-interconnection region, the plurality of shielding layer grooves extend along a second axis and are positioned at the side edge of the second part, projections of the shielding layer grooves and the second part in the second axis are overlapped at least partially, the plurality of shielding layer grooves are refilled to form a plurality of shielding layers, then, a photoresist layer is formed on the second mask layer, a plurality of etching openings corresponding to the plurality of second regions and a plurality of auxiliary openings corresponding to the plurality of shielding layers are formed in the photoresist layer, so that a manufacturing process window of a pattern (an immediate etching opening) corresponding to the second part in a photoetching process can be increased, the process weakness existing in the pattern corresponding to the second part can be overcome, the subsequent etching process weakness of the pattern corresponding to the second part can be further improved, the subsequent performance of a semiconductor device corresponding to the second part formed in the second grooves can be improved; in addition, in the etching process of forming the plurality of second grooves, the plurality of shielding layers are used as etching masks, and due to the blocking of the plurality of shielding layers, the patterns of the plurality of auxiliary openings cannot be transmitted to the first mask layer and the layer to be etched below through the shielding layers, so that the original pattern structure of the semiconductor device cannot be affected.
The semiconductor structure is manufactured by the patterning method, and has the same or similar advantages as the patterning method.
Drawings
Fig. 1-3 are schematic plan views of different semiconductor structures.
Fig. 4 to 7 are schematic views illustrating a process of fabricating a semiconductor structure by using a patterning method.
FIG. 8 is a flow chart of a patterning method according to an embodiment of the invention.
Fig. 9 to 21 are schematic views illustrating a process of fabricating a semiconductor structure by using a patterning method according to an embodiment of the present invention.
Detailed Description
The patterning method and semiconductor structure according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 4 to 7 are schematic views illustrating a process of fabricating a semiconductor structure by using a patterning method.
Fig. 4 to 7 are top views of semiconductor structures. The steps of the patterning method are described below in conjunction with fig. 4-7.
The patterning method mainly comprises the following steps.
In step one, referring to fig. 4, a layer to be etched, a first mask layer 20 and a second mask layer 30 are provided, which are sequentially stacked from bottom to top (i.e., in a direction out of the vertical paper surface in fig. 4). The layer to be etched includes an interconnection region and a non-interconnection region located at the periphery of the interconnection region, the interconnection region includes a plurality of first regions (not shown in fig. 4) and a plurality of second regions 102, and the first regions and the second regions 102 are alternately arranged along a first axial direction (for example, X-axis direction) and each elongate along a second axial direction (for example, Y-axis direction) perpendicular to the first axial direction. The second regions 102 each comprise a first portion 102a, a partial number of the second regions 102 comprising further second portions 102b, the first and second portions 102a, 102b of the same second region being arranged in sequence along a second axis, and the second portions 102b exceeding the boundaries of the first regions adjacent to the second regions 102.
In the second step, referring to fig. 4, the second mask layer on the first regions (not shown in fig. 4) is removed to form a plurality of first grooves 301, and the bottoms of the first grooves 301 are exposed from the upper surface of the first mask layer 20.
Step three, as shown in fig. 4, the second mask layer 30 is etched and stopped on the upper surface of the first mask layer 20, and second dividing grooves 302 are formed on a part of the number of second regions 102, and the second dividing grooves 302 divide the second regions 102 in the second axial direction.
Step four, as shown in fig. 5, a filling material layer is deposited on the inner surfaces of the first grooves 301 and the second dividing grooves 302, and the filling material layer in the first grooves 301 is etched back to form side walls 303 on the side walls of the first grooves 301 and form a second dividing mask layer 302a in the second dividing grooves 302.
Step five, as shown in fig. 6, a first division mask layer 304 is formed in a part of the number of first grooves 301, and the first division mask layer 304 divides the first grooves 301 in the second axial direction.
Step six, as shown in fig. 7, the second mask layer 30 remaining on the second region 102 is removed by photolithography and etching processes, so as to form a plurality of second recesses 305.
And step seven, taking the side wall 303, the second division mask layer 302a, the first division mask layer 304 and the second mask layer 30 remained on the first mask layer 20 as masks, sequentially etching the first mask layer 20 and the layer to be etched downwards and stopping in the layer to be etched, and forming corresponding patterns in the first region and the second region 102 of the layer to be etched.
Since the second portion 102b of the second region exceeds the boundary of the adjacent first region, that is, the second portion 102b is a relatively isolated region, the pattern of the second portion 102b of the second region is not affected by the patterns such as the side wall 303 on the first region in the forming process, but is directly formed through the photolithography process and the etching process, so that the process window for manufacturing the pattern of the second portion 102b of the second region is narrower, and the pattern of the second portion 102b is easy to have a process weak point, so that the process weak point in the photolithography process directly forms a patterning defect, thereby resulting in poor performance of the semiconductor device.
In order to increase the process window for patterning the island (i.e., the second portion of the second region) and improve the performance of the semiconductor device, the present embodiment provides a patterning method. FIG. 8 is a flow chart of a patterning method according to an embodiment of the invention. As shown in fig. 8, the patterning method includes the steps of:
s1, providing a layer to be etched, a first mask layer and a second mask layer which are sequentially overlapped from bottom to top; the layer to be etched comprises an interconnection region and a non-interconnection region which is positioned at the periphery of the interconnection region, the interconnection region comprises a plurality of first regions and a plurality of second regions which are alternately arranged along a first axial direction, and the first regions and the second regions are elongated along a second axial direction which is perpendicular to the first axial direction; the plurality of second regions each include a first portion that adjoins an adjacent first region; a partial number of the second regions include second portions, the first and second portions of the same second region being arranged along the second axis, and the second portions protruding from the boundary of adjacent first regions;
s2, etching the second mask layer and stopping on the upper surface of the first mask layer, and forming a plurality of shielding layer grooves which are arranged along the first axial direction in the second mask layer on the non-interconnection area; the plurality of shielding layer grooves are elongated along the second axis and distributed on the side edges of the second part, and projections of the shielding layer grooves and the second part on the second axis are at least partially overlapped;
s3, filling the plurality of shielding layer grooves to form a plurality of shielding layers;
s4, forming a photoresist layer on the second mask layer, wherein the photoresist layer is provided with a plurality of etching openings corresponding to the second areas and a plurality of auxiliary openings corresponding to the shielding layers;
and S5, etching the second mask layer by taking the photoresist layer and the shielding layers as masks to form a plurality of second grooves respectively corresponding to the second areas, wherein the bottoms of the second grooves are exposed out of the upper surface of the first mask layer.
Fig. 9 to 21 are schematic views illustrating a process of fabricating a semiconductor structure by using a patterning method according to an embodiment of the present invention. Fig. 9, 11 to 13, 15, 17, and 19 to 21 are schematic plan views of a semiconductor structure, and fig. 10, 14, 16, and 18 are schematic cross-sectional views of the semiconductor structure. The patterning method of the present embodiment is described below with reference to fig. 9 to 21.
Fig. 9 shows a schematic plan view of a layer to be etched in a semiconductor structure, and referring to fig. 9, in step S1, a layer to be etched 10 is first provided. The layer to be etched 10 includes an interconnection region and a non-interconnection region 103 located at the periphery of the interconnection region. As an example, the non-interconnect region may surround the interconnect region. In one embodiment, the layer to be etched 10 is formed on a semiconductor substrate. In one embodiment, the layer to be etched 10 is a portion of a semiconductor substrate.
The layer 10 to be etched may be a single material layer or a multi-layer structure formed by stacking different material layers. Preferably, the layer to be etched 10 may include a first material layer and a second material layer located on the first material layer, where the dielectric constant of the second material layer is higher than that of the first material layer, and since the dielectric constant of the second material layer is higher than that of the first material layer, the etching loss suffered by the second material layer in the subsequent process of etching the layer to be etched is smaller, and the second material layer may be used as an etching stop layer of the first material layer, and in the process of transferring the pattern in the second material layer to the first material layer, the stability of the pattern transfer is higher, which is helpful to improve the overall pattern precision of the layer to be etched 10 and improve the performance of the semiconductor device.
Specifically, the material of the first material layer may include silicon oxide or a low dielectric constant material having a dielectric constant (K) of 3.9 or less. The material of the second material layer may be a hard mask material, for example, including silicon nitride, titanium nitride, or silicon oxynitride.
The interconnection region includes a plurality of first regions 101 and a plurality of second regions 102, and the plurality of first regions 101 and the plurality of second regions 102 are alternately arranged along a first axial direction (for example, X-axis direction) and each elongated along a second axial direction (for example, Y-axis direction) perpendicular to the first axial direction. In this embodiment, in the first axial direction, the arrangement order of the plurality of first areas 101 and the plurality of second areas 102 may be: first region 101, second region 102, first regions 101, … …, second region 102, first region 101. In other embodiments, in the first axial direction, the order of arrangement of the plurality of first regions 101 and the plurality of second regions 102 may be: second region 102, first region 101, second regions 102, … …, first region 101, second region 102.
The plurality of second regions 102 each comprise a first portion 102a, the first portion 102a being contiguous with an adjacent first region 101. As an example, when the second region 102 is located between two first regions 101, the first portion 102a of the second region adjoins (connects) two adjacent first regions 101; when the second region 102 is provided with the first region 101 on only one side, the first portion 102a of the second region adjoins the first region 101 on its side. A partial number of the second regions 102 include second portions 102b, the first portions 102a and the second portions 102b of the same second region 102 are sequentially arranged along the second axis, and the second portions 102b are beyond the boundary of the first region 101 adjacent to the second region 102, that is, the second portions 102b are relatively isolated regions. It should be noted that, in this embodiment, the partial number of second regions 102 includes only the first portions 102a and no second portions 102b.
As shown in fig. 9, in this embodiment, the first portion 102a and the second portion 102b of the same second region 102 may be connected. In another embodiment, the first portion 102a and the second portion 102b of the same second region 102 may be spaced apart in a second axis, i.e., the first portion 102a and the second portion 102b are not connected.
Fig. 10 is a schematic cross-sectional view of the semiconductor structure after forming a first mask layer and a second mask layer on the layer to be etched 10. As shown in fig. 10, a first mask layer 20 and a second mask layer 30 are sequentially stacked on the layer to be etched 10, the first mask layer 20 covering the upper surface of the layer to be etched 10, and the second mask layer 30 covering the upper surface of the first mask layer 20.
The first mask layer 20 may be a single material layer or a multi-layer structure formed by stacking different material layers. The material of the first mask layer 20 may include at least one of a polysilicon material layer, an amorphous silicon material layer, a silicon oxide layer, a silicon nitride layer, a titanium oxide layer, and a titanium nitride layer. The second mask layer 30 may be a single material layer or a multi-layer structure formed by stacking different material layers. The material of the second mask layer 30 may include at least one of a polysilicon material layer, an amorphous silicon material layer, a silicon oxide layer, a silicon nitride layer, a titanium oxide layer, and a titanium nitride layer.
When the first mask layer 20 and the second mask layer 30 are both single-layer materials, the materials of the first mask layer 20 and the second mask layer 30 are different. When the first mask layer 20 and the second mask layer 30 are both of a multi-layered structure, materials of the bottom material layer of the first mask layer 20 and the bottom material layer of the second mask layer 30 may be different.
In this embodiment, the first mask layer 20 and the second mask layer 30 may be formed by a Chemical Vapor Deposition (CVD) method and/or a furnace process, and the CVD method may be, for example, low Temperature CVD (LTCVD), low Pressure CVD (LPCVD), rapid Thermal CVD (RTCVD), or Plasma Enhanced CVD (PECVD). However, the present invention is not limited to this, and the method of forming the first mask layer 20 and the second mask layer 30 is not limited thereto.
Fig. 11 is a schematic plan view of the semiconductor structure after forming the first recess in the second mask layer. As shown in fig. 11, after step S1 and before step S2, the patterning method may include: the second mask layer 30 on the first regions 101 is removed to form a plurality of first grooves 301, and the bottoms of the first grooves 301 expose the upper surface of the first mask layer 20.
Specifically, the method of forming the plurality of first grooves 301 may include: a patterned first photoresist layer (not shown) is formed on the second mask layer 30, the second mask layer 30 is etched and stopped on the upper surface of the first mask layer 20 by using the patterned first photoresist layer as a mask, a plurality of first grooves 301 corresponding to the plurality of first regions 101 are formed, and bottoms of the plurality of first grooves 301 are exposed from the upper surface of the first mask layer 20.
Fig. 12 is a schematic plan view of the semiconductor structure after forming a plurality of barrier layer recesses in the second mask layer. As shown in fig. 12, after the plurality of first grooves 301 are formed, step S2 is performed to etch the second mask layer 30 and stop on the upper surface of the first mask layer 20, and a plurality of shielding layer grooves 306 arranged along the first axial direction (X axial direction) are formed in the second mask layer 30 on the non-interconnect region 103; the plurality of barrier grooves 306 are each elongated and distributed along the second axis (Y-axis) on a side of the second portion 102b, and projections of the barrier grooves 306 and the second portion 102b in the second axis overlap at least partially.
In one embodiment, the projections of each of the barrier recess 306 and the second portion 102b in the second axial direction at least partially overlap. In an embodiment, the projections of the partial number of barrier grooves 306 and the second portion 102b in the second axial direction at least partially overlap, preferably the projections of the barrier grooves 306 and the second portion 102b near the second portion 102b in the second axial direction at least partially overlap.
Referring to fig. 9 and 12, a partial number of the second regions 102 include only the first portions 102a adjacent to the adjacent first regions 101, for example, ordered along the X-axis, the first and fourth second regions 102 include only the first portions 102a, and the second and third second regions 102 include the first portions 102a and the second portions 102b. In this embodiment, at least a part of the shielding layer grooves 306 may correspond to the second regions 102 including only the first portions in position and are disposed at the side edges of the ends of the corresponding second regions 102, so that at least a part of the shielding layer grooves 306 have the same arrangement period in the first axial direction as the second regions 102 including only the first portions, and further, the arrangement period of the combination of the etching openings corresponding to the second portions 102b and the auxiliary patterns in the photoresist layer in the subsequent step S4 in the first axial direction is the same as the arrangement period of the second regions 102, so that in the process of patterning the photoresist layer in the step S4, the manufacturing process window of the patterns (etching openings) corresponding to the second portions 102b is facilitated to be increased, and the pattern accuracy of the second portions 102b is facilitated to be increased.
In this embodiment, as shown in fig. 12, while the second mask layer 30 is etched and stopped on the upper surface of the first mask layer 20 to form the plurality of shielding layer recesses 306, second dividing grooves 302 may be formed in a part of the second mask layer 30 on the second regions 102, and the second dividing grooves 302 divide the corresponding second regions 102 in the second axial direction. That is, in the present embodiment, the second dividing grooves 302 of the second regions 102 with the divided portions are formed simultaneously with the formation of the plurality of shielding layer grooves 306, that is, the formation of the plurality of shielding layer grooves 306 does not increase the manufacturing process of the semiconductor structure, or add additional masks, or increase the manufacturing time of the semiconductor structure. It should be noted that, the final pattern of a portion of the second regions 102 is not continuous in the second axial direction, and thus the second dividing grooves 302 need to be formed in order to subsequently form the second dividing mask layer 302a to divide the corresponding second regions 102 in the second axial direction.
Fig. 13 is a schematic plan view of a semiconductor structure after forming a plurality of shielding layers according to an embodiment of the invention. As shown in fig. 13, after the plurality of shielding layer recesses 306 are formed, step S3 is performed to fill the plurality of shielding layer recesses 306, forming a plurality of shielding layers 307.
In one embodiment, the width of the shielding layer groove 306 in the first axial direction is less than or equal to the width of the second dividing groove 302 in the second axial direction. As shown in fig. 13, when the plurality of shielding layer grooves 306 are filled to form a plurality of shielding layers 307, side walls 303 may be formed on the side walls of the plurality of first grooves 301 and a second dividing mask layer 302a may be formed in the second dividing groove 302, so that the manufacturing process of the semiconductor structure may be simplified, and the production cost may be saved.
Fig. 14 is a cross-sectional view of the semiconductor structure of fig. 13 taken along line AA. Referring to fig. 13 and 14, the method of forming the plurality of shielding layers 307, the sidewalls 303, and the second division mask layer 302a may include: depositing a filling material layer, wherein the filling material layer covers the inner surfaces of the first grooves 301 and the upper surfaces of the second mask layer 30, and fills the second dividing grooves 302 and the shielding layer grooves 306; the filling material layer is etched back until the upper surface of the second mask layer 30 and the upper surface of the first mask layer 20 located at the bottom surfaces of the first grooves 301 are exposed, the filling material layer on the sidewalls of the first grooves 301 is reserved as a sidewall 303, and the filling material layer located in the second dividing groove 302 and the shielding layer grooves 306 is reserved as a second dividing mask layer 302a and the shielding layers 307, respectively. It should be noted that, when the widths of the plurality of shielding layer grooves 306 are narrow (i.e., the widths of the second dividing grooves 302 in the second axis are smaller or equal), the shielding layer grooves 306 may be filled at one time.
Fig. 15 is a schematic plan view of a semiconductor structure after forming a shielding layer according to another embodiment of the present invention. In another embodiment, as shown in fig. 15, the width of the shielding layer groove 306 in the first axial direction is larger than the width of the second dividing groove 302 in the second axial direction. Due to the large width of the barrier layer recess 306, the barrier layer 307 may be formed by filling the barrier layer recess 306 a plurality of times to ensure that the barrier layer recess 306 is filled.
Fig. 16 is a schematic cross-sectional view of the semiconductor structure shown in fig. 15 along line BB. Referring to fig. 15 and 16, a method of forming a plurality of barrier layers 307 may include filling the plurality of barrier layer recesses 306 having a larger width (e.g., the barrier layer recesses 306 having a width greater than a width of the corresponding second region 102): forming a first filling material layer 307a, wherein the first filling material layer 307a covers the inner surfaces of the first grooves 301, the inner surfaces of the shielding layer grooves 306 and the upper surfaces of the second mask layer 30 and fills the second dividing grooves 302, and the first filling material layer 307a does not fill the shielding layer grooves 306; forming a patterned layer 308 covering the upper surface of the first filling material layer 307a, wherein the patterned layer 308 has a first opening therein, and the first opening exposes the upper surface of the first filling material layer 307a on the plurality of shielding layer grooves 306; continuing to deposit and form a second filling material layer 307b, wherein the second filling material layer 307b fills the shielding layer grooves 306; performing first etching back until the upper surface of the first filling material layer 307a corresponding to the first opening is exposed; removing the patterned layer 308; and performing a second etching back until the upper surface of the second mask layer 30 and the upper surface of the first mask layer 20 at the bottom of the first groove 301 are exposed, reserving the first filling material layer 307a on the side wall of the first groove 301 as the side wall 303, reserving the first filling material layer 307a in the second dividing groove 302 as the second dividing mask layer 302a, and jointly taking the remaining first filling material layer 307a and second filling material layer 307b in the shielding layer groove 306 as the shielding layer 307.
The patterned layer 308 may be a multi-layered structure, for example, including a first patterned layer 308a, a second patterned layer 308b, and a third patterned layer 308c sequentially stacked on the first filling material layer 307 a; the first patterned layer 308a may be an oxide layer; the second patterned layer 308b may be used as a bottom anti-reflective layer, and the material may be a polymer with high carbon content; the third patterned layer 308c may be a photoresist layer, so that the accuracy of forming the first opening may be improved, and the shielding effect during etching back the second filling material layer 307b may also be improved.
Fig. 17 is a schematic plan view of a semiconductor structure after forming a first split mask layer according to an embodiment of the present invention. After forming the plurality of shielding layers 307 (specifically, for example, after forming the sidewall 303, the second division mask layer 302a, and the shielding layers 307), the patterning method may further include: a first division mask layer 304 is formed in a part of the number of first grooves 301, the first division mask layer 304 dividing the corresponding first grooves 301 in the second axis. It should be noted that, in general, the final pattern of a part of the number of first regions 101 is not continuous in the second axis direction, and thus, it is necessary to form the first division mask layer 304 to divide the corresponding first regions 101 in the second axis direction.
In this embodiment, the method for forming the first division mask layer 304 may include: forming a mask covering the upper surface of the second mask layer 30 and filling the first recess 301; forming first dividing grooves in the mask in a part of the number of first grooves 301, the first dividing grooves exposing the upper surface of the first mask layer 20; filling the first dividing grooves to form a first dividing mask layer 304; the mask is removed.
After forming the first division mask layer 304 in a part of the number of the first grooves 301, step S4 is performed to form a photoresist layer (hereinafter referred to as a second photoresist layer) on the second mask layer 30, where the second photoresist layer has a plurality of etching openings corresponding to the plurality of second regions 102 and a plurality of auxiliary openings corresponding to the plurality of shielding layers 307, respectively.
Fig. 18 is a schematic cross-sectional view of a semiconductor structure after forming a second photoresist layer according to an embodiment of the invention. As shown in fig. 18, the second photoresist layer 309 has a plurality of etched openings 310 and a plurality of auxiliary openings 311 therein, the etched openings 310 being located over the corresponding second regions 102, the auxiliary openings 311 being located over the corresponding shielding layers 307.
In the process of patterning the second photoresist layer 309 (including exposing and developing), a plurality of etching openings 310 corresponding to the plurality of second regions 102 (including the first portion 102a and the second portion 102 b) are formed in the second photoresist layer 309, and a plurality of auxiliary openings 311 (i.e., auxiliary patterns) corresponding to the plurality of shielding layers 307 are formed at the same time, so that a manufacturing process window of a pattern corresponding to the second portion 102b (a portion of the etching opening 310 corresponding to the second portion 102 b) can be enlarged in a photolithography process, which is helpful to overcome a process weak point existing in the pattern corresponding to the second portion 102b, and improve the accuracy of the etching opening 310 corresponding to the second portion 102b.
Fig. 19 is a schematic plan view of a semiconductor structure after forming a second recess in the semiconductor structure according to an embodiment of the invention. After step S4, step S5 is performed, and the second photoresist layer 309 and the plurality of shielding layers 307 are used as masks, so as to etch the second mask layer 30 to form a plurality of second grooves 305 corresponding to the plurality of second regions 102, where the bottoms of the plurality of second grooves 305 are exposed from the upper surface of the first mask layer 20. Since the accuracy of the etching openings 310 corresponding to the second portions 102b in the second photoresist layer 309 is higher, the accuracy of the patterns corresponding to the second portions 102b in the plurality of second grooves 305 formed by etching the second mask layer 30 can be improved, which is beneficial to improving the performance of the semiconductor device obtained later.
In this embodiment, in the process of etching the second mask layer 30 to form the plurality of second grooves 305, the second photoresist layer 309 and the plurality of shielding layers 307 are used as masks, and the first division mask layer 304, the second division mask layer 302a and the side walls 303 are used as masks.
Fig. 20 is a schematic plan view of a semiconductor structure after etching a first mask layer according to an embodiment of the present invention. After etching the second mask layer 30 to form the plurality of second grooves 305, as shown in fig. 20, the patterning method may further include: removing the second photoresist layer 309; the first mask layer 20 is etched by taking the first division mask layer 304, the second division mask layer 30, the side wall 303, the plurality of shielding layers 307 and the rest of the second mask layer 30 as masks, and the etching stops on the upper surface of the layer to be etched 10, so that the pattern formed by the first division mask layer 304, the second division mask layer 30, the side wall 303, the plurality of shielding layers 307 and the rest of the second mask layer 30 can be transferred into the first mask layer 20.
After etching the first mask layer 20, etching down of the layer to be etched 10 is continued and stopped in the layer to be etched 10 to transfer the pattern in the first mask layer 20 into the layer to be etched 10 to form corresponding patterns in the first region 101 and the second region 102.
Fig. 21 is a schematic plan view of a semiconductor structure after removing the first mask layer and the second mask layer according to an embodiment of the invention. As shown in fig. 21, after the etching of the layer to be etched 10 is completed, a first etching groove 101' is formed in the first region 101, and a second etching groove 102' is formed in the second region 102, where a portion of the second etching groove 102' may include a first etching sub-groove 102a ' and a second etching sub-groove 102b ', the side wall 303 and the layer to be etched 10 under the first dividing mask layer 304 in the first region 101 are not etched, the layer to be etched 10 under the second dividing mask layer 302a in the second region 102 is not etched, and positions corresponding to the plurality of shielding layers 307 in the non-interconnect region 103 are not etched.
After the etching of the layer to be etched 10 is finished, the patterning method may further include: removing the second mask layer 30, the first mask layer 20, the side wall 303, the first division mask layer 304, the second division mask layer 302a and the shielding layer 307 on the layer to be etched 10; conductive material is filled in the first etching groove 101 'and the second etching groove 102' to form an interconnection structure in the layer to be etched 10. The conductive material may be a metal material such as aluminum, copper, silver, or tungsten. However, the conductive material is not limited thereto, and may be other materials such as a conductive metal alloy.
The embodiment also provides a semiconductor structure, which is manufactured by the patterning method. The semiconductor structure may be any semiconductor structure formed during the execution of the patterning method described above.
It should be noted that, in this application, unless explicitly defined and specified otherwise, a first feature may be "on" or "off" a second feature, either the first feature being in direct contact with the second feature or the first and second features being in indirect contact via an intervening medium. Moreover, the first feature being "above," "over" and "above" the second feature is intended to describe that the first feature is at a higher level than the second feature. The first feature being "under", "below" and "beneath" the second feature is intended to describe that the first feature has a lesser level than the second feature.
Although the terms first, second, third, etc. may be used herein to describe various elements, regions, layers and/or sections, these elements, regions, layers and/or sections should not be limited by these terms and these terms should be interpreted as only being able to distinguish between different elements, regions, layers and/or sections. Thus, a first component, region, layer, and/or section discussed above could be termed a second component, region, layer, and/or section without departing from embodiments of the present invention.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.

Claims (10)

1. A method of patterning, comprising:
providing a layer to be etched, a first mask layer and a second mask layer which are sequentially overlapped from bottom to top; the layer to be etched comprises an interconnection region and a non-interconnection region which is positioned at the periphery of the interconnection region, the interconnection region comprises a plurality of first regions and a plurality of second regions which are alternately arranged along a first axial direction, and the first regions and the second regions are elongated along a second axial direction which is perpendicular to the first axial direction; the plurality of second regions each include a first portion that adjoins an adjacent first region; a partial number of the second regions include second portions, the first and second portions of the same second region being arranged along the second axis, and the second portions protruding from the boundary of adjacent first regions;
etching the second mask layer and stopping on the upper surface of the first mask layer, and forming a plurality of shielding layer grooves which are arranged along the first axial direction in the second mask layer on the non-interconnection area; the plurality of shielding layer grooves are elongated along the second axis and distributed on the side edge of the second part, and projections of the shielding layer grooves and the second part on the second axis are at least partially overlapped;
filling the plurality of shielding layer grooves to form a plurality of shielding layers;
forming a photoresist layer on the second mask layer, wherein the photoresist layer is provided with a plurality of etching openings corresponding to the second areas and a plurality of auxiliary openings corresponding to the shielding layers; and
and etching the second mask layer by taking the photoresist layer and the shielding layers as masks to form a plurality of second grooves respectively corresponding to the second areas, wherein the bottoms of the second grooves are exposed out of the upper surface of the first mask layer.
2. The patterning method of claim 1, wherein a second dividing groove is formed in a partial number of the second mask layers on the second regions while forming the plurality of shielding layer recesses in the second mask layers on the non-interconnect regions, the second dividing groove dividing the corresponding second region in the second axis.
3. The patterning method of claim 2, wherein prior to forming the plurality of masking layer recesses, the patterning method comprises:
and removing the second mask layers on the first areas to form a plurality of first grooves, wherein the bottoms of the first grooves are exposed out of the upper surfaces of the first mask layers.
4. A patterning method according to claim 3, wherein the width of the barrier layer recess in the first axial direction is equal to or less than the width of the second dividing groove in the second axial direction.
5. The patterning method of claim 4, wherein filling the plurality of masking layer recesses to form the plurality of masking layers comprises:
forming a filling material layer, wherein the filling material layer covers the inner surfaces of the first grooves and the upper surfaces of the second mask layer and fills the second dividing grooves and the shielding layer grooves;
and etching back the filling material layer until the upper surfaces of the second mask layer and the upper surfaces of the first mask layers positioned on the bottom surfaces of the first grooves are exposed, reserving the filling material layer on the side walls of the first grooves as side walls, and reserving the filling material layer positioned in the second dividing grooves and the shielding layer grooves as a second dividing mask layer and the shielding layers respectively.
6. The patterning method of claim 5, wherein after etching the second mask layer to form the plurality of second recesses, the patterning method comprises:
removing the photoresist layer;
and sequentially etching the first mask layer, the layer to be etched and stopping in the layer to be etched by taking the second divided mask layer, the side walls, the plurality of shielding layers and the rest second mask layer as masks so as to form corresponding patterns in the first region and the second region.
7. The patterning process of claim 2, wherein a width of said barrier layer recess in said first axial direction is greater than a width of said second dividing groove in said second axial direction.
8. The patterning process of claim 1, wherein a partial number of said second regions includes only a first portion, and at least a partial number of said barrier recesses corresponds to a position of a second region including only a first portion and is disposed at an end side of the corresponding second region.
9. The patterning process of claim 1, wherein the first portion and the second portion of the same said second region are connected; alternatively, the first and second portions of the same said second region are spaced apart in said second axis.
10. A semiconductor structure formed by a patterning process according to any one of claims 1 to 9.
CN202211111843.XA 2021-11-24 2022-09-13 Patterning method and semiconductor structure Pending CN116169013A (en)

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