JPH03125469A - Structure for mim capacitor - Google Patents

Abstract

PURPOSE:To minimize the level difference in a part of an upper layer electrode and a low layer electrode as compared with the thickness of an MIM capacitor and reduce the rate of generation of failure by laying out an MIM capacitor, where an insulation layer is interposed between the upper layer electrode and the lower layer electrode, so that the capacitor may be partly embedded into a recessed part. CONSTITUTION:As for the structure of an MIM capacitoralpha, a recessed part 3 is cut in the surface 2 of a substrate 1 made of a III-V compound, such as GaAs. The MIM capacitoralpha, which comprises a lower layer electrode 4, an insulation layer 5, and an upper layer electrode 6, is laid out so that the capacitoralpha may be partly embedded into the recessed part 3. The thickness of the MIM capacitor is almost half embedded into the recessed part 3. The different level part of the upper layer electrode 6 and the different level part of the lower layer electrode are about one half of the thickness of the MIM capacitoralpha, which prevents the generation of disconnection at the level different parts during the formation of the upper layer electrode 6 and the lower layer electrode 4, and hence reduced half the rate of generation of disconnection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to the structure of an MIM (metal-insulator-metal) capacitor in which a pair of electrodes are overlaid via an insulating layer.

[Background Art] FIGS. 3(a), (b), (c), and (d) show the conventional M
The structure of an IM capacitor is shown along the manufacturing order.

That is, the lower electrode 53 is formed on the semiconductor substrate 51 as shown in FIG. 3(a) with a flat surface 52.
)), further, an insulating layer 54 is formed on the lower electrode 53.
3(c)), and then, as shown in FIG. 3(d), the upper layer electrode 55 is layered from the upper surface of the insulating layer 54 to the substrate surface 52 without contacting the lower layer electrode 53.
was formed, and the upper layer electrode 55 and the lower layer electrode 53 were made to face each other with the insulating layer 54 interposed therebetween to create the MIM capacitor β.

[Problems to be Solved by the Invention] Since the conventional MIM capacitor β had a structure as shown in FIG.
A large step in the thickness of the positive insulating layer 54 occurs, and a disconnection occurs in the upper layer electrode 55 at the molecule of this step, and the upper layer electrode 55
The yield was reduced due to poor formation.

The present invention has been made in view of the drawbacks of the conventional examples described above, and has an object of preventing disconnection of the upper layer electrode in an MIM capacitor having a structure in which an insulating layer is sandwiched between an upper layer electrode and a lower layer electrode. It has been done.

[Means for Solving the Problems] Therefore, in the structure of the MIM capacitor of the present invention, a recess is formed by digging into the surface of a semiconductor substrate, and a lower electrode is formed from the bottom of the recess to the surface of the substrate. ,
The present invention is characterized in that an insulating layer is laminated on the lower electrode in the recessed portion so that the surface of the insulating layer protrudes beyond the substrate surface, and the upper electrode is formed from the surface of the insulating layer to the surface of the substrate.

[Function] In the present invention, a recessed portion is dug into the surface of the substrate,
Since the capacitor structure is formed so as to be partially buried within this recess, the step between the surface of the insulating layer and the substrate surface can be reduced by the depth of the recess. The bent portion of the upper layer electrode formed between the upper layer electrode and the substrate surface has a gentle shape, and disconnection of the upper layer electrode at this portion can be prevented.

On the other hand, by digging the recess, a step corresponding to the depth of the recess is created in the lower electrode, but this step in the lower electrode is smaller than the step in the conventional upper electrode. Compared to conventional upper layer electrodes, the incidence of disconnection is extremely small.

Therefore, even if the occurrence of wire breaks in the upper layer electrode and the lower layer electrode are combined, the wire breakage occurrence rate can be lowered than the incidence of wire breaks in the conventional upper layer electrode.

[Example] Hereinafter, the present invention will be explained in detail based on the accompanying drawings.

In Figure 1 (a) (b) (c) (d) (e),
1 is a schematic diagram illustrating the structure of an MIM capacitor α according to the present invention in accordance with its manufacturing order. MIM capacitor α of the present invention
As shown in FIG. 1(e), a recess 3 is dug into the surface 2 of a substrate 1 of a ■-■ group compound semiconductor such as GaAs, and a lower electrode 4, an insulating layer 5, and an upper electrode are formed. A part of the MIM capacitor α consisting of .

To briefly explain the manufacturing method of one embodiment of the above-mentioned MIM capacitor α, first, the recessed portion 3 is formed by etching the surface 2 of the substrate 1, which has a smooth finish as shown in FIG. 1(a). Figure 1 (b))
A lower electrode 4 is formed from the bottom of the recess 3 to the substrate surface 2 (FIG. 1C), and the lower electrode 4 inside the recess 3 is drawn out to the substrate surface 2. Next, a thin insulating layer 5 is formed on the lower electrode 4 in the recess S.
(d)), and further from the top surface of the insulating layer 5 to the substrate surface 2.
Then, the upper layer electrode 6 is formed, and the upper layer electrode on the upper surface of the insulating layer 5 is drawn out onto the substrate surface 2 (FIG. 1(e)). here,
The depth of the recessed part 3 formed in the step of FIG.
The thickness of the IM capacitor α is approximately 172 mm,
For this reason, about 172 of the MIM capacitor α is embedded in the recess portion 3. Therefore, the step portion of the upper layer electrode 8 and the step portion of the lower layer electrode 4 are both approximately 172 times the thickness of the MIM capacitor α.
When forming the upper layer electrode 6 and the lower layer electrode 4, wire breakage was less likely to occur at the step portion, and the occurrence rate of wire breakage could be halved.

FIGS. 2(a) to 2(h) show details of the manufacturing process of the MIM capacitor α. That is, the surface 2 of the substrate 1 is covered with a resist mask 8 in which a window 7 corresponding to the recess formation region is opened (FIG. 2(a)), and the substrate surface 2 is etched through the window 7 of this resist mask 8. A recessed portion 3 is formed (FIG. 2(b)). After this,
The resist mask 8 is peeled off, a resist mask 10 with a window 9 corresponding to the region where the lower electrode 4 is formed is again formed on the substrate surface 2, an electrode metal 11 is deposited on the resist mask 10, and the resist window 9 of mask 1o
A lower electrode 4 is formed through the substrate from the bottom surface of the recess 3 to the substrate surface 2 (FIG. 2(C)). Thereafter, the electrode metal 11 deposited on the resist mask 10 is peeled off together with the resist mask 10. Next, an insulating film 12 of SiNx is formed over the entire substrate 1 by the P-CVD method (FIG. 2(d)).

Thereafter, a resist mask 13 is formed on the insulating film 12 corresponding to the formation area of the insulating layer 5 (FIG. 2(e)).
), the unnecessary portions of the insulating film 12 exposed from the resist mask 13 are removed by etching, and then the resist mask 13 is peeled off (FIG. 2(f)). moreover,
The substrate surface 2 is covered with a resist mask 15 in which a window 14 is opened in the formation area of the upper layer electrode 6, and the electrode metal 16 is vapor-deposited from above, from the surface of the insulating layer 5 to the substrate surface 2 through the window 14 of the resist mask 15. An upper layer electrode 6 is formed (FIG. 2(g)). After this, resist mask 15
The electrode metal 16 deposited on the resist mask 15 is peeled off and removed together with the resist mask 15. In this way, an MIM capacitor α having a structure as shown in FIG. 2(h) is manufactured.

[Effects of the Invention] According to the present invention, the M
Since a part of the IM capacitor is disposed so as to be buried in the recessed portion, the size of the step difference between the upper layer electrode and the lower layer electrode can be made smaller than the thickness of the MIM capacitor. Therefore, the bending shapes of the upper and lower layer electrodes become gentler, and the number of electrode breaks at each stepped portion can be reduced by half compared to the conventional method. This made it possible to reduce the incidence of defective products and improve product yield.

[Brief explanation of the drawing]

Figures 1 (a), (b), (c), (d) and (e) are cross-sectional views showing one embodiment of the present invention along the manufacturing order, and Figure 2 (
a) (b) (c) (d) (e) (f) (g)
(h) is a sectional view showing the same manufacturing method in detail;
Figures (a), (b), (c), and (d) are cross-sectional views showing a conventional example along the manufacturing order. 1...Semiconductor substrate 2...Semiconductor substrate surface 3...Recess portion 4...Lower layer electrode 5...Insulating layer 6...Upper layer electrode H CI') Dimensions 0

Claims (1)

[Claims] (1) A recess is formed by digging into the surface of the semiconductor substrate, a lower electrode is formed from the bottom of the recess to the surface of the substrate, and an insulating layer is laminated on the lower electrode in the recess. A structure of an MIM capacitor, characterized in that a surface thereof is made to protrude from a surface of a substrate, and an upper layer electrode is formed from the surface of this insulating layer to the surface of the substrate.