JPS622654A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent defective opening and the yield of a thin part in electrode wiring material at the side wall surface of a contact hole, by forming a tapered part in the contact hole so that its diameter becomes smaller from the upper side to the lower side. CONSTITUTION:In order to provide contact with a semiconductor substrate 11, n-type impurities are diffused and an n<+> diffused layer 12 is formed. Then, an oxide film 13 is deposited. Phosphorus glass 14 having an impurity concentration of 1X10<20>cm<-2> is deposited thereon. Phosphorus glass 15 having an impurity concentration of 1X10<21>cm<-2> is further deposited thereon. Thus a multilayer thin-film layer is formed. When etching is performed in the horizontal direction for the multilayer thin-film layer, the etching rate at the upper film is high, because the thin film layer has oxide films including the phosphorus as the impurities, and the phosphorus concentration is higher in the upper film than in the lower film. Therefore, the tapered shape can be obtained in the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly used for forming fine contact holes.

[Technical background of the invention]

Conventionally, contact openings (contact holes) are formed in desired parts of a thin film layer formed on the surface of a semiconductor substrate.
A method of making contact with a semiconductor substrate is used. A conventional contact hole forming method will be described below.

FIGS. 2(a) to 2(C) are cross-sectional views of each process for explaining a conventional contact hole forming method. For example, oxidized I! is applied as a thin film layer on the semiconductor substrate 1. 12 is formed, resists 1 to 3 are applied to the surface thereof, and then patterning is performed to form openings in desired portions. Next, the oxide film 2 is etched using the resist 3 as a mask to obtain a structure as shown in FIG. 2(b). Next, Figure 2 (C)
After removing the resist 3 as shown in FIG. 1, an aluminum layer 4 for electrode wiring is deposited and patterned as desired to establish contact with the semiconductor substrate 1.

[Problems with background technology]

In such conventional contact hole forming methods, when the contact hole becomes fine, the coverage of the electrode wiring material deteriorates. For this reason, oven failure of aluminum H4 may occur.

FIG. 3 is a sectional view of the element for explaining this oven failure. As shown in the figure, the aluminum layer 4 is broken at the stepped portion of the oxide film 2, resulting in an oven failure.

Oven failure due to such step breakage is due to oxidation It! J
This tends to occur when 2 is thick or the openings are minute. Furthermore, even if no oven failure occurs, the aluminum layer 4, which is the electrode material, may become thinner on the side wall of the contact hole as shown in FIG.

In such a case, wiring resistance increases, which may adversely affect device characteristics. Furthermore, if such a phenomenon occurs in a portion where the current density is high, wire breakage may occur during long-term use, which poses a serious problem in terms of reliability.

[Purpose of the invention]

The present invention has been made to eliminate the above-mentioned drawbacks, and provides a semiconductor device and its manufacturing method that improves the coverage of the electrode wiring material and prevents oven failure and thinning of the electrode wiring material on the side wall surface of the contact hole. The purpose is to provide.

[Summary of the invention]

To achieve the above object, the present invention provides a semiconductor device and a method for manufacturing the same, in which the inner diameter of a contact hole gradually decreases from the upper side, that is, the wiring layer side, to the lower side, that is, the conductive layer side. It is something to do.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views of each process for explaining an embodiment of the present invention. First, as shown in FIG. 1(a), in order to make contact with a semiconductor (for example, silicon) substrate 11, an n-type impurity is diffused to form an n+ diffusion layer 12. Next, as shown in FIG. 1(b), oxide 113 is deposited on the surface of this semiconductor substrate 11 to a thickness of 3,000 layers, and phosphorus glass 14 with an impurity concentration of 1×10 20 CrA-2 is deposited on the surface of the semiconductor substrate 11 to a thickness of 4,000 layers. A phosphorus glass 15 having an impurity concentration of 1×10 2 'cm-2 is deposited thereon to a thickness of 3000 nm to form a multilayered thin film layer.

Next, a resist 17 is applied to the surface of the thin WA layer of this multilayer structure.
and apply resist 1 to the area 16 where the contact hole is to be formed.
Buttering is done so that - does not remain. Next, as shown in FIG. 1(d), using the resist 17 as a mask, the highly impurity phosphorus glass 15, the low impurity phosphorus glass 14, and the oxide film 13 are etched using reactive ion etching. In this reactive ion etching, there is relatively little so-called nide etching in which etching progresses in the horizontal direction. Therefore, as shown in FIG. 1(d>), etching progresses only in the vertical direction, resulting in openings.

Next, as shown in FIG. 1(e), after the resist 17 is peeled off, the thin film layer of this multilayer structure is etched in the horizontal direction. In the case of this example, hydrofluoric acid:water-1:100
The thin film layer 13, 14, 15 is etched from the inside surface of the opening using an aqueous solution of . The 4111 layer used in this example is an oxide film containing phosphorus as an impurity, and since the upper layer has a higher phosphorus concentration than the lower layer, the upper layer has a higher etching rate. Therefore, the contact hole can have a tapered shape as shown in FIG. 1(e).

As described above, in this embodiment, a multilayer thin film layer with different impurity concentrations is used, and the difference in etching rate is used to create a taper on the side walls of the contact 1 to the hole.

For this purpose, the etching rate of a thin film layer is determined approximately by the concentration of impurities contained therein, and the fact that the etching rate is higher at higher temperatures is utilized.

Next, as shown in FIG. 1(f), the aluminum layer 18
is applied to make contact with the semiconductor substrate 11.

It goes without saying that the present invention is not limited to the above embodiments. In the above embodiment, a multilayered oxide film containing phosphorus as an impurity was used as the thin film layer, but boron may also be used as the impurity. Further, the thin film layer is not limited to an oxide film, and an insulating layer such as a nitride film can be used as well.

Further, the insulating layer in which the contact hole is formed by etching is not limited to a stack of thin film layers, and may be, for example, a single layer in which the impurity concentration gradually changes. The formation of such an insulating layer can be realized, for example, by vapor phase growth or implantation of impurity ions using an accelerating voltage.

Note that after the reactive ion etching is completed, the amount of etching when giving a taper by etching the opening according to the depth difference depends on the concentration of the thin film layer, the concentration of the etchant, and the thickness of the thin film layer. The necessary conditions must be calculated by taking these factors into consideration. By doing this, the taper of the contact hole can be adjusted by adjusting the impurity to 11 degrees or a combination thereof.

〔Effect of the invention〕

As described above, in the present invention, since the contact hole is tapered so that the inner diameter becomes smaller from the top to the bottom,
A semiconductor device and a method for manufacturing the same that can improve the coverage of electrode wiring material are obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of each step to explain an embodiment of the present invention, FIG. 2 is a cross-sectional view of each step to explain a conventional contact hole forming method, and FIGS. The figure is a cross-sectional view for explaining the coverage of the wiring material of the electrode. 11... Semiconductor substrate, 13... Oxide film, 14. ．． 1
5... Phosphorus glass, 16... Contact hole planned portion, 18... Aluminum layer for electrode wiring.

Claims (1)

[Claims] 1. A conductive layer on a semiconductor substrate is covered with an insulating layer, and the conductive layer and a wiring layer on the insulating layer are electrically connected through a contact hole formed in the insulating layer. A semiconductor device, characterized in that the inner diameter of the contact hole gradually decreases from the wiring layer side toward the conductive layer side. 2. a first step of forming a conductive layer on the semiconductor substrate; a second step of forming an insulating layer on the conductive layer, the etching rate of which decreases from top to bottom;
a third step of vertically etching a portion of the insulating layer where a contact hole is to be formed to form an opening; and etching the opening formed in the third step horizontally from the inner surface to form a contact hole. a fourth step of forming;
A method for manufacturing a semiconductor device, comprising a fifth step of forming a wiring layer on the insulating layer and connecting the wiring layer and the conductive layer via the contact hole. 3. The semiconductor device according to claim 2, wherein the second step is a step of forming an insulating layer on the conductive layer, the impurity concentration of which gradually decreases from the upper side to the lower side. Production method. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the second step is a step of sequentially forming a plurality of insulating layers with high impurity concentrations on the conductive layer. 5. The method of manufacturing a semiconductor device according to any one of claims 2 to 4, wherein the insulating layer is a phosphorus glass containing phosphorus as an impurity. 6. The method of manufacturing a semiconductor device according to any one of claims 2 to 4, wherein the insulating layer is made of boron glass containing boron as an impurity. 7. The method for manufacturing a semiconductor device according to any one of claims 2 to 6, in which the third step uses a reactive ion etching method. 8. The method of manufacturing a semiconductor device according to any one of claims 2 to 6, wherein the fourth step uses an etching method using dilute hydrofluoric acid.