JPS6331100B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device including a step of forming a conductive path with an extremely high precision pattern connected to a semiconductor substrate.

A plan view of a conventional example for forming an electrical connection between a diffusion region and a polycrystalline silicon conductive path in a MOS type semiconductor device is shown in FIG.
- A cross-sectional view is shown in Fig. 1b. The structure shown in FIG. 1 is commonly called a buried contact or a direct contact. This is done by providing a thick field insulating film 2 on a part of the semiconductor substrate 1,
Next, a gate insulating film 3 is provided, and after removing the gate insulating film 3 in the area indicated by 8 in FIG. A conductive path 4 and a gate electrode 5 are formed, and impurities are introduced into the semiconductor substrate 1 using a method such as ion implantation using the conductive path 4 and gate electrode 5 as masks to form diffusion regions 6 and 7 to be used as sources and drains. The conductive path 4 is manufactured by forming a diffusion layer connected to the lower surface by diffusing the impurity contained therein from the connecting portion of the conductive path 4.

In the structure shown in FIGS. 1a and 1b, the gate insulating film 3
The mask 8 used for selective removal of the gate insulating film 2 is mask-aligned using the pattern of the field insulating film 2 as a reference, and the mask process for determining the shape of the polycrystalline silicon layer is performed to selectively remove the thin gate insulating film. Since the opening is difficult to use as a standard, mask alignment is performed using the pattern of the field insulating film 2 as a standard. Assuming that the alignment error due to mask alignment is αμm with respect to the reference pattern, the distance between the mask 8 and the gate electrode 5, that is, a in FIG. A margin of ×αμm or more is required. Similarly, a margin of 2×α μm or more must be allowed for the distance between the mask 8 and the conductive path 4 (FIG. 1a, b). With the current technology, it is necessary to allow for a mask alignment error of at least 1 μm for one mask alignment α μm. Moreover, as is clear from FIG. 1b, the gate electrode 5
Since the height is different from that of the conductive path 4 and the tip of the conductive path 4, fine patterning may be hindered.

The object of the present invention is to, after the shape of the polycrystalline silicon layer is determined, to
It is an object of the present invention to provide a method for manufacturing a semiconductor device that uses a photoetching process for mask alignment when etching a gate insulating film to reduce mask alignment errors and thereby improve the integration density of elements.

The present invention is characterized by the steps of: selectively forming a thick field insulating film on the surface of a semiconductor substrate of one conductivity type; forming a gate insulating film on the surface of the semiconductor substrate adjacent to the thick field insulating film; forming a gate electrode on the gate insulating film by patterning a silicon layer and forming a conductive path extending from the gate insulating film onto the field insulating film; A step of introducing an impurity into the semiconductor substrate through the gate insulating film using an insulating film as a mask to form source and drain regions of opposite conductivity type under the gate insulating film, and a patterning process in which the gate electrode and conductive path are formed. Using a mask and using the polycrystalline silicon layer as a reference, a portion of the gate insulating film from a portion spaced apart from the gate electrode in a planar shape to a portion around the tip of the conductive path is selectively etched away. exposing a portion of one of the source and drain regions from a location spaced a predetermined distance from below the gate electrode to below the periphery of the tip of the conductive path, and further comprising a gate insulating film in contact with the bottom of the tip of the conductive path; a step of removing the portion by under-etching to form a vacant region therein and exposing a portion of one conductivity type of the semiconductor substrate under the vacant region; depositing a polycrystalline silicon film over the entire surface; a step of filling the empty region with a polycrystalline silicon film; and a step of converting the other polycrystalline silicon film portions into a silicon oxide film while leaving a portion of the polycrystalline silicon film in the empty region unoxidized. , introducing an impurity into a location of one conductivity type of the semiconductor substrate under the void region through the polycrystalline silicon film in the void region to connect the region to one of the source and drain regions; The method of manufacturing a semiconductor device includes forming a diffusion layer of an opposite conductivity type and thereby connecting the conductive path to the one region through the polycrystalline silicon film in the empty region and the diffusion layer.

Next, the present invention will be explained by examples.

FIGS. 2, 3a, 4, and 5 are cross-sectional views in the order of manufacturing steps of an embodiment of the present invention, and FIG. 3b is a plan view corresponding to FIG. 3a. In FIG. 2, the surface of the semiconductor substrate 11 is selectively oxidized by a known technique,
A thick field insulating film 12 is grown, a gate insulating film 13 is formed, a polycrystalline silicon layer is grown and selectively etched to form a gate electrode 15 and a conductive path 14, and then a shaped silicon layer is formed. Using 14, 15 and the field insulating film 12 as a mask, impurities are introduced into the semiconductor substrate 11 by ion implantation to form diffusion regions 16, 17 forming sources and drains.

Then, using a conventional photomask process, a portion of the gate insulating film in region 18 shown in the plan view of FIG. 3B is etched to form an opening. By sufficiently performing wet etching using hydrofluoric acid to prevent the polycrystalline silicon from being etched, a gate insulating film is formed directly under the end of the polycrystalline silicon conductive path 14, as shown in FIG. 3a. An empty region 19 is formed by retreating in self-alignment with the shape of the conductive path 14, that is, by under-etching. The width of the empty area 19 depends on the etching time, but is preferably about 0.3 to 0.5 μm. Then, as shown in FIG. 4, when a polycrystalline silicon film 20 is formed by vapor phase growth, the inside of the empty region 19 is also filled with the polycrystalline silicon film 20. The thickness of the polycrystalline silicon film 20 is set to 1/2 of the thickness of the gate insulating film 13 in order to completely fill the thickness of the empty region 19, that is, the thickness of the gate insulating film 13. The thickness must be at least . Normally, the thickness of the gate insulating film 13 is
Since a thickness of 400 to 800 Å is used, the thickness of the polycrystalline silicon film 20 must be 200 to 400 Å or more.

Next, the polycrystalline silicon film 20 is oxidized to cause the silicon oxide film 23 to lose its conductivity, thereby forming an empty region 1.
Only the inside of the polycrystalline silicon film 9 is left unoxidized. As a result, as shown in FIG.
Since the portion 9 is completely filled and is not oxidized, the polycrystalline silicon film 20 remains only in the empty region 19 and forms a conductor 21, so that the conductive path 14 and the diffusion region 16 are electrically connected. Ru. During the oxidation or by performing appropriate heat treatment, impurities in the conductive path 14 diffuse into the semiconductor substrate 11 through the conductor 21, forming a diffusion layer 22, and preventing juncture leak in this portion. It is also effective to dope impurities into the polycrystalline silicon film 20 in advance to form the diffusion layer 22.

According to the present invention, the mask region 18 for forming the empty region 19 can be aligned based on the gate electrode 15 and the conductive path 14, which are generally made of a polycrystalline silicon layer thicker than the gate insulating film. The distance between the gate electrode 15 and the mask region 18 and the conductive path 14 is approximately 1/2 that of the conventional example shown in FIG. This has a significant effect on improving the integration density of elements. Furthermore, since both the gate electrode and the tip of the conductive path are located on the gate insulating film, their heights are the same, which facilitates patterning even if the gap between the two electrodes is minute. Further, the oxide film 23 from the polycrystalline silicon film 20 makes the surface of each part smooth, and by using this as an interlayer insulating film or a part thereof, a multilayer structure is preferable.

[Brief explanation of drawings]

1a and 1b are plan views and sectional views taken along the line A-A in the process for explaining a conventional semiconductor device manufacturing method, and FIGS. 2, 3a, 4, and 5 are FIG. 3B is a cross-sectional view of the process sequence for explaining an example of the invention, and FIG. 3B is a plan view corresponding to FIG. 3A. 1, 11... Semiconductor substrate, 2, 12... Field insulating film, 3, 13... Gate insulating film, 4, 1
4... Conductive path, 5, 15... Gate electrode, 6,
7, 16, 17... Source and drain diffusion regions, 8, 18... Etched regions at the ends of conductive paths,
19...Empty〓, 20...Empty〓Filling polycrystalline silicon film, 21...Empty〓Filling conductor, 22...Empty〓Diffusion region directly below, 23...Silicon oxide film.

Claims (1)

[Claims] 1. A step of selectively forming a thick field insulating film on the surface of a semiconductor substrate of one conductivity type, forming a gate insulating film on the surface of the semiconductor substrate adjacent to the thick field insulating film, and patterning a polycrystalline silicon layer. forming a gate electrode on the gate insulating film and forming a conductive path extending from the gate insulating film onto the field insulating film; and using the gate electrode, the conductive path and the field insulating film as a mask. A step of introducing impurities into the semiconductor substrate through the gate insulating film to form source and drain regions of opposite conductivity types under the gate insulating film, and a patterned polycrystalline silicon layer in which the gate electrode and the conductive path are formed. Using a mask as a reference, a portion of the gate insulating film from a portion spaced apart from the gate electrode in a planar shape to a portion around the tip of the conductive path is selectively etched away. exposing a portion of one of the source and drain regions from a location separated by a distance to below the periphery of the tip of the conductive path, and further under-etching a portion of the gate insulating film that is in contact with the bottom of the tip of the conductive path; forming a vacant region therein and exposing a portion of one conductivity type of the semiconductor substrate under the vacant region; depositing a polycrystalline silicon film over the entire surface; a step of filling the empty region; a step of leaving a portion of the polycrystalline silicon film in the empty region unoxidized and converting the other portion of the polycrystalline silicon film into a silicon oxide film; By introducing a lower impurity into a portion of one conductivity type of the semiconductor substrate under the empty region through a polycrystalline silicon film in the semiconductor substrate, the opposite conductivity type is connected to one of the source and drain regions. 1. A method of manufacturing a semiconductor device, comprising the step of forming a diffusion layer, thereby connecting the conductive path to the one region through the polycrystalline silicon film in the empty region and the diffusion layer.