JPH08130195A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To avoid the increase of junction leakage without remarkably improving positional accuracy. CONSTITUTION: A plurality of LOCOS oxide films 2 are formed selectively and diffusion regions 3 among these oxide films 2 on a substrate 1 respectively. A PSG film 4 is deposited on the whole surface, and an inter-layer film 5 consisting of a silicon oxide film is further deposited. The inter-layer film 5 is opened in the upper sections of the diffusion regions 3 through dry etching, and the PSG films 4 are exposed. The PSG films 4 are etched by Vapor HF to expose the diffusion regions 3, and wiring connecting layers 8 are formed onto the diffusion regions 3. Consequently, Vapor HF etches the PSG films but does not so much etch the silicon oxide film 5 and silicon. Accordingly, since the bird beaks of the end sections of the LOCOS oxide films 2 are not etched, the substrate 1 is not exposed, thus preventing the electrical connection of the P-N junctions of the diffusion regions 3 and the substrate 1 and the wiring connecting layers 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for forming contacts of a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a technique called LOCOS (Local Oxidation of Silicon) has been used as a technique for separating elements. Oxide film for element isolation formed by this technique (hereinafter referred to as "LOCOS oxide film")
Has locally thin ends called bird's beaks.

FIG. 50 is a sectional view showing a structure around a conventional contact. Selective N on P type silicon substrate 1
A mold diffusion region 3 is formed with a thickness of 0.1 to 0.2 μm, and only both ends of this diffusion region 3 are covered with the LOCOS oxide film 2. Bird's beaks 2 a are formed at the edges of the LOCOS oxide film 2.

An interlayer film 5 is once formed on the structure formed by the substrate 1, the LOCOS oxide film 2 and the diffusion region 3, and is selectively removed above the diffusion region 3 to form a contact hole 90. It

Here, an oxide film is generally used as the interlayer film 5, and when the contact hole 90 is formed by selectively removing the oxide film, the etching method is such that the diffusion region 3 is exposed and stopped. That is, an etching method in which the etching ratio of the oxide film to silicon is large, for example, dry etching using a chlorine-based gas is used.

[0006]

However, the bird's beak 2a is also a part of the LOCOS oxide film 2 and may be removed when the interlayer film 5 is etched. FIG. 51 is a cross-sectional view showing a case where such etching is performed. In the contact hole 90, not only the diffusion region 3 but also the part 1a of the substrate 1 is exposed. Therefore, the PN junction formed by the diffusion region 3 and the part 1a of the substrate 1 is exposed in the contact hole 90.

Such exposure of the PN junction causes a problem that a so-called junction leak increases a leak current. For example, in an element having a leak current value of 10 fA / μm ² when the bird's beak 2 a is not etched, the leak current value flowing when the bird's beak 2 a is etched is 100 to 1000 fA / μm ^2.
Also reaches.

In order to solve such a problem, the position accuracy may be improved by making the dimension L2 of the contact hole 90 smaller than the distance L1 between the adjacent bird's beaks 2a. However, due to the recent miniaturization of integrated circuits, the diffusion region 3
Is smaller, and the distance L1 is correspondingly smaller. As a result, it is required to reduce the dimension L2 and improve the positional accuracy. However, it is not easy to improve such positional accuracy.

FIG. 52 shows FIG. 1 of US Pat. FIG. 6B is a cross-sectional view disclosed in 6A. Figure 52
The reference numbers used in this patent are those assigned in that U.S. patent and are valid only in this drawing and have no relationship to the reference numbers in the other figures herein. A space between adjacent word lines 12 is filled with a silicon oxide film 28 and a silicon nitride film 51, and these are selectively removed to expose the diffusion layer 16. Such selective removal is realized by etching using the patterned resist mask 61, but the patterning accuracy of the resist mask 61 is relaxed. That is, even if the patterning accuracy is low, the sidewall damage of the word line 12 is small.

However, since the side wall is also formed of an oxide film, the bird's beak is removed together with the side wall in the vicinity of the bird's beak of the LOCOS oxide film 21, and there is still a possibility that not only the diffusion layer 16 but also the substrate 11 is exposed. Remain.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a technique for suppressing a junction leak without significantly increasing the positional accuracy in forming a contact hole.

[0012]

[Means for Solving the Problems] Claim 1 of the present invention
(A) a step of selectively forming an element isolation film made of an oxide film on a semiconductor substrate, and (b) forming a diffusion region on the semiconductor substrate adjacent to the element isolation film. And (c) forming a PSG film on at least the diffusion region, and (d) depositing an interlayer film made of an oxide film on the entire surface of the structure obtained in the process (c). e) selectively removing the interlayer film above the diffusion region to expose the PSG film;
(F) The PS using hydrofluoric acid vapor (Vapor HF)
Manufacturing a semiconductor device, comprising: etching a G film to expose the diffusion region; and (g) forming a wiring connection layer electrically connected to the diffusion region through the interlayer film. Is the way.

According to claim 2 of the present invention,
The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), a PSG film is deposited on the entire surface of the structure obtained in the step (b).

According to claim 3 of the present invention,
The method of manufacturing a semiconductor device according to claim 2, wherein in step (f), the PSG film is etched until the end portion of the element isolation film is exposed without exposing the central portion of the element isolation film.

According to claim 4 of the present invention,
2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), the PSG film is deposited such that the vicinity of the center of the element isolation film is exposed.

According to claim 5 of the present invention,
The method of manufacturing a semiconductor device according to claim 4, wherein in the step (c), the PSG film is deposited so as to cover an end portion of the element isolation film.

According to claim 6 of the present invention,
The method of manufacturing a semiconductor device according to claim 5, wherein the step (c) includes a step (c-1) of providing a patterned nitride film on the PSG film on the PSG film.

According to claim 7 of the present invention,
(A) a step of forming a pair of wirings each having a sidewall made of an oxide film on a semiconductor substrate;
(B) a step of forming a PSG film on the semiconductor substrate sandwiched by the pair of wirings, and (c) the step (b)
Depositing an interlayer film made of an oxide film on the entire surface of the structure obtained in step (d), exposing the PSG film by selectively removing the interlayer film above the PSG film, and (e) ) A step of etching the PSG film using hydrofluoric acid vapor (Vapor HF) to expose the semiconductor substrate, and (f) a wiring connection layer electrically connected to the semiconductor substrate through the interlayer film. And a step of forming the semiconductor device.

According to claim 8 of the present invention,
8. The method of manufacturing a semiconductor device according to claim 7, wherein in the step (a), a diffusion region is formed in the semiconductor substrate sandwiched by the pair of wirings. Then, in the step (f), the wiring connection layer is electrically connected to the diffusion region.

According to claim 9 of the present invention,
(A) a step of selectively forming an element isolation film made of an oxide film on a semiconductor substrate, and (b) a step of forming a diffusion region on the semiconductor substrate adjacent to the element isolation film,
(C) depositing an interlayer film made of an oxide film on the entire surface of the structure obtained in step (b), and (d) selectively implanting phosphorus ions into the interlayer film above the diffusion region. A step of forming an impurity introduction region, and (e) hydrofluoric acid vapor (V
apor HF) to etch the impurity introduction region to expose the diffusion region, and (f) to form a wiring connection layer electrically connected to the diffusion region through the interlayer film. And a method for manufacturing a semiconductor device.

A tenth aspect of the present invention is directed to (a) a step of forming a pair of wirings each having a first sidewall made of an oxide film on a semiconductor substrate, and (b) the step. (A) depositing an interlayer film made of an oxide film on the entire surface of the structure obtained in (a), and (c) selectively etching the interlayer film above the semiconductor substrate sandwiched between the pair of wirings. Thereby, a step of digging a groove whose bottom is located above the first sidewall, (d) a step of forming a second sidewall made of an oxide film on a sidewall of the groove, and (e) ) Phosphorus ions are implanted into the entire surface of the structure obtained in the step (d) from above, and the interlayer film located above the pair of wirings and the trench where the second sidewall allows exposure. Below the bottom Exposing the semiconductor substrate to the step of changing the placed interlayer film and the second sidewall into an impurity introduction region; and (f) etching the impurity introduction region using hydrofluoric acid vapor (Vapor HF). It is a manufacturing method of a semiconductor device provided with a process and (g) a process of forming a wiring connection layer electrically connected with the semiconductor substrate through the interlayer film.

According to an eleventh aspect of the present invention, there is provided a semiconductor device manufacturing method according to the tenth aspect,
In the step (a), a diffusion region is formed in the semiconductor substrate sandwiched by the pair of wirings. Then, in the step (g), the wiring connection layer is electrically connected to the diffusion region.

According to a twelfth aspect of the present invention, (a) a semiconductor substrate, (b) a pair of element isolation films made of an oxide film and selectively formed on the semiconductor substrate, and (c) ) A diffusion region selectively formed on the semiconductor substrate sandwiched between the pair of element isolation films, and (d) formed on a central portion of the pair of element isolation films,
A PSG film which is not formed at the end portion thereof, and (e) the PS
An interlayer film made of an oxide film formed on the G film, and (f)
The semiconductor device includes the interlayer film, the PSG film, the pair of element isolation films, and a wiring connection layer filling a region surrounded by the diffusion region.

According to a thirteenth aspect of the present invention, (a) a semiconductor substrate, (b) a pair of element isolation films made of an oxide film selectively formed on the semiconductor substrate, and (c) ) A diffusion region selectively formed on the semiconductor substrate, sandwiched between the pair of element isolation films, and (d) formed on a central portion of each of the pair of element isolation films, and at an end thereof. Is a semiconductor device including an interlayer film that is not in contact with the oxide film, and (e) a wiring connection layer that fills a region surrounded by the interlayer film, the pair of element isolation films, and the diffusion region.

[0025]

In the method of manufacturing a semiconductor device according to the first aspect of the present invention, Vapor HF etches the PSG film, but hardly etches the semiconductor or the oxide film.

In the method of manufacturing a semiconductor device according to claim 2 of the present invention, the PSG film is deposited without patterning.

In the method of manufacturing a semiconductor device according to the third aspect of the present invention, since the end portion of the element isolation film is not etched, the diffusion region can be largely exposed as long as the element isolation film allows exposure.

In the method of manufacturing a semiconductor device according to the fourth aspect of the present invention, the interlayer film is deposited immediately above the center of the element isolation film.

In the method for manufacturing a semiconductor device according to the fifth aspect of the present invention, by etching the PSG film entirely, the diffusion region can be exposed to a large extent as long as the element isolation film allows the exposure.

In the method of manufacturing a semiconductor device according to claim 6 of the present invention, when etching is performed using Vapor HF, the nitride film is more difficult to etch than the PSG film.

In the method for manufacturing a semiconductor device according to the seventh and eighth aspects of the present invention, the Vapor H
F etches the PSG film, but hardly etches the semiconductor or oxide film.

According to the ninth to eleventh aspects of the present invention, in the method for manufacturing a semiconductor device, Vapor is used.
HF etches an impurity-introduced region into which phosphorus ions are introduced, but hardly etches a semiconductor or an oxide film.

Claims 12 and 13 of the present invention
In the semiconductor device according to the second aspect, electrical connection is made between the wiring connection layer and the diffusion region.

[0034]

【Example】

A. Embodiment using PSG film: (a-1) First embodiment: FIGS. 1 to 6 show the first embodiment of the present invention.
FIG. 7 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the example in the order of steps. First, as shown in FIG. 1, a LOCOS oxide film 2 is selectively formed on the surface of a P-type silicon substrate 1, and a diffusion region 3 is formed therebetween by ion implantation.

Next, a PSG film 4 containing phosphorus is deposited on the entire surface of the structure shown in FIG. 1 (FIG. 2), and an interlayer film 5 is further deposited thereon (FIG. 3). The interlayer film 5 is, for example, CVD.
It is made of a silicon oxide film such as TEOS or HTO formed by the method. Then, dry etching is performed using the patterned resist layer 6 as a mask. At this time, the open portion of the resist layer 6 is located above the diffusion region 3. By this dry etching, the interlayer film 5 and the PSG film 4 are selectively removed according to the pattern of the resist layer 6 (FIG. 4).

After that, the resist layer 6 is removed, and etching using hydrofluoric acid vapor (Vapor HF) is performed.
As a result, only the PSG film 4 can be etched. By etching until it becomes over-etching, the PSG film 4 existing on the end portion of the LOCOS oxide film 2, that is, the portion where the bird's beak is generated is also etched, and the contact hole 7 is punched. Vapor H
Since the etching using F hardly etches the LOCOS oxide film 2, the bird's beak is prevented from being etched. Further, since the silicon is hardly etched, the diffusion region 3 is not etched and the substrate 1 is not exposed.

Therefore, even if the entire diffusion region 3 exposed by the LOCOS oxide film 2 is exposed in the contact hole 7, the substrate 1 is not exposed in the contact hole 7. Therefore, even if the positional accuracy of the contact hole 7 is not significantly increased, it is possible to avoid the situation where the junction leak increases.

After that, by filling the contact hole 7 with the wiring connection layer 8, the wiring connection layer 8 and the diffusion region 3 are electrically connected (FIG. 6). As described above, the diffusion area 3
Since the area exposed in the contact hole 7 can be increased, the contact area between the diffusion region 3 and the wiring connection layer 8 can be widened, and the connection resistance between both can be reduced.

Further, unlike the second and third embodiments described later, the step of patterning the PSG film 4 can be omitted.

(A-2) Second embodiment: In the first embodiment, when the PSG film 4 is over-etched too much, the PSG film 4 shown in the center of FIG. 6 is also etched. There is a possibility that the wiring connection layers 8 located on both sides of the wiring connection layer 8 may be short-circuited. Since such a problem can be easily overcome by controlling the amount of overetching, the effect of the first embodiment on the conventional technique is not impaired. However, in the second embodiment, a technique is disclosed in which even managing such an overetching amount is unnecessary.

7 to 12 are sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps. First, the structure shown in FIG. 1 is obtained by the steps similar to those described with reference to FIG. 1 (FIG. 7).

Further, the PSG film 4 is once formed on the entire surface of the structure shown in FIG. Then, the PSG film 4 is dry-etched using the patterned resist layer 51. As a result, the PSG film 4 is formed so as to extend over the adjacent LOCOS oxide films 2 so as to cover the diffusion region 3 and not to exist near the center of the LOCOS oxide film 2 (FIG. 8). .

Vapor with the resist layer 51 attached.
The PSG film 4 is laterally etched by etching using HF. As a result, the width L3 of the PSG film 4
Is controlled, and the dimension of the contact hole 7 to be opened in the future is determined with respect to the dimension L1 of the diffusion region 3 (FIG. 9). But,
Even if the over-etching progresses, adjacent wirings will not be short-circuited. FIG. 9 shows a case where the width L3 of the PSG film 4 is set to be equal to the dimension L1 of the diffusion region 3.

After that, the resist layer 51 is removed, and the interlayer film 5 is formed on the entire surface (FIG. 10). Then, dry etching is performed using the patterned resist layer 6 as a mask. As a result, the interlayer film 5 and the PSG film 4 are selectively removed according to the pattern of the resist layer 6 (FIG. 11).

After that, the resist layer 6 is removed, and Vapo
Etching with rHF is performed. As a result, only the PSG film 4 can be etched to form the contact hole 7 (FIG. 12). At this time, even if the PSG film 4 is entirely etched, the PSG film 4 was not originally formed in the vicinity of the center of the LOCOS oxide film as shown in FIG. . Therefore, it is not necessary to manage overetching as in the first embodiment.

After this, as shown in FIG. 13, the contact hole 7 is filled with the wiring connection layer 8. Also in the second embodiment,
As in the first embodiment, the problem of increased junction leakage can be avoided.

The width L3 of the PSG film 4 may be set larger than the dimension L1 of the diffusion region 3. FIG. 14 is a sectional view showing such a case. In this case, the resist layer 51
It is possible to omit the lateral etching of the PSG film 4 which is performed with the mark attached. Therefore, as shown in FIG. 14, the resist layer 51 can be removed after the PSG film 4 is patterned.

15 to 18 are sectional views showing the steps described with reference to FIGS. 10 to 13, respectively. In the structure obtained by advancing the process in this way, the diffusion region 3
Since the area exposed by the contact hole 7 can be increased, the wiring connection layer 8 can be formed in the same manner as in the first embodiment.
The connection resistance in the electrical connection between the diffusion region 3 and the diffusion region 3 can be reduced.

Of course, the width L3 of the PSG film 4 can be made smaller than the dimension L1 of the diffusion region 3. FIG. 19 is a cross-sectional view showing a case where there is such a dimensional relationship in the step shown in FIG. Even in such a case, the interlayer film 5 is present above the end of the LOCOS oxide film 2 as in the case shown in FIG. Moreover, since the diffusion region is exposed by etching the PSG film 4, the substrate 1 is not exposed even if the patterning accuracy of the resist layer 6 is not significantly improved. Therefore, there is no increase in junction leak.

(A-3) Third embodiment: FIGS. 20 to 25
FIG. 6A is a sectional view showing a method of manufacturing a semiconductor device according to a third example of the invention in the order of steps. First, as shown in FIG. 20, LOCOS oxide film 2 is selectively formed on the surface of substrate 1, and diffusion region 3 is formed between them by ion implantation.

Next, a PSG film 4 containing phosphorus is formed on the entire surface of the structure shown in FIG. 20, and a nitride film 9 is further formed thereon.
To form a film. Then, these are patterned so as to cover the diffusion region 3 and not to exist near the center of the LOCOS oxide film 2 (FIG. 21). Such patterning can be easily realized by dry etching.

An interlayer film 5 is formed on the entire surface of the structure obtained in FIG. 21 (FIG. 22), and the interlayer film 5 is selectively removed by dry etching using the patterned resist layer 6. The opening of the resist layer 6 is located above the nitride film 9. Generally, in dry etching, the nitride film 9 is less likely to be etched by 10 to 30 times than the PSG film 4. Therefore, as compared with the second embodiment, the bottom portion of the contact hole 7 can be formed more accurately.

Further, the nitride film 9 is removed by wet etching using phosphoric acid, and the PSG film 4 is removed by etching using Vapor HF.
Are perforated (FIG. 24). After that, the contact hole 7 is filled with the wiring connection layer 8, and an electrical connection is obtained between the wiring connection layer 8 and the diffusion region 3 (FIG. 25). Since the bottom portion of the contact hole 7 can be accurately configured, the shape of the wiring connection layer 8 can also be accurately configured.

In the third embodiment as well, it is of course possible to suppress an increase in junction leak without significantly improving the patterning accuracy.

A polysilicon film may be used instead of the nitride film 9. In this case, in the process of proceeding from the structure shown in FIG. 23 to the structure shown in FIG. 24, an isotropic etchant of silicon is used for etching the polysilicon film instead of phosphoric acid.

(A-4) Fourth Embodiment: The present invention can be applied to multilayer wiring. 26 to 3
FIG. 2 is a sectional view showing a method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 26 shows a structure in which a LOCOS oxide film 2 and diffusion regions 3a and 3b are formed on a substrate 1. Further, a wiring 21a having a sidewall made of a silicon oxide film is formed on the LOCOS oxide film 2, a wiring 21b is formed on the substrate 1 sandwiched between the diffusion regions 3a and 3b, and a diffusion region 3b is formed on the diffusion region 3b. 3a
Wirings 21c are respectively formed on the substrate 1 on the opposite side. Both the wirings 21b and 21c have sidewalls made of a silicon oxide film.

PSG is provided between the wiring 21a and the wiring 21b.
The film 31a has a PSG between the wiring 21b and the wiring 21c.
The membranes 31b are respectively filled. And wiring 2
1a to 21c, the interlayer film 3 on the PSG films 31a and 31b
2 is provided on the entire surface. The interlayer film 32 is similar to the interlayer film 5 in that TEOS formed by, for example, the CVD method,
It is made of a silicon oxide film such as HTO.

A patterned resist film 6a is formed on the above structure. The opening of the resist film 6a is located above the diffusion region 3b. The interlayer film 32 is etched using the resist film 6a as a mask. This makes P
The SG film 31b is exposed (FIG. 27).

The resist layer 6a is removed and Vapor H
Only the PSG film 31b is etched by etching using F. As a result, the contact hole 41 is formed (FIG. 28). The wiring connection layer 8 fills the contact hole 41 and is electrically connected to the diffusion region 3b (FIG. 2).
9).

An interlayer film 33 is further formed on the entire surface of the structure obtained by the above steps. The interlayer film 33 is also made of, for example, C
It is made of a silicon oxide film such as TEOS or HTO formed by the VD method. A patterned resist film 6b is formed on the interlayer film 33. The opening of the resist film 6b is located above the diffusion region 3a. Resist film 6b
Both of the interlayer films 32 and 33 are etched using the mask as a mask. As a result, the diffusion region 3a is exposed (FIG. 30).

The resist layer 6b is removed, and Vapor H
Only the PSG film 31a is etched by the etching using F. As a result, the contact hole 42 is formed (FIG. 31). The wiring connection layer 17 fills the contact hole 42 and is electrically connected to the diffusion region 3a (FIG. 3).
2).

When exposing the diffusion regions 3a and 3b, P
Since the contact holes 41 and 42 are formed by etching the SG films 31a and 31b, the sidewalls of the wirings 21a to 21c are not etched. Therefore, similar to the first to third embodiments, the wiring connection layers 8 and 17 are formed.
In either case, no increase in junction leak occurs. Further, the wirings 21a to 21c do not short-circuit with each other. Therefore, the patterning accuracy of the resist layers 6a and 6b is relaxed.

As described above, since the present invention can be applied to the multi-layer wiring, the transfer gate of the DRAM,
The effect can be improved also in the wiring near the word line.

B. Example Using Oxide Film Introduced with Impurities: (b-1) Fifth Example: FIGS. 33 to 37 are sectional views showing a method of manufacturing a semiconductor device according to a fifth example of the present invention in the order of steps. . First, as shown in FIG. 33, a LOCOS oxide film 2 is selectively formed on the surface of a substrate 1, and a diffusion region 3 is formed between them by ion implantation.

Next, an interlayer film 5 is formed on the entire surface of the structure shown in FIG. 33 by, for example, the CVD method, TEOS, HTO.
And a silicon oxide film (FIG. 34).

Then, the patterned resist layer 6 is formed.
Are formed on the interlayer film 5. The opening of the resist layer 6 at this time is located above the diffusion region 3. Then, phosphorus ions are implanted using the resist layer 6 as a mask. As a result, phosphorus ions are introduced into the part 10 of the interlayer film 5 located above the diffusion region 3 (FIG. 35). The implantation amount of phosphorus ions is, for example, on the order of 10 ¹⁵ to 10 ¹⁶ atoms / cm ² .

A part 10 of the interlayer film 5 thus obtained
Is etched by VaporHF, like the PSG film. On the other hand, the interlayer film 5 and the diffusion region 3 into which phosphorus ions have not been introduced are not etched. Therefore, when the resist layer 6 is removed and etching is performed by Vapor HF in the same manner as in the first to third embodiments, the contact hole 7 can be formed as shown in FIG. After that, by filling the contact hole 7 with the wiring connection layer 8, the wiring connection layer 8 and the diffusion region 3 can be electrically connected (FIG. 37).

Also in the fifth embodiment, since the LOCOS oxide film 2 is not etched in the step of exposing the diffusion region 3, the substrate 1 is not exposed. Therefore, the junction leak can be suppressed. Of course, the patterning accuracy of the resist layer 6 is not significantly increased.

(B-2) Sixth Embodiment: The sixth embodiment is the fourth
Similar to the embodiment, a case where the present invention is applied to the case where a diffusion region exists between wirings having a sidewall made of a silicon oxide film will be described.

38 to 43 are sectional views showing a method of manufacturing a semiconductor device according to the sixth embodiment of the present invention in the order of steps. A LOCOS oxide film 2 and a diffusion region 3a are formed on the substrate 1, and a wiring 21a is further formed on the LOCOS oxide film 2.
Wirings 21b are formed on the substrate 1 on the side opposite to the wiring 21a with respect to the diffusion region 3a. Wiring 21
Both a and 21b have sidewalls made of a silicon oxide film. An interlayer film 5 made of a silicon oxide film is formed on the wirings 21a and 21b and the diffusion region 3a.
Are provided (FIG. 38).

A patterned resist layer 6 is provided on the interlayer film 5. The opening of the resist layer 6 is located above the diffusion region 3a. Then, the interlayer film 5 is partially removed from above by dry etching using the resist layer 6 as a mask, and the groove 12 is dug (FIG. 39).

At this time, conventionally, the interlayer film 5 is etched until the diffusion region 3a is exposed, and thereby the contact hole is formed. However, in that case, the dimension L4 of the opening of the resist layer 6 must be smaller than the dimension L5 between the conductive layers 22a and 22b in the wirings 21a and 21b and must be patterned with high accuracy. Otherwise, the conductive layers 22a and 22b are exposed in the contact hole, and when the contact hole is filled with the wiring connection layer, both are short-circuited. Moreover, the bird's beak of the LOCOS oxide film 2 may also be etched.

Thereafter, sidewalls 13 made of an oxide film are formed on the sidewalls of the trench 12 (FIG. 40). And FIG.
Ion implantation of phosphorus ions is performed on the entire surface of the structure shown in FIG. With this, almost all of the sidewalls 13,
The upper portion of the interlayer film 5 and the interlayer film 5 located above the vicinity of the center of the diffusion region 3a become the impurity introduction region 14 (FIG. 4).
1).

As shown in the fifth embodiment, the oxide film into which phosphorus ions are introduced is etched by Vapor HF. Therefore, by performing such etching, the interlayer film 5 is left only at the ends of the diffusion region 3a and around the wirings 21a and 21b. And contact hole 16
Are perforated, where the diffusion region 3a is exposed (FIG. 42).

Since the interlayer film 5 is left around the wirings 21a and 21b, these wirings 21a and 21b are formed.
The side wall b is never etched. That is, the substrate 1 and the conductive layers 22a and 22b are not exposed. Therefore, the contact hole 16 is formed in the wiring connection layer 1
Even if it is filled with 7 (FIG. 43), the junction leak does not increase and the conductive layers 22a and 22b are not short-circuited. Further, since the diffusion region 3a is exposed with a size smaller than the size L4 of the opening of the resist layer 6, it is not necessary to remarkably improve the patterning accuracy of the resist layer 6.

(B-3) Seventh Embodiment: Diffusion region 3a and
Even when the LOCOS oxide film 2 is not provided, by applying the present invention, it is possible to avoid a short circuit between wirings.

44 to 49 are sectional views showing a method of manufacturing a semiconductor device according to the seventh embodiment of the present invention in the order of steps, and correspond to FIGS. 38 to 43, respectively.

First, a pair of wirings 21 are formed on the substrate 1, and the interlayer film 5 is formed on the entire surfaces thereof. Each of the wirings 21 has a sidewall made of a silicon oxide film, and the interlayer film 5 is also made of a silicon oxide film (FIG. 44). The subsequent steps are the same as in the sixth embodiment. The interlayer film 5 is partially etched by using the patterned resist layer 6 as a mask to dig a groove 12 (FIG. 45), and a sidewall 13 is formed on the sidewall of the groove 12 with a silicon oxide film (FIG. 4).
6). Then, by implanting phosphorus ions on the entire surface, the impurity introduction region 14 is obtained (FIG. 47). Vapor HF
The impurity introduction region 14 is etched by etching using the to form the contact hole 16 (FIG. 48), and the contact hole 16 is filled with the wiring connection layer 8 to establish electrical connection with the substrate 1 (FIG. 49).

As shown in the fifth to sixth embodiments, the oxide film introduced with phosphorus ions is etched by Vapor HF, and the oxide film not introduced is not etched. Not etched. Therefore, even if the wiring hole 8 is filled with the wiring connection layer 8, the wirings 21 do not short-circuit. Further, since the substrate 1 is exposed with a size smaller than the size L4 of the opening of the resist layer 6, the resist layer 6
It is not necessary to significantly improve the patterning accuracy of the.

[0081]

In the method for manufacturing a semiconductor device according to the first aspect of the present invention, the diffusion region is exposed without etching the element isolation film and the diffusion region, so that the semiconductor substrate is not exposed. Therefore, the junction formed between the semiconductor substrate and the diffusion region is not exposed, and these are not short-circuited in the wiring connection layer. Therefore, the so-called junction leak does not increase. In addition, no significant accuracy is required for positioning when removing the interlayer film.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, the step of patterning the PSG film is unnecessary.

In the method of manufacturing a semiconductor device according to claim 3 of the present invention, the connection resistance between the diffusion region and the wiring connection layer can be reduced.

In the method for manufacturing a semiconductor device according to claim 4 of the present invention, even if the PSG film is entirely etched, adjacent wiring connection layers do not short-circuit.

In the method for manufacturing a semiconductor device according to claim 5 of the present invention, the connection resistance between the diffusion region and the wiring connection layer can be reduced.

In the method of manufacturing a semiconductor device according to claim 6 of the present invention, the shape of the contact hole formed by the interlayer film can be accurately configured, and the shape of the wiring connection layer filling the contact hole can also be accurately configured. be able to.

In the method of manufacturing a semiconductor device according to claim 7 of the present invention, since the wiring connection layer can be formed without etching the sidewalls of the wiring, no short circuit occurs between the wirings.

In the method of manufacturing a semiconductor device according to claim 8 of the present invention, the junction formed between the semiconductor substrate and the diffusion region is not exposed, and they are not short-circuited in the wiring connection layer. Therefore, the so-called junction leak does not increase. In addition, no significant accuracy is required for positioning when removing the interlayer film.

In the method of manufacturing a semiconductor device according to the ninth aspect of the present invention, the diffusion region is exposed without etching the element isolation film and the diffusion region, so that the semiconductor substrate is not exposed. Therefore, the junction formed between the semiconductor substrate and the diffusion region is not exposed, and these are not short-circuited in the wiring connection layer. Therefore, the so-called junction leak does not increase.

In the method of manufacturing a semiconductor device according to the tenth aspect of the present invention, since the wiring connection layer can be formed without etching the sidewalls of the wiring, no short circuit occurs between the wirings.

In the semiconductor device manufacturing method according to the eleventh aspect of the present invention, the junction formed between the semiconductor substrate and the diffusion region is not exposed, and they are not short-circuited in the wiring connection layer. Therefore, the so-called junction leak does not increase.

Claims 12 and 13 of the present invention
In the semiconductor device according to the above, the interlayer film, the element isolation film,
The presence of the PSG film insulates the wiring connection layer from regions other than the diffusion region. Moreover, since the contact surface between the diffusion region and the wiring connection layer is wide, the connection resistance in this portion can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the first embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 8 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 9 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 10 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 12 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 13 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 14 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 15 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 16 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 17 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 18 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 19 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the second embodiment of the present invention in the order of steps.

FIG. 20 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 21 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 22 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 23 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 24 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 25 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment of the present invention in the order of steps.

FIG. 26 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 27 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 28 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 29 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 30 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 31 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 32 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment of the present invention in the order of steps.

FIG. 33 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention in the order of steps.

FIG. 34 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention in the order of steps.

FIG. 35 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention in the order of steps.

FIG. 36 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention in the order of steps.

FIG. 37 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the fifth embodiment of the present invention in the order of steps.

FIG. 38 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention in the order of steps.

FIG. 39 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention in the order of steps.

FIG. 40 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention in the order of steps.

FIG. 41 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention in the order of steps.

FIG. 42 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention in the order of steps.

FIG. 43 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the sixth embodiment of the present invention in the order of steps.

FIG. 44 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the seventh embodiment of the present invention in the order of steps.

FIG. 45 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the seventh example of the present invention in the order of steps.

FIG. 46 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the seventh embodiment of the present invention in the order of steps.

FIG. 47 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the seventh example of the present invention in the order of steps.

FIG. 48 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the seventh example of the present invention in the order of steps.

FIG. 49 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the seventh example of the present invention in the order of steps.

FIG. 50 is a cross-sectional view showing a conventional technique.

FIG. 51 is a cross-sectional view showing a conventional technique.

FIG. 52 is a cross-sectional view showing a conventional technique.

[Explanation of symbols]

1 silicon substrate, 2 LOCOS oxide film, 2a bird's beak, 3,3a, 3b diffusion region, 4, 31a, 3
1b PSG film, 5, 32, 33 interlayer film, 7, 16,
41, 42 contact hole, 8, 17 wiring connection layer, 9
Nitride film, 14 impurity introduction region, 21, 21a to 21c
wiring.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 21/768 21/316 H01L 21/90 D 8418-4M 21/94 A

Claims (13)

[Claims] 1. A process of (a) selectively forming an element isolation film made of an oxide film on a semiconductor substrate, and (b) forming a diffusion region on the semiconductor substrate adjacent to the element isolation film. And (c) forming a PSG film on at least the diffusion region, and (d) depositing an interlayer film made of an oxide film on the entire surface of the structure obtained in step (c). e) a step of selectively removing the interlayer film above the diffusion region to expose the PSG film, and (f) the PS film using hydrofluoric acid vapor (Vapor HF).
Manufacturing a semiconductor device, comprising: a step of etching a G film to expose the diffusion region; and a step of (g) forming a wiring connection layer electrically connected to the diffusion region through the interlayer film. Method. 2. In the step (c), a PSG film is deposited on the entire surface of the structure obtained in the step (b),
The method for manufacturing a semiconductor device according to claim 1. 3. The method of manufacturing a semiconductor device according to claim 2, wherein in the step (f), the PSG film is etched until the end portion of the element isolation film is exposed without exposing the central portion of the element isolation film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein in the step (c), the PSG film is deposited so that the vicinity of the center of the element isolation film is exposed. 5. The method of manufacturing a semiconductor device according to claim 4, wherein in the step (c), the PSG film is deposited so as to cover an end portion of the element isolation film. 6. The step (c) includes the step (c-1) of providing a patterned nitride film on the PSG film on the PSG film.
The manufacturing method of the semiconductor device described in the above. 7. (a) a step of forming a pair of wirings each having a sidewall made of an oxide film on the semiconductor substrate; and (b) a step of forming a pair of wirings on the semiconductor substrate sandwiched by the pair of wirings. A step of forming a PSG film, (c) a step of depositing an interlayer film made of an oxide film on the entire surface of the structure obtained in the step (b), and (d) selecting the interlayer film above the PSG film. To remove the PSG film to remove the PSG film by (e) using hydrofluoric acid vapor (Vapor HF).
Manufacturing a semiconductor device, comprising: a step of etching a G film to expose the semiconductor substrate; and (f) a step of forming a wiring connection layer electrically connected to the semiconductor substrate through the interlayer film. Method. 8. A diffusion region is formed in the semiconductor substrate sandwiched by the pair of wirings in the step (a), and the wiring connection layer is electrically connected to the diffusion region in the step (f). The method for manufacturing a semiconductor device according to claim 7, wherein the method is performed. 9. (a) a step of selectively forming an element isolation film made of an oxide film on the semiconductor substrate; (b) forming a diffusion region on the semiconductor substrate adjacent to the element isolation film. And (c) a step of depositing an interlayer film made of an oxide film on the entire surface of the structure obtained in the step (b), and (d) a phosphorus ion selectively to the interlayer film above the diffusion region. To form an impurity introduction region, (e) a step of etching the impurity introduction region using hydrofluoric acid vapor (Vapor HF) to expose the diffusion region, and (f) the diffusion region And a step of forming a wiring connection layer electrically connected through the interlayer film. 10. (a) A step of forming a pair of wirings each having a first sidewall made of an oxide film on a semiconductor substrate, and (b) the entire surface of the structure obtained in the step (a). And (c) selectively etching the interlayer film above the semiconductor substrate sandwiched by the pair of wirings so that the bottom portion of the interlayer film is the first film. A step of digging a groove located above the side wall, (d) a step of forming a second side wall made of an oxide film on a side wall of the groove, and (e) obtained in the step (d). On the whole surface of the structure,
Phosphorus ions are implanted from above, the interlayer film positioned above the pair of wirings, the interlayer film positioned below the bottom of the trench where the second sidewall allows exposure, and the second film. And (f) etching the impurity-doped region using hydrofluoric acid vapor (Vapor HF) to expose the semiconductor substrate, and (g) the semiconductor substrate. And a step of forming a wiring connection layer electrically connected through the interlayer film. 11. A diffusion region is formed in the semiconductor substrate sandwiched by the pair of wirings in the step (a), and the wiring connection layer is electrically connected to the diffusion region in the step (g). The method for manufacturing a semiconductor device according to claim 10, wherein the method is performed. 12. (a) a semiconductor substrate; (b) a pair of element isolation films made of an oxide film and selectively formed on the semiconductor substrate; and (c) sandwiched between the pair of element isolation films. A diffusion region selectively formed on the semiconductor substrate, and (d) a PSG film formed on the central portion of the pair of element isolation films and not formed on the end portions thereof, (e) An interlayer film made of an oxide film formed on the PSG film, and (f) a wiring connection layer filling the region surrounded by the interlayer film, the PSG film, the pair of element isolation films, and the diffusion region. A semiconductor device comprising. 13. A semiconductor substrate; (b) a pair of element isolation films made of an oxide film, which is selectively formed on the semiconductor substrate; and (c) sandwiched between the pair of element isolation films. And a diffusion region selectively formed on the semiconductor substrate, and (d) an interlayer film formed of an oxide film that is formed on the central portion of each of the pair of element isolation films and does not contact the end portions thereof. And (e) a semiconductor device comprising the interlayer film, the pair of element isolation films, and a wiring connection layer filling a region surrounded by the diffusion region.