KR20010006944A - Semiconductor integrated circuit device and process for fabricating thereof - Google Patents

Abstract

PURPOSE: To facilitate scale down of a semiconductor device by respectively forming a contact plug to the predetermined contact hole amount a plurality of contact holes and a first wiring layer on the remaining contact holes with single dry-etching process of the one conductive film. CONSTITUTION: An element isolation region 2 is formed in the predetermined region at the surface of a silicon substrate 1 and moreover a gate insulation film 3 is also formed. On the gate insulation film 3, a gate electrode 4 is covered with a protection insulation film 5 to form diffused layers 6, 6a in the region located between the gate electrodes 4. A first conductive layer 8 is formed in such a manner as being connected with the diffused layer 6 as the wiring layer in the contact hole formed in the region including a first interlayer insulation film 7. Moreover, a contact plug 9 is formed in such a manner as being connected with the diffused layer 6a in the contact hole formed in the region including the first interlayer insulation film 7. There first conductive layer 8 and contact plug 9 are processed with single dry-etching process.

Description

Semiconductor integrated circuit device and manufacturing method therefor {SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR FABRICATING THEREOF}

The present invention relates to a semiconductor integrated circuit device, and more particularly, to a semiconductor integrated circuit device and a method for manufacturing a semiconductor integrated circuit device in which contacts between conductive wires are formed at different levels.

Due to the increased integration density of semiconductor integrated circuit devices, circuit components are miniaturized.

These circuit components are reduced not only in the horizontal direction but also in the vertical direction. However, the reduction in the vertical direction is lessened than the reduction in the horizontal direction. This increases the unevenness of the surface of the semiconductor integrated circuit device. In other words, when the integrated density is improved, the shape of the semiconductor integrated circuit device is increased.

The shape of the semiconductor integrated circuit device is greatly affected by the vertical contacts of the semiconductor integrated circuit device. The aspect ratio of the contact hole increases. Thus, interconnection through contact holes with large aspect ratios is more difficult than interconnection through conventional contact holes.

In order to connect a conductive part through a contact hole with a large aspect ratio, the contact hole is filled with a conductive material. The conductive material is called as a so-called contact plug. Impurity regions and conductive strips or conductive strips of varying levels are connected through contact plugs.

A typical example of a method for forming a contact plug is disclosed in Japanese Unexamined Patent Publication No. 9-191084. The conventional method is illustrated in Figures 1A-1G.

The conventional method starts with preparing the silicon substrate 101. An insulating region 102, such as trench isolation, is optionally formed on the silicon substrate 101. The surface portion of the silicon substrate 101 is oxidized so that the silicon substrate 101 is covered with a thin silicon oxide layer 103. Subsequently, a conductive material is deposited on the thin silicon oxide layer 103 to form the conductive layer 104. Silicon nitride is deposited on the conductive layer 104 and a silicon nitride layer 105 is deposited on the conductive layer 104 as shown in FIG. 1A.

Although not shown in FIG. 1B, an etching mask is patterned on the silicon nitride layer 105 by using photolithographic techniques, and the silicon nitride layer 105, the conductive layer 104, and the thin silicon oxide layer 103 are formed. It is selectively etched by this dry etching. As a result, as shown in FIG. 1B, the gate insulating layer 103, the gate electrode 107, and the upper protective insulating layer 106 remain on the silicon substrate 101. The gate insulating layer 103, the gate electrode 107, and the upper protective insulating layer 106 are combined to form a gate structure.

Subsequently, sidewall spacers 108 are formed on the gate structures 103/107/106, and dopant impurities are introduced into the exposed surface of the silicon substrate 101. Therefore, the impurity regions 109 are formed in the silicon substrate 101 at predetermined intervals. Silicon oxide is deposited on the entire surface by chemical vapor deposition to form a silicon oxide layer. The silicon oxide layer is planarized through chemical mechanical polishing, and the first interlayer insulating layer 110 is formed as shown in FIG. 1C.

An etch mask (not shown) is formed on the first interlayer insulating layer 110 by using photolithographic techniques, and the first interlayer insulating layer 110 is selectively etched. And the contact hole 111 is formed as shown in Figure 1d.

Subsequently, a conductive material such as phosphorus doped polycrystalline silicon is deposited on the front surface of the final structure. The conductive material fills and swells the contact hole 111 to form a conductive material layer. The conductive material layer on the first interlayer insulating layer 110 is removed from the final structure, and the contact plugs 112 / 112a remain in the contact holes. The contact plugs 112 / 112a are kept in contact with the impurity region 109. This contact plug 112 / 112a is called a contact pad. Silicon oxide is then deposited on the front of the final structure to form a second interlayer dielectric layer 113 as shown in FIG. 1E.

Subsequently, a second contact hole 114 is formed in the second interlayer insulating layer 113, and some contact plugs 112 are exposed with respect to the second contact hole 114. The first level of conductive strip 115 is formed on the second interlayer insulating layer 113. The conductive strip 115 penetrates into the second contact hole 114 and remains in contact with the contact plug 112 as shown in FIG. 1F.

Subsequently, silicon oxide is deposited on the entire surface of the final structure to form a third interlayer insulating layer 116. The third contact hole 117 is formed in the second and third interlayer insulating layers 113 and 116, and the contact plug 112a is exposed with respect to the third contact hole 117 as shown in FIG. 1C.

Although not shown in the figures, a second level conductive strip is formed on the third interlayer insulating layer 116 and remains in contact with the contact plug 112a through the third contact hole.

However, the conventional method has the following problems. First, the conventional method involves a large number of process steps, which makes the manufacturing process complicated. First, contact plugs 112a / 112a are formed for the first level conductive strip 115 and the second level conductive strip, and then the first level conductive strip 115 and the second level conductive strip are formed. It is formed in a step shape. Photolithography and etching are repeated for these steps, which complicates the conventional process. For this reason, the conventional process is expensive and the manufacturing cost is increased. This is the first problem inherent in the conventional method.

A second problem is the large semiconductor substrate 101 required for integrated circuits. The first level of conductive strip 115 is expected to be located on the top surface of the contact plug 112, and the second level of conductive strip 115 is expected to be located on the top surface of the contact plug 112a. However, in the case of photolithography, a matching margin is required. This means that the contact holes 111 are widely spaced from each other. Therefore, the manufacturer needs a large silicon substrate 101 due to the matching margin. That is, the conventional method is not suitable for the next generation of ultra-large scale semiconductor integrated circuit devices.

Therefore, an important object of the present invention is to provide a semiconductor integrated circuit of a structure that allows the manufacturer to improve the integration density.

It is also an important object of the present invention to provide a semiconductor integrated circuit having a structure that is simple and allows a manufacturer to reduce manufacturing costs.

In order to achieve this object, the present invention proposes simultaneously forming a contact plug and a first level conductive strip.

According to one feature of the invention, a semiconductor integrated circuit device manufactured on a semiconductor substrate includes at least two conductive portions formed on a main surface of the semiconductor substrate, a hole covering the at least two conductive portions and exposing the at least two conductive portions. A first insulating layer having one of the holes, a contact plug formed in one of the holes and held in contact with an associated conductive part of the at least two conductive parts, and formed on the first insulating layer and through the at least one of the holes. A first conductive strip which is kept in contact with another of the two conductive parts, a second insulating layer having the first insulating layer and the first conductive strip covering the first conductive strip and having a hole through which the contact plug is exposed, and the second And a second conductive strip formed on the insulating layer and held in contact with the contact plug through the hole.

According to another feature of the invention, a method of manufacturing a semiconductor integrated circuit device, the method comprising the steps of preparing a semiconductor substrate, forming at least two conductive portions on the main surface of the semiconductor substrate, the at least Covering the two conductive portions, forming holes in the insulating layer in a manner such that the at least two conductive portions are respectively exposed to the holes, forming a conductive layer filling the holes and extending onto the first insulating layer. A contact plug held in contact with one of the at least two conductive portions through an associated one of the holes and a contact plug with the other conductive portion of the at least two conductive portions through a remaining hole of the holes; Patterning the first conductive strip having a height different from that of the contact plug, the first insulating layer as a second insulating layer, Covering the contact plug and the first conductive strip, forming a hole in the second insulating layer in a manner that exposes the contact plug to the hole, and maintains contact with the contact plug through the hole and the first plug; Forming a second conductive strip extending over the second insulating layer.

1A to 1G are cross-sectional views showing a conventional method.

2 is a cross-sectional view showing a method of manufacturing a semiconductor integrated circuit device according to the present invention.

3A-3G are cross-sectional views illustrating a method of manufacturing a semiconductor integrated circuit device in accordance with the present invention.

4 is a cross-sectional view illustrating a method of manufacturing another semiconductor integrated circuit device in accordance with the present invention.

5A-5G are cross-sectional views illustrating a method of manufacturing a semiconductor integrated circuit device in accordance with the present invention.

<Description of the code | symbol about the principal part of drawing>

1: silicon substrate

2: insulation area

3: gate insulating layer

4: gate electrode

5: protective insulation layer

6a / 6: Source / Drain Area

7: first interlayer insulating layer

8: first level conductive strip

9: contact plug

10: second interlayer insulating layer

11: second level conductive strip

Features and advantages of the semiconductor integrated circuit device and method will be more readily understood from the following detailed description, which is described in conjunction with the accompanying drawings.

First, referring to FIG. 2, the semiconductor integrated circuit device of the present invention is manufactured on a silicon substrate 1. An insulating region 2 is formed in the silicon substrate 1 and defines a plurality of active regions. A plurality of field effect transistors is selectively assigned to the plurality of active regions. The source / drain regions 6a / 6 are formed in the surface portion of the silicon substrate 1 at predetermined intervals, and the silicon substrate 1 between the source / drain regions 6a / 6 serves as a channel region of the field effect transistor. do. The channel region is covered with the gate insulating layer 4, and the gate electrode 4 is laminated on the thin gate insulating layer 3, respectively. The gate electrode 4 is surrounded by the protective insulating layer 5, respectively. The gap is defined between the protective insulating layers 5. The first interlayer insulating layer 7 is formed on the protective insulating layer 5, and contact holes are formed in the first interlayer insulating layer 7. Since the gap is connected to the contact hole, the source / drain area is opened in the direction of the contact hole.

The contact plug 9 is selectively formed in the contact hole and the gap and remains in contact with the source region 6a. The first level of conductive strip 8 is formed on the first interlayer insulating layer 7 and is kept in direct contact with the drain region 6 via contact holes and gaps.

The first level of conductive strip 8 is covered with a second interlayer insulating layer 10 and contact holes are formed in the second interlayer insulating layer 10. The contact plug 9 is exposed to the contact holes formed in the second interlayer insulating layer 10. The second level conductive strip 11 is formed on the second interlayer insulating layer 11 and is kept in contact with the contact plug 9 through a contact hole formed in the second interlayer insulating layer 10.

The distance between the first level conductive strip 8 and the silicon substrate 1 is shorter than the distance between the second level conductive strip 11 and the silicon substrate 1. In the case of the second level conductive strip 11, a contact plug 9 is required, but the first level conductive strip 8 is closer to the silicon substrate 1 than the second level conductive strip 11. The one level conductive strip 8 remains in contact with the drain region 6 without any contact plugs. This means that no matching margin is needed for the first level of conductive strip 8. As a result, the field effect transistors are integrated on the silicon substrate 1 at a high density. Therefore, the structure shown in FIG. 2 is desirable for the next generation of ultra-large scale semiconductor integrated circuit device.

The semiconductor integrated circuit device is manufactured as follows. 3A-3G illustrate a method of manufacturing a semiconductor integrated circuit device. The method starts with the step of preparing the silicon substrate 1, wherein the insulating region 2 is selectively formed in the surface portion of the silicon substrate 1. The thin silicon oxide layer 3a is grown on the main surface of the silicon substrate 1 and is about 10 nm thick.

Then, tungsten silicide is deposited on the thin silicon oxide layer 3a to form a 200 nm thick tungsten silicide layer 12. A silicon nitride layer is deposited on the tungsten silicide layer 12 to form a 150 nm thick silicon nitride layer 13. The final structure is shown in Figure 3a.

The photoresist solution is spun on and baked on the silicon nitride layer 13 to form a photoresist layer. The pattern image for the gate electrode is transferred to the photoresist layer and a latent image is formed on the photoresist layer. The latent image is developed and the photoresist layer is patterned with a photoresist etching mask (not shown). Thus, a photoresist etching mask is formed on the silicon nitride layer 13 through photolithography.

The silicon nitride layer 13, tungsten silicide layer 12 and silicon oxide layer 3 are selectively etched by dry etching. After completion of the dry etching, the thin gate insulating layer 3, the gate electrode 4 and the upper insulating layer 14 remain on the main surface of the silicon substrate 1 as shown in FIG. 3B. The gate electrodes 4 are about 200 nm long and spaced apart from each other at intervals of 200 nm. The gate insulating layer 3, the gate electrode 4 and the upper insulating layer 14 constitute a gate structure as a whole.

Subsequently, silicon nitride is deposited on the front surface of the final structure, and a 50 nm thick silicon nitride layer is formed homogeneously. The silicon nitride layer is etched back and sidewall spacers 15 are formed on the sides of the gate structure. The upper insulating layer 14 and the sidewall spacers 15 constitute the protective insulating layer 5 as a whole.

Dopant impurities are introduced into the silicon substrate 1 exposed in the gap between the sidewall spacers 15 and form source / drain regions 6a / 6. The solution of hydrogen containing silicon oxide diffuses over the front of the final structure and is heat treated at 100 to 200 ° C. The final structure is then covered with a hydrogen containing silicon oxide layer. The hydrogen containing silicon oxide layer is annealed at 450 ° C. in a vacuum of 10 ⁻⁹ torr to 10 ⁻³ torr. After the annealing is completed, the hydrogen-containing silicon oxide layer further contains about several percent hydrogen. Hydrogen silsesquioxane, abbreviation "HSQ", may be used as the hydrogen containing silicon oxide. Thus, the final structure is covered with a hydrogen containing silicon oxide layer as shown in FIG. 3C to act as the first interlayer insulating layer 7.

The photoresist etch mask 16 is then patterned on the first interlayer insulating layer 7 by photolithography to selectively etch the first interlayer insulating layer 7. The protective insulating layer 5 is hardly etched because the protective insulating layer is made of silicon nitride. Thus, a contact hole 17 is formed in the first interlayer insulating layer 7 and leads to a gap between the gate structures shown in FIG. 3D. The contact hole 17 has a dimension of about 200 nm.

Subsequently, phosphorus doped polycrystalline silicon or arsenic doped polycrystalline silicon is deposited on the front surface of the final structure. Doped polycrystalline silicon fills and swells the gap and contact hole 17 to form a conductive layer 18. Polycrystalline tungsten silicide is deposited over the conductive layer 18 and forms a 150 nm thick silicide layer 19 as shown in FIG. 3E.

A 200 nm thick hard mask 20 is patterned on the silicide layer 19. For example, the hard mask 20 is formed of silicon oxide deposited by chemical vapor deposition and has a dimension of about 300 nm. The silicide layer 19 and the conductive layer 18 are selectively etched by using the hard mask 20 as an etching mask and using anisotropic dry etching under the following conditions. As a feed gas from which plasma is generated, a gas mixture of Cl ₂ , HBr and O ₂ is used. Hydrogen is released from the first interlayer insulating layer 7 when the first interlayer insulating layer 7 is exposed. Hydrogen reacts with the feed gas and reduces the amount of species in the plasma state. This ends the anisotropic dry etching. Thus, the first interlayer insulating layer 7 is exposed to a gap below the recessed space formed in the hard mask 20 and the contact plug 9 and the first level conductive strip 8 are shown in FIG. 3F. Formed at the same time. For example, each of the contact plugs 9 has a wider upper portion than the lower portion and is classified as a contact pad. The first level of conductive strip 8 has a stacked structure of doped polycrystalline silicon layer and silicide layer.

No matching margin is required for the conductive strip 8 of the first level, i.e. the boundary between the lower part kept in contact with the drain region 6 and the upper part on the first interlayer insulating layer 7. Thus, the first level of conductive strip 8 is formed in the first interlayer insulating layer 7 at a narrower interval than that of the conventional first level of conductive strip 115.

Subsequently, the second interlayer insulating layer 10 is formed on the final structure by chemical vapor deposition and the second contact hole 21 is formed in the second interlayer insulating layer 10. The contact plug 9 is exposed to the second contact hole 21 as shown in FIG. 3G.

Finally, a second level conductive strip 11 is formed on the second interlayer insulating layer 10 and connected to the contact plug 9 as shown in FIG.

As can be seen from the above description, the contact plug 9 and the first level conductive strip 8 are formed simultaneously through anisotropic dry etching. Photolithography and dry etching on the contact plugs 112 / 112a were removed in the process according to the present invention. Thus, the process according to the invention is simpler than the conventional process.

By acting as an etch stopper, the hydrogen containing silicon oxide allows the manufacturer to precisely control the anisotropic etching using the first interlayer insulating layer 7 of the hydrogen containing silicon oxide.

Second embodiment

4 illustrates a structure of another semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit device of the second embodiment is similar to the semiconductor integrated circuit device of the first embodiment except for the contact plug 9a. Other layers and regions of the second embodiment are denoted by reference numerals representing corresponding layers and regions of the first embodiment for simplicity of explanation.

The field effect transistor 3/4/6 / 6a is covered with the protective insulating layer 5, and the contact plug 9a is formed in the contact hole formed in the first interlayer insulating layer. The first interlayer insulating layer remains in the gap between the protective insulating layers 5. The contact plug 9a does not extend to the upper surface of the protective insulating layer 5. The contact plug 9a is kept in contact with the source region 6a.

The first level of conductive strip 8 is patterned directly on the conductive insulating layer 5 and remains in contact with the drain region 6. The first level of conductive strip 8 is covered with a second interlayer insulating layer 10 and contact holes are formed in the second interlayer insulating layer. The contact plug 9a is exposed to the contact hole and the second level conductive strip 11 is kept in contact with the contact hole 9a through a contact hole formed in the interlayer insulating layer 10.

The semiconductor integrated circuit device is manufactured as follows. 5A through 5G illustrate a process of manufacturing a semiconductor integrated circuit device. The insulating region 2 is formed in the silicon substrate 1 similarly to the first embodiment. The thin silicon oxide layer 3a is grown on the main surface of the silicon substrate 1 and is formed to a thickness of about 5 nm.

Then, tungsten silicide is deposited on the thin silicon oxide layer 3a to form a 150 nm thick tungsten silicide layer 12. Silicon nitride is deposited on the tungsten silicide layer 12 to form a silicon nitride layer 13 having a thickness of 100 nm. The final structure is shown in FIG. 5A.

A photoresist etch mask is formed on the silicon nitride layer 13 through photolithography. The silicon nitride layer 13, tungsten silicide layer 12 and silicon oxide layer 3 are selectively etched by dry etching. After the dry etching is completed, the thin gate insulating layer 3, the gate electrode 4 and the upper insulating layer 14 remain on the main surface of the silicon substrate 1 as shown in FIG. 5B. The gate electrodes 4 have a length of about 150 nm and are spaced apart from each other at intervals of 150 nm. The gate insulating layer 3, the gate electrode 4 and the upper insulating layer 14 constitute a gate structure as a whole.

Subsequently, silicon nitride is deposited on the front surface of the final structure and a 30 nm thick silicon nitride layer is formed homogeneously. The silicon nitride layer is etched back and sidewall spacers are formed on the sides of the gate structure. The upper insulating layer 14 and the sidewall spacers constitute the protective insulating layer 5 as a whole. Dopant impurities are introduced into the silicon substrate 1 exposed in the gap between the protective insulating layers 5 and form source / drain regions 6a / 6.

Silicon oxide is deposited on the front of the final structure by chemical vapor deposition. Silicon oxide fills in the gap between the protective insulating layers 5 and swells into the silicon oxide layer. The silicon oxide layer is chemically mechanically polished and the first interlayer insulating layer 7a is left in the gap between the protective insulating layers 5 as shown in FIG. 5C. The protective insulating layer 5 acts as a polishing stopper and the first interlayer insulating layer 7a is never left on the protective insulating layer 5.

The photoresist etch mask 16 is then patterned on the protective insulating layer 5 and the first interlayer insulating layer 7 by photolithography and the first interlayer insulating layer 7 is selectively etched. The protective insulating layer 5 is hardly etched because the protective layer is formed of silicon nitride. Thus, a contact hole 17a is formed in the first interlayer insulating layer 7a, and the source / drain regions 6a / 6 are exposed to the contact hole 17a as shown in FIG. 5D. The contact hole 17a has a dimension of about 100 nm.

The final structure is then covered with a conductive layer 18a, and a 150 nm thick silicide layer 19 is deposited on the conductive layer 18a as shown in FIG. 5E. For example, the conductive layer 18a is formed of phosphorus doped amorphous silicon or arsenic doped amorphous silicon, and the silicide layer 19 is also amorphous.

A 200 nm thick hard mask 20 is patterned on the silicide layer 19. For example, the hard mask 20 is formed of silicon oxide deposited by plasma chemical vapor deposition and has a dimension of about 200 nm. The silicide layer 19 and the conductive layer 18a are selectively etched by using the hard mask 20 as an etching mask and using anisotropic dry etching. Anisotropic etching was performed on the conditions similar to 1st Example. As described above, since the conductive layer 18a and the silicide layer 19 are amorphous, the surface configuration is more relaxed than the surface configuration of the first embodiment. For this reason, the end of the anisotropic dry etching is easily determined. The contact plug 9a and the first level of conductive strip 8 are formed simultaneously as shown in FIG. 5F. For example, each of the contact plugs 9 has an upper surface which is not higher than the upper surface of the protective insulating layer 5.

Amorphous silicon and amorphous silicide are crystallized through heat treatment and coated with polycrystalline silicon and polycrystalline silicide. The first level conductive strip 8 has a laminated structure of a doped polycrystalline silicon layer and a polycrystalline silicide layer and the contact plug 9a is formed of polycrystalline silicon.

No matching margin is required for the conductive strip 8 of the first level, i.e. the boundary between the lower part kept in contact with the drain region 6 and the upper part over the protective insulating layer 5. Therefore, the first level conductive strip 8 is formed in the protective insulating layer 5 at a narrower interval than that of the conventional first level conductive strip 115.

Subsequently, the second interlayer insulating layer 10 is formed on the final structure by chemical vapor deposition and the second contact hole 21 is formed in the second interlayer insulating layer 10. The contact plug 9 is exposed to the second contact hole 21 as shown in FIG. 5G.

Finally, a second level conductive strip 11 is formed on the second interlayer insulating layer 10 and connected to the contact plug 9 as shown in FIG.

The process shown in FIGS. 5A-5G is simpler than the conventional process, and the contact plug 9a is never shorted with the conductive strip 8 of the first level. This is because the contact plug 9a is formed inside the contact hole 17a.

2 and 4 may be applied to a dynamic random access memory cell. For example, the first conductive strip 8 acts as a bit line, and the field effect transistors 3/4/6 / 6a each act as an access transistor of a dynamic random access memory cell. The second conductive strip 11 is covered with a dielectric layer and the counter electrode is opposed to the second conductive strip 11 through the dielectric layer.

As can be seen from the description above, the first level of conductive strip 8 remains in direct contact with the drain region 6 and no matching margin is required for the first level of conductive strip. . For this reason, the conductive strip 8 of the first level is arranged at a high density. Therefore, the process according to the present invention can be applied to the next generation of ultra-large scale semiconductor integrated circuit device.

In addition, the contact plug 9a and the first level of conductive strip 8 are formed simultaneously to simplify the process sequence than the conventional process.

In the case where the first interlayer insulating layer is formed of hydrogen containing silicon oxide, hydrogen is released from the hydrogen containing silicon oxide during the dry etching after exposure to automatically terminate the dry etching. Therefore, dry etching is well controlled due to the hydrogen containing silicon oxide.

While specific embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention.

For example, the present invention can be applied to vertical interconnects in through holes formed in an interlayer insulating layer.

In the above-described embodiment, the contact plug 9a and the first level conductive strip 8 are alternately arranged with the gate electrode 4, but between the contact plug 9a and the first level conductive strip 8. One or more gate electrodes may be formed.

Claims (17)

In the semiconductor integrated circuit device manufactured on the semiconductor substrate 1, At least two conductive portions 6 / 6a formed on the main surface of the semiconductor substrate, A first insulating layer 5/7, 5 / 7a covering the at least two conductive portions and having holes 17, 17a exposing the at least two conductive portions, Contact plugs 9 and 9a formed in one of the holes and held in contact with an associated conductive portion 6a of the at least two conductive portions, A first conductive strip 8 formed on the first insulating layer and electrically connected to another of the at least two conductive parts 6, A second insulating layer 10 having a hole 21 covering the first insulating layer and the first conductive strip and exposing the contact plug, and A second conductive strip 11 formed on the second insulating layer and held in contact with the contact plug through the hole; Including And said first conductive strip (8) is held in contact with another of said at least two conductive parts (6) through an associated one of said holes. 2. The gate structure according to claim 1, wherein each gate structure (3/4/5) formed on the main surface at predetermined intervals, and a surface portion of the semiconductor substrate, are defined between the gate structures and act as part of the holes. And a plurality of field effect transistors comprising source and drain regions (6 / 6a) exposed in the gap, wherein the conductive portion is comprised of two source / drain regions. 3. The gate structure according to claim 2, wherein the gate structure comprises a gate insulating layer 3 formed on the main surface, a gate electrode 4 formed on the gate insulating layer 3, and the gate electrode at predetermined intervals. And each protective insulating layer (5) covering and defining said gap and acting as part of said first insulating layer. 4. The protective insulating layer (5) of the gate structure is covered by a first interlayer insulating layer (7) which acts as another part of the first insulating layer, and the contact plug (9) A semiconductor integrated circuit device, characterized in that it is formed in an interlayer insulating layer (7) and occupies the upper surface of the protective insulating layer (5) of a hollow space acting as another part of one of the holes. 5. The semiconductor integrated circuit device according to claim 4, wherein the first interlayer insulating layer (7) further acts as an etch stopper during manufacture. The side surface of the protective insulating layer (5) is covered with a first interlayer insulating layer (7a) forming the first insulating layer together with the protective insulating layer, and the hole (17a) is the gap. The semiconductor integrated circuit device, characterized in that located in. 7. The semiconductor integrated circuit device according to claim 6, wherein the contact plug (9a) has a top surface coplanar or less than the top surface of the protective insulating layer. 3. The method of claim 2, wherein one of the plurality of field effect transistors (3/4/5/6 / 6a), the first conductive strip (8) and the second conductive strip (11) are formed of a dynamic random access memory cell. And an accumulation transistor of an access transistor, a bit line and a storage capacitor of said random access memory cell. In the method of manufacturing a semiconductor integrated circuit device, a) preparing a semiconductor substrate 1, b) forming at least two conductive portions 6 / 6a on the main surface of the semiconductor substrate, c) covering the at least two conductive portions with a first insulating layer 5/7, 5 / 7a, d) forming holes 17 / 17a in the first insulating layer in such a manner that the at least two conductive portions 6 / 6a are respectively exposed in the holes, e) forming a conductive layer (18/19, 18a / 19) filling the hole and extending over the first insulating layer, f) contacting the conductive layers 18/19, 18a / 19 with at least one of the contact plugs 9, 9a which are held in contact with one of the at least two conductive portions through the associated one of the holes and the rest of the holes. Patterning with a first conductive strip 8 which remains in contact with the other of the two conductive parts and is different in height from the contact plug, g) covering the first insulating layer, the contact plug and the first conductive strip with a second insulating layer 10, h) forming a hole 21 in the second insulating layer in such a way that the contact plug is exposed in the hole, and i) forming a second conductive strip 11 which remains in contact with the contact plug through the hole and extends onto the second insulating layer Method of manufacturing a semiconductor integrated circuit device comprising a. The method of claim 9, wherein the steps c) and f), c-1) A gate electrode 4 formed on each channel region in which at least two conductive portions 6 / 6a are alternately arranged on the surface portion of the semiconductor substrate 1 is formed of a first insulating material, and therebetween. Covering with a protective insulating layer 5 defining a gap, c-2) depositing a second insulating material different from the first insulating material to form first interlayer insulating layers 7 and 7a-the protective insulating layer and the first interlayer insulating layer are combined to form the first insulating material. Forming a layer, f-1) covering a portion of the conductive layers 18/19, 18a / 19 to be formed in the first conductive strip with an etching mask 20, and f-2) etching another portion of the conductive layer not covered with the etching mask until the first interlayer insulating layer is exposed Method of manufacturing a semiconductor integrated circuit device comprising a. The method of claim 10, wherein the first interlayer insulating layer acts as an etching stopper. 12. The method according to claim 11, characterized in that the first interlayer insulating layer (7) generates a chemical which deactivates the etching species in step f-2) to automatically terminate the etching. Semiconductor integrated circuit device manufacturing method. 13. The doped polycrystalline silicon layer according to claim 12, wherein the chemical is hydrogen contained in the first interlayer insulating layer (7), and the conductive layer is selectively etched by dry etching in step f-2). 18) and a refractory metal silicide layer (19). The method of claim 13, wherein the doped polycrystalline silicon and the refractory metal silicide layer are exposed to a plasma generated from a feed gas containing Cl ₂ and HBr. The plasma of claim 13, wherein the first interlayer dielectric layer is formed of hydrogen silsesquioxane, and the doped polycrystalline silicon and the refractory metal silicide layer are plasma generated from a feed gas containing Cl ₂ and HBr. A semiconductor integrated circuit device manufacturing method, characterized in that exposed to. The method of claim 10, wherein the first insulating material and the second insulating material are silicon nitride and silicon oxide, respectively. 10. The method of claim 9, wherein the conductive layer is a combination of a doped amorphous polycrystalline silicon layer (18a) and an amorphous refractory metal silicide layer (19).