JPS61188948A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61188948A
JPS61188948A JP2969285A JP2969285A JPS61188948A JP S61188948 A JPS61188948 A JP S61188948A JP 2969285 A JP2969285 A JP 2969285A JP 2969285 A JP2969285 A JP 2969285A JP S61188948 A JPS61188948 A JP S61188948A
Authority
JP
Japan
Prior art keywords
film
silicon nitride
layer electrode
nitride film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2969285A
Other languages
Japanese (ja)
Inventor
Shigeyuki Sawamukai
沢向 茂幸
Kazuo Sato
和夫 佐藤
Toshio Yonezawa
敏夫 米沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2969285A priority Critical patent/JPS61188948A/en
Publication of JPS61188948A publication Critical patent/JPS61188948A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the reliability and integration by forming a polyimide film on a nitride silicon film formed on a semiconductor substrate, and then providing step of etching back both at substantially equal etching ratio, thereby flattening the surface of an interlayer insulating film. CONSTITUTION:The first layer electrode 4 connected with an impurity region 2 through a contacting hole and the first layer electrode 4 of the prescribed pattern are formed on an insulating film 3, and a plasma nitride silicon film 5 to coat the electrode 4 is formed on the film 3. Then, a polyimide film 6 to coat the film 5 is formed in the prescribed thickness. The film 6 is etched back by reactive ion etching until arriving at the surface region of the film 5 by substantially equal etching ratio. The recess of the film 5 is buried by the film 6 by flattening the surface to obtain a flat surface.

Description

【発明の詳細な説明】 「 χ寥閤n)帖49八弊 〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] “ χ寥閤n)Chapter 49 Eight Evil〕 The present invention relates to a method for manufacturing a semiconductor device.

〔発明の技術的背景〕[Technical background of the invention]

従来、第3図に示すような構造の半導体装置は、次のよ
うにして製造されている。先ず、半導体基板200所定
領域に不純物領域21を”形成し、次いで、この不純物
領域21を含む半導体基板200表面を覆う絶縁膜22
を形成する。
Conventionally, a semiconductor device having a structure as shown in FIG. 3 has been manufactured as follows. First, an impurity region 21 is formed in a predetermined region of the semiconductor substrate 200, and then an insulating film 22 is formed to cover the surface of the semiconductor substrate 200 including this impurity region 21.
form.

次いで、絶縁膜22の所定領域に不純物領域21に通じ
るコンタクトホールを開口する。次に2コンタクトホー
ルを介して不純物領域21に接続する第1層目電極23
と所定パターンの第1層目電極23を絶縁膜22上に形
成する。次いで、各第1層目電極23を覆うチッ化シリ
コン膜24を絶縁膜22上に形成する。次いで、チッ化
シリコン膜24に第1層目電極23に通じるコンタクト
ホールを開口する。次に1コンタクトホールを介して第
1層目電極23に接続する第2層目電極25と所定ノ臂
ターンの第2層目電極25をチッ化シリコン膜24Vc
形成する。
Next, a contact hole communicating with the impurity region 21 is opened in a predetermined region of the insulating film 22. Next, the first layer electrode 23 is connected to the impurity region 21 through two contact holes.
A first layer electrode 23 having a predetermined pattern is formed on the insulating film 22. Next, a silicon nitride film 24 covering each first layer electrode 23 is formed on the insulating film 22. Next, a contact hole communicating with the first layer electrode 23 is opened in the silicon nitride film 24. Next, the second layer electrode 25 connected to the first layer electrode 23 through one contact hole and the second layer electrode 25 of a predetermined arm turn are connected to the silicon nitride film 24Vc.
Form.

妹ス邸、aP舘2層日雷膓25冬葛^ノ譬−1?ノー−
ジョン膜26をチッ化シリコン膜24上に形成して所定
の仕様を満した半導体装置30を得る。
Sister's residence, aP building 2nd floor Nichirai 25 winter kudzu^ no parable-1? No-
A John film 26 is formed on the silicon nitride film 24 to obtain a semiconductor device 30 that satisfies predetermined specifications.

〔背景技術の問題点〕[Problems with background technology]

このような半導体装置の製造方法は、次の欠点を有して
いる。
This method of manufacturing a semiconductor device has the following drawbacks.

■ 第1層目電極23上に形成されるチッ化シリコンM
24のステップ力・々レージが悪くなるため、第2層目
電極25にマウスホールと称せられる凹部が形成された
シ、段切れが発生し易い。このため素子の信頼性が低下
する。
■ Silicon nitride M formed on the first layer electrode 23
Since the stepping force and distance of the second layer electrode 24 deteriorates, a concave portion called a mouse hole is formed in the second layer electrode 25, and breakage is likely to occur. This reduces the reliability of the device.

■ チッ化シリコン膜のステップカバレージが悪いため
第1層目電極23の相互の間隔を狭くできず、第2層目
電極25の相互の間隔は更に広くなる。その素子の集積
度を高めることができない。
(2) Since the step coverage of the silicon nitride film is poor, the mutual spacing between the first layer electrodes 23 cannot be narrowed, and the mutual spacing between the second layer electrodes 25 becomes even wider. The degree of integration of the device cannot be increased.

〔発明の目的〕[Purpose of the invention]

本発明は、眉間絶縁膜の表面を平坦化して信頼性及び集
積度の向上を達成した半導体装置を容易に得ることがで
きる半導体装置の製造方法を提供することをその目的と
するものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily obtain a semiconductor device with improved reliability and degree of integration by flattening the surface of a glabellar insulating film.

〔発明の概要〕[Summary of the invention]

本発明は、眉間絶縁膜となるチツ化シリコン膜を半導体
基板上に形成し、次いで、チツ化シリコン膜上に4リイ
ミド膜を形成した後、両者を略等しいエツチング比でエ
ッチパックする工程を設けたことによシ、眉間絶縁膜の
表面を平坦化して信頼性及び集積度の向上を達成した半
導体装置を容易に得ることができる半導体装置の製造方
法である。
The present invention includes a step of forming a silicon nitride film to serve as an insulating film between the eyebrows on a semiconductor substrate, then forming a 4-limide film on the silicon nitride film, and then etch-packing both at approximately the same etching ratio. Especially, this is a method of manufacturing a semiconductor device that can easily obtain a semiconductor device that has improved reliability and degree of integration by flattening the surface of the glabellar insulating film.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例について図面を参照して説明する
。先ず、第1図囚に示す如く、半導体基板1の所定領域
に不純物領域2を形成し、次いで、この不純物領域2′
fc含む半導体基板1の表面を覆う絶縁膜3を形成する
。次いで、絶縁膜3に不純物領域2上に通じるコンタク
トホールを周知の写真蝕刻法によシ開口する。次いで、
コンタクトホールを介して不純物領域2に接続する第1
層目電極4と所定パターンの第1層目電極4を絶縁膜3
上に形成する。次いで、これらの第1層目電極4を覆う
プラズマチッ化シリコン膜5を絶縁膜3上に形成する。
Embodiments of the present invention will be described below with reference to the drawings. First, as shown in FIG. 1, an impurity region 2 is formed in a predetermined region of a semiconductor substrate 1, and then this impurity region 2'
An insulating film 3 is formed to cover the surface of the semiconductor substrate 1 including fc. Next, a contact hole communicating with the impurity region 2 is opened in the insulating film 3 by a well-known photolithography method. Then,
A first electrode connected to impurity region 2 through a contact hole.
The layer electrode 4 and the first layer electrode 4 of a predetermined pattern are covered with an insulating film 3.
Form on top. Next, a plasma silicon nitride film 5 covering these first layer electrodes 4 is formed on the insulating film 3.

次に、同図(B)に示す如く、プラズマチッ化シリコン
膜5を覆うポリイミド膜6を所定の膜厚で形成する。
Next, as shown in FIG. 2B, a polyimide film 6 covering the plasma silicon nitride film 5 is formed to a predetermined thickness.

次に、同図(C)に示す如く、エツチング比が壷1ぼ同
じになるようKしてプラズマチッ化シリコン膜5の表面
領域にまで達するエッチパック処理をポリイミド膜6に
リアクティブイオンエツチングによシ施す。この表面平
坦化によってプラズマチッ化シリコン膜5の凹部をポリ
イミド膜6で埋めて平坦な表面を得る。
Next, as shown in FIG. 6C, the polyimide film 6 is subjected to an etch pack process that reaches the surface area of the plasma silicon nitride film 5 by reactive ion etching with the etching ratio being approximately the same. Give well. By this surface flattening, the concave portions of the plasma silicon nitride film 5 are filled with the polyimide film 6 to obtain a flat surface.

次に1同図(ロ)に示す如く、プラズマチッ化シリコン
膜5の所定領域に第1層目電極4に通じるコンタクトホ
ールを開口する。次いで、コンタクトホールを介して第
1層目電極4に接続する第2層目電極7をプラズマチッ
化シリコン膜5上に形成する。
Next, as shown in FIG. 1 (b), a contact hole communicating with the first layer electrode 4 is opened in a predetermined region of the plasma silicon nitride film 5. Next, a second layer electrode 7 connected to the first layer electrode 4 via a contact hole is formed on the plasma silicon nitride film 5.

然る後、同図@)に示す如く、第2層目電極2ヲ覆う・
ぐツシペーション膜8をプラズマチッ化シリコン膜5及
びポリイミド膜6の露出表面上に形成して所定の仕様を
満した半導体装置10を得る。
After that, as shown in the same figure @), the second layer electrode 2 is covered.
A compression film 8 is formed on the exposed surfaces of the plasma silicon nitride film 5 and the polyimide film 6 to obtain a semiconductor device 10 that satisfies predetermined specifications.

このようにこの半導体装置の製造方法によれば、プラズ
マチッ化シリコン膜5の凹部をポリイミド膜6で埋めて
エッチパック処理を施すことによシ、表面を平坦にした
眉間絶縁膜を容易に形成することができる。その結果、
第1層目電極4及び第2層目電極7の相互の間隔を十分
狭くして集積度を向上させることができる。また、第2
層目電極70段切れを防止して素子の信頼性を高めるこ
とができる。
As described above, according to this semiconductor device manufacturing method, by filling the recesses of the plasma silicon nitride film 5 with the polyimide film 6 and performing an etch pack process, it is possible to easily form a glabella insulating film with a flat surface. can do. the result,
The degree of integration can be improved by making the mutual interval between the first layer electrode 4 and the second layer electrode 7 sufficiently narrow. Also, the second
It is possible to prevent the layer electrode from breaking at 70 stages, thereby increasing the reliability of the device.

なお、実施例では、第1層目電極4と第2層目電極7を
含んだ2層の眉間絶縁膜を有す半導体装置を得るものに
ついて説明したが、第2図に示す如く、実施例と同様に
して第2層目電極7上K、凹部を4リイミド膜6で埋め
て表面平坦化を図ったプラズマチア化シリコン膜5から
まる眉間絶縁膜を形成し、これにコンタクトホールを開
口して第2層目電極7に接続する第3層目電極11を形
成するようにしても良い。
In the example, a semiconductor device having a two-layer glabella insulating film including a first layer electrode 4 and a second layer electrode 7 was obtained. However, as shown in FIG. In the same manner as above, a round insulating film between the eyebrows is formed on the second layer electrode 7 by filling the concave part with the 4-limide film 6 and flattening the surface by forming a plasma-thioated silicon film 5, and a contact hole is opened in this. A third layer electrode 11 connected to the second layer electrode 7 may be formed.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く、本発明に係る半導体装置の製造方法
によれば、層間絶縁膜の表面を平坦化して信頼性及び集
積度の向上を達成した半導体装置を容易に得ることがで
きるものである。
As described above, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to easily obtain a semiconductor device in which the surface of the interlayer insulating film is planarized and the reliability and degree of integration are improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(A)乃至同図(ト)は、本発明方法を工程順に
示す説明図、第2図は、本発明方法で製造された半導体
装置の他の例を示す断面図、第3図は、従来の方法で製
造された半導体装置の構填を示す断面図である。 1・・・半導体基板、2・・・不純物領域、3・・・絶
縁膜、4・・・第1層目電極、5・・・プラズマチッ化
シリコン膜、6・・・ポリイミド膜、7・・・第2層目
電極、8・・・パッシベーションILIO・・・半導体
装置、11・・・第3層目電極。 出願人代理人  弁理士 鈴 江 武 彦第1 図
1(A) to 1(G) are explanatory diagrams showing the method of the present invention in the order of steps, FIG. 2 is a sectional view showing another example of a semiconductor device manufactured by the method of the present invention, and FIG. 1 is a cross-sectional view showing the structure of a semiconductor device manufactured by a conventional method. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Impurity region, 3... Insulating film, 4... First layer electrode, 5... Plasma silicon nitride film, 6... Polyimide film, 7... ...Second layer electrode, 8...Passivation ILIO...Semiconductor device, 11...Third layer electrode. Applicant's representative Patent attorney Takehiko Suzue Figure 1

Claims (1)

【特許請求の範囲】[Claims]  半導体基板上に絶縁膜を介して所定パターンの下層電
極を形成する工程と、該下層電極を覆うチッ化シリコン
膜を前記絶縁膜上に形成する工程と、該チッ化シリコン
膜上にポリイミド膜を形成する工程と、該ポリイミド膜
に前記チッ化シリコン膜に達するエッチバック処理を該
ポリイミド膜を前記チッ化シリコン膜とのエッチング比
がほぼ等しくなるようにして表面を平坦化する工程と、
前記チッ化シリコン膜に前記下層電極に通じるコンタク
トホールを開口する工程と、該コンタクトホールを介し
て前記下層電極に接続する上層電極を前記チッ化シリコ
ン膜上に形成する工程とを具備することを特徴とする半
導体装置の製造方法。
A step of forming a lower layer electrode in a predetermined pattern on a semiconductor substrate via an insulating film, a step of forming a silicon nitride film on the insulating film to cover the lower layer electrode, and a step of forming a polyimide film on the silicon nitride film. a step of performing an etch-back treatment on the polyimide film to reach the silicon nitride film so that the etching ratio of the polyimide film is approximately equal to that of the silicon nitride film to flatten the surface;
The method further comprises the steps of: opening a contact hole in the silicon nitride film leading to the lower electrode; and forming an upper electrode on the silicon nitride film to connect to the lower electrode through the contact hole. A method for manufacturing a featured semiconductor device.
JP2969285A 1985-02-18 1985-02-18 Manufacture of semiconductor device Pending JPS61188948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2969285A JPS61188948A (en) 1985-02-18 1985-02-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2969285A JPS61188948A (en) 1985-02-18 1985-02-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61188948A true JPS61188948A (en) 1986-08-22

Family

ID=12283156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2969285A Pending JPS61188948A (en) 1985-02-18 1985-02-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61188948A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002037306A (en) * 2000-07-27 2002-02-06 Japan Crown Cork Co Ltd Resin cap for carbonated beverage vessel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002037306A (en) * 2000-07-27 2002-02-06 Japan Crown Cork Co Ltd Resin cap for carbonated beverage vessel

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