JPS5459081A - Surface treatment method for semiconductor element - Google Patents

Surface treatment method for semiconductor element

Info

Publication number
JPS5459081A
JPS5459081A JP12506977A JP12506977A JPS5459081A JP S5459081 A JPS5459081 A JP S5459081A JP 12506977 A JP12506977 A JP 12506977A JP 12506977 A JP12506977 A JP 12506977A JP S5459081 A JPS5459081 A JP S5459081A
Authority
JP
Japan
Prior art keywords
etched
electrode
resist
mesa groove
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12506977A
Other languages
Japanese (ja)
Inventor
Kuniyoshi Oe
Kenji Azetsubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12506977A priority Critical patent/JPS5459081A/en
Publication of JPS5459081A publication Critical patent/JPS5459081A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: To avoid the characteristic fluctuation as well as to reduce the number of manufacturing processes by forming the resist pattern on the main surface of the substrate containing the exposed pn-junction and then providing the mesa groove with exposed pn-junction using the resist pattern as the mask.
CONSTITUTION: N-layer 4 is added to P-epitaxial layer 2 on N-type Si substrate 1, and electrode 1a formed through Ni deposition. Then electrode 3a and 4a are formed to the opening part of SiO2 film 3. The electrodes are then coated with resist 16a and 16b and mesa groove 36 is etched through selective driling of the openings. Then about 20-minute treatment is given with O2 plasma to remove the resist, and then the mesa groove surface is etched about 500Å by preventing the electrode and film 3 from being etched with the mixture gas of Freon and O2 of about 0.3 torr. After this, a coating is applied with Si resin 30 or the like. In this way, a high- quality device featuring reduced leak current can be manufactured in a reduced number of manufacturing processes
COPYRIGHT: (C)1979,JPO&Japio
JP12506977A 1977-10-20 1977-10-20 Surface treatment method for semiconductor element Pending JPS5459081A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12506977A JPS5459081A (en) 1977-10-20 1977-10-20 Surface treatment method for semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12506977A JPS5459081A (en) 1977-10-20 1977-10-20 Surface treatment method for semiconductor element

Publications (1)

Publication Number Publication Date
JPS5459081A true JPS5459081A (en) 1979-05-12

Family

ID=14901042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12506977A Pending JPS5459081A (en) 1977-10-20 1977-10-20 Surface treatment method for semiconductor element

Country Status (1)

Country Link
JP (1) JPS5459081A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4872971A (en) * 1971-12-29 1973-10-02
JPS5186374A (en) * 1975-01-27 1976-07-28 Mitsubishi Electric Corp HANDOTAISOCHINOHYOMENSHORIHOHO

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4872971A (en) * 1971-12-29 1973-10-02
JPS5186374A (en) * 1975-01-27 1976-07-28 Mitsubishi Electric Corp HANDOTAISOCHINOHYOMENSHORIHOHO

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