JPS6437851A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6437851A
JPS6437851A JP19467687A JP19467687A JPS6437851A JP S6437851 A JPS6437851 A JP S6437851A JP 19467687 A JP19467687 A JP 19467687A JP 19467687 A JP19467687 A JP 19467687A JP S6437851 A JPS6437851 A JP S6437851A
Authority
JP
Japan
Prior art keywords
deposited
silicide
resist
dry etching
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19467687A
Other languages
Japanese (ja)
Inventor
Kouji Uraoka
Takeya Ezaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP19467687A priority Critical patent/JPS6437851A/en
Publication of JPS6437851A publication Critical patent/JPS6437851A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To form a stabilized wiring by thinly depositing a chemically stable high melting-point metal or an silicide thereof immediately after Al is deposited and protecting Al from damage such as dry etching when the Al metallic wiring is shaped. CONSTITUTION:A high melting-point silicide 2 such as Tasix is deposited thinly immediately after an n layer (n=1, 2...) Al wiring 1 is deposited in specified thickness. A resist 4 is applied and a pattern is formed through a photoetching process. Dry etching is conducted, using the resist as a mask. When a device is damaged when a metallic pattern is shaped through the dry etching, the resist 4 is removed, and the surface or the whole of the patterned silicide 2 is gotten rid of by hydrofluoric acid. An insulating film is deposited. An inter- layer film 5 is etched in order to bore a through-hole 5a, and the surface of the silicide 2 is etched chemically, thus taking off damage.
JP19467687A 1987-08-04 1987-08-04 Manufacture of semiconductor device Pending JPS6437851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19467687A JPS6437851A (en) 1987-08-04 1987-08-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19467687A JPS6437851A (en) 1987-08-04 1987-08-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6437851A true JPS6437851A (en) 1989-02-08

Family

ID=16328443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19467687A Pending JPS6437851A (en) 1987-08-04 1987-08-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6437851A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653102A (en) * 1992-08-03 1994-02-25 Hitachi Ltd Dielectric isolated substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653102A (en) * 1992-08-03 1994-02-25 Hitachi Ltd Dielectric isolated substrate

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