JPS5687326A - Method of forming wiring - Google Patents

Method of forming wiring

Info

Publication number
JPS5687326A
JPS5687326A JP16391679A JP16391679A JPS5687326A JP S5687326 A JPS5687326 A JP S5687326A JP 16391679 A JP16391679 A JP 16391679A JP 16391679 A JP16391679 A JP 16391679A JP S5687326 A JPS5687326 A JP S5687326A
Authority
JP
Japan
Prior art keywords
layer
resist layer
resist
pattern
laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16391679A
Other languages
Japanese (ja)
Inventor
Koji Otsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP16391679A priority Critical patent/JPS5687326A/en
Publication of JPS5687326A publication Critical patent/JPS5687326A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To easily, safely and securely form wirings in narrow width by a method wherein an Mo layer and resist layer are laminated on a substrate in a prescribed pattern, and the Mo layer and the resist layer are removed after a conductor layer is attahced to the laminated layer over the whole surface. CONSTITUTION:After the Mo layer 5 and resist layer 6 in a prescribed pattern are formed on the Si substrate 1 through an SiO2 film 2, the conductor layer such as Al is evaporated on the whole surface and applied with a fuming nitric acid to completely dissolve the Mo layer 5 and resist layer 6 instantaneously, thereby permitting only Al on the resist layer to be lifted off to form the Al wiring layer in the predetermined pattern. Whereby the wirings in a fine pattern with narrow width are formed with ease and in certainty without producing a problem of a side-etching because Al is not directly etched.
JP16391679A 1979-12-17 1979-12-17 Method of forming wiring Pending JPS5687326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16391679A JPS5687326A (en) 1979-12-17 1979-12-17 Method of forming wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16391679A JPS5687326A (en) 1979-12-17 1979-12-17 Method of forming wiring

Publications (1)

Publication Number Publication Date
JPS5687326A true JPS5687326A (en) 1981-07-15

Family

ID=15783252

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16391679A Pending JPS5687326A (en) 1979-12-17 1979-12-17 Method of forming wiring

Country Status (1)

Country Link
JP (1) JPS5687326A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827324A (en) * 1981-08-10 1983-02-18 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPS59136933A (en) * 1983-01-13 1984-08-06 コミツサリア・タ・レネルギ−・アトミ−ク Method of producing integrated circuit conductor using planar technique
US7345370B2 (en) 2005-01-12 2008-03-18 International Business Machines Corporation Wiring patterns formed by selective metal plating

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4845868A (en) * 1971-10-15 1973-06-30
JPS4999274A (en) * 1973-01-25 1974-09-19
JPS5045571A (en) * 1973-08-25 1975-04-23

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4845868A (en) * 1971-10-15 1973-06-30
JPS4999274A (en) * 1973-01-25 1974-09-19
JPS5045571A (en) * 1973-08-25 1975-04-23

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827324A (en) * 1981-08-10 1983-02-18 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPH0151053B2 (en) * 1981-08-10 1989-11-01 Nippon Telegraph & Telephone
JPS59136933A (en) * 1983-01-13 1984-08-06 コミツサリア・タ・レネルギ−・アトミ−ク Method of producing integrated circuit conductor using planar technique
JPH051614B2 (en) * 1983-01-13 1993-01-08 Komitsusaria Ta Renerujii Atomiiku
US7345370B2 (en) 2005-01-12 2008-03-18 International Business Machines Corporation Wiring patterns formed by selective metal plating
US7521808B2 (en) 2005-01-12 2009-04-21 International Business Machines Corporation Wiring paterns formed by selective metal plating

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