JPS6473718A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS6473718A JPS6473718A JP62229525A JP22952587A JPS6473718A JP S6473718 A JPS6473718 A JP S6473718A JP 62229525 A JP62229525 A JP 62229525A JP 22952587 A JP22952587 A JP 22952587A JP S6473718 A JPS6473718 A JP S6473718A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- substrate
- alignment
- manufacture
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Integrated Circuits (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
PURPOSE:To prevent any defective resolution of resist due to a step on the surface of a substrate from occurring by a method wherein the step for alignment in the photolithographic process performed after epitaxial formation is formed only on an alignment part (a) on the substrate. CONSTITUTION:An insulating film 2 is formed on the surface of a semiconductor substrate 1 by thermal oxidation; another insulating film 3 is formed on the film 2 by CVD process; and the other insulating film 4 capable of selectively etching the insulating film 3 is formed. Resist patterns 5 in specific shapes corresponding to the shapes of buried layers 7 are formed on the insulating film 4. Then, openings 4a, 4b are made using said patterns 5 as masks to form a resist pattern 6 for the opening 4a. The other opening 3a is made using the pattern 6 and the insulating film 4 as masks. Finally, after forming the layers 7, the insulating films 4, 3, 2 are etched away to form a step 8 for alignment on the surface of the exposed substrate 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62229525A JPS6473718A (en) | 1987-09-16 | 1987-09-16 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62229525A JPS6473718A (en) | 1987-09-16 | 1987-09-16 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6473718A true JPS6473718A (en) | 1989-03-20 |
Family
ID=16893535
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62229525A Pending JPS6473718A (en) | 1987-09-16 | 1987-09-16 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6473718A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002368147A (en) * | 2001-04-04 | 2002-12-20 | Internatl Business Mach Corp <Ibm> | Manufacturing method for semiconductor device having deep sub-collector region |
| JP2019066766A (en) * | 2017-10-04 | 2019-04-25 | パナソニックＩｐマネジメント株式会社 | Semiconductor device and manufacturing method therefor |
-
1987
- 1987-09-16 JP JP62229525A patent/JPS6473718A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002368147A (en) * | 2001-04-04 | 2002-12-20 | Internatl Business Mach Corp <Ibm> | Manufacturing method for semiconductor device having deep sub-collector region |
| JP2019066766A (en) * | 2017-10-04 | 2019-04-25 | パナソニックＩｐマネジメント株式会社 | Semiconductor device and manufacturing method therefor |
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