JPS56115537A - Forming method of infinitesimal pattern - Google Patents

Forming method of infinitesimal pattern

Info

Publication number
JPS56115537A
JPS56115537A JP1790680A JP1790680A JPS56115537A JP S56115537 A JPS56115537 A JP S56115537A JP 1790680 A JP1790680 A JP 1790680A JP 1790680 A JP1790680 A JP 1790680A JP S56115537 A JPS56115537 A JP S56115537A
Authority
JP
Japan
Prior art keywords
plasma
pattern
infinitesimal
film
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1790680A
Other languages
Japanese (ja)
Inventor
Ken Ogura
Yoshio Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP1790680A priority Critical patent/JPS56115537A/en
Publication of JPS56115537A publication Critical patent/JPS56115537A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31127Etching organic layers
    • H01L21/31133Etching organic layers by chemical means
    • H01L21/31138Etching organic layers by chemical means by dry-etching

Abstract

PURPOSE:To enable the dry patterning of a resist film by coating the resist film on the surface of a semiconductor substrate, irradiating a plasma or ion beam in accordance with a predetermined pattern on the surface of the film, and allowing it to stand in O2 plasma. CONSTITUTION:The resist pattern 13 is formed on the semiconductor substrate 11 having a thermal silicon oxide film 12. The plasma 14 formed of CF4 gas is irradiated on the surface of the resist film 13 in accordance with the desired pattern. Then, the substrate 11 is allowed to stand in the O2 plasma in an etching tunnel 16, the part in which the plasma is not irradiated is etched and removes as a resist pattern 13'. Thus, it can prevent the irregularity in the patterning characteristics and conduct the infinitesimal dry patterning.
JP1790680A 1980-02-18 1980-02-18 Forming method of infinitesimal pattern Pending JPS56115537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1790680A JPS56115537A (en) 1980-02-18 1980-02-18 Forming method of infinitesimal pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1790680A JPS56115537A (en) 1980-02-18 1980-02-18 Forming method of infinitesimal pattern

Publications (1)

Publication Number Publication Date
JPS56115537A true JPS56115537A (en) 1981-09-10

Family

ID=11956779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1790680A Pending JPS56115537A (en) 1980-02-18 1980-02-18 Forming method of infinitesimal pattern

Country Status (1)

Country Link
JP (1) JPS56115537A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074845A2 (en) * 1981-09-14 1983-03-23 Fujitsu Limited Etching polyimide resin layers and method of manufacturing a semiconductor device having a layer of polyimide resin

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074845A2 (en) * 1981-09-14 1983-03-23 Fujitsu Limited Etching polyimide resin layers and method of manufacturing a semiconductor device having a layer of polyimide resin

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