JPS61248437A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61248437A JPS61248437A JP8930585A JP8930585A JPS61248437A JP S61248437 A JPS61248437 A JP S61248437A JP 8930585 A JP8930585 A JP 8930585A JP 8930585 A JP8930585 A JP 8930585A JP S61248437 A JPS61248437 A JP S61248437A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- etched
- substrate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置のS遣方法に関し、特に表面の平
坦な素子分離膜の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a semiconductor device, and more particularly to a method for forming an element isolation film with a flat surface.
半導体装置の高集積化に伴ない配線の段切れ防止や多層
配線構造の実現のため、素子領域とフィールド領域の凹
凸をなくす表面平滑化が大きな問題となりている。従来
から行なわれている平滑化方法は、素子形底予定領域全
窒化展でカバーしフィールド領域を熱酸化し、更にこの
酸化膜金去金し之のち再度熱酸化する方法。また再酸化
する前に窒化膜成長金し、窒化膜全素子形成予定領域の
@壁に残して酸化する方法がとられ、フィールド反転防
止のため再酸化する前にホウ素拡散金行なう方法が行わ
れていた。As semiconductor devices become more highly integrated, surface smoothing to eliminate unevenness in element regions and field regions has become a major issue in order to prevent wiring breaks and realize multilayer wiring structures. The conventional smoothing method is to cover the entire area intended for the bottom of the element shape with nitridation, thermally oxidize the field area, remove gold from this oxide film, and then thermally oxidize again. In addition, a method is used in which a nitride film is grown before reoxidation, and the nitride film is left on the walls of all the regions where elements are to be formed, and then oxidized, and a method is used in which boron is diffused before reoxidation to prevent field reversal. was.
しかしながらこのよつな平滑化方法においてなく1)工
程数が多い、(2)熱酸化法のtめバーズビークが生じ
、素子の寸法精度が劣化する、(3)熱酸化(通常10
00℃〜1200℃)法の定め半導体基板に結晶欠陥が
生じ、素子特性のリーク不良に継がる、(4]フイ一ル
ド反転防止層のホウ素拡散層が次工程の熱酸化に19深
さ及び横広がりが制御しにくい、というよりな欠点がめ
る。However, unlike this type of smoothing method, 1) the number of steps is large, (2) a bird's beak occurs in the thermal oxidation method and the dimensional accuracy of the element deteriorates, and (3) thermal oxidation (usually 10
(4) The boron diffusion layer of the field inversion prevention layer is heated to a depth of 19 degrees and The main drawback is that the lateral spread is difficult to control.
本発明の目的は、上記欠点を除去し、非常に簡便に、素
子領域とフィールド領域との表面平滑化を実現し、特性
劣化ヶもたらすことなく、半導体素子の高集積化上可能
とした半導体装置の製造方法を提供することにるる。It is an object of the present invention to eliminate the above-mentioned drawbacks, to realize a very simple surface smoothing between the element region and the field region, and to achieve a semiconductor device that enables high integration of semiconductor devices without causing characteristic deterioration. The purpose is to provide a manufacturing method for.
本発明の半導体装置の製造方法は、半導体基板上に酸化
膜全形取する工程と、素子形成領域以外の前記酸化WX
?!−除去する工程と、素子形成領域以外の前記半導体
基板表面を所定の深さ迄エツチングする工程と、全面に
不純物拡散源液業塗布したのち絶縁膜形取用液紮塗布し
焼成して絶縁膜を形成する工程と、Iii′i前記酸化
膜と前記絶縁膜とをエツチングし素子形底佃域における
半導体基板表面全露出きせる工程と金含んで構成される
。The method for manufacturing a semiconductor device of the present invention includes the steps of forming an entire oxide film on a semiconductor substrate,
? ! - a step of etching the surface of the semiconductor substrate other than the element forming area to a predetermined depth; and a step of applying an impurity diffusion source liquid to the entire surface, and then applying an insulating film shaping liquid and baking it to form an insulating film. A step of etching the oxide film and the insulating film to expose the entire surface of the semiconductor substrate in the bottom region of the element shape.
次に1本発明の実施例について図面を参照して説明する
。Next, an embodiment of the present invention will be described with reference to the drawings.
第1図(a)〜(e)は本発明の一実施例全説明するた
めの工程断面図であり9M08型半導体装置に適用した
場合を示している。FIGS. 1(a) to 1(e) are process cross-sectional views for fully explaining one embodiment of the present invention, and show a case where the present invention is applied to a 9M08 type semiconductor device.
まず、第1図(a)に示すように、P型シリコン基板1
の表面に、熱酸化により数百Aの酸化膜+8i0z)2
e形底する。この酸化膜2は、次工程において、フィー
ルド反転防止に用いる不純物拡散源液のマスクとして用
いる。酸化a2全形放しt後、ホトレジスト塗布を行な
い素子形成予定領域のみにホトレジスト膜4を残す。次
に第1図(b)に示すように、ホトレジストMlマスク
にして、リアクティブイオンエツチング法にて、フィー
ルド領域の酸化a2及びシリコン基板1を所定の深さま
でエツチングする。次に第1図(C)に示すよりにホト
レジスト膜4t″除去し友後、フィールド反転防止とし
てホウ素を含む不純物拡散源液を薄く表面に塗布し不純
物拡散mar形成する。次に第1因(メに示すように絶
縁膜形成用液(不純物紮含まないシリコン化合物のアル
コール溶液)全1シリコン基板1表面全体tおおりエラ
に厚く塗布し200〜300℃で焼成する。必要に応じ
てこの操作音くり返し表面の平滑な絶縁膜5會形成する
。次に第1図(e)に示すように弗酸系のウェットエッ
チ法等により、素子形成予定領域の表面が露出するまで
絶縁膜5及び酸化膜2をエツチングする。First, as shown in FIG. 1(a), a P-type silicon substrate 1
An oxide film of several hundred amperes is formed on the surface by thermal oxidation.
It has an e-shaped bottom. This oxide film 2 is used as a mask for an impurity diffusion source solution used to prevent field inversion in the next step. After the oxidized A2 is completely released, photoresist is applied to leave the photoresist film 4 only in the area where the element is to be formed. Next, as shown in FIG. 1(b), using a photoresist Ml mask, the oxide a2 in the field region and the silicon substrate 1 are etched to a predetermined depth by reactive ion etching. Next, as shown in FIG. 1(C), after removing the photoresist film 4t'', a thin layer of an impurity diffusion source solution containing boron is applied to the surface to prevent field reversal to form an impurity diffusion mark.Next, the first factor ( As shown in the figure, apply the insulating film forming liquid (alcoholic solution of silicon compound containing no impurities) thickly to the entire surface of the silicon substrate and bake at 200 to 300°C.This operation may be performed as necessary. Five insulating films with a smooth surface are formed.Next, as shown in FIG. Membrane 2 is etched.
このよりにして、素子分離用絶縁wj#、5t−形成し
t後、素子形成予定領域全酸化、ホトエツチング、拡散
、蒸着、等の工程を経て、素子を形成する。After forming the element isolation insulator wj#, 5t, the element is formed through processes such as total oxidation, photoetching, diffusion, and vapor deposition in the area where the element is to be formed.
このように本発明の実施例によれば、従来に比べて非常
に簡便な工程により半導体表面の平滑化がはかられ、素
子領域の寸法が最初のホトレジストマスク寸法にて決定
されるため、設計値に近い特性値が得られる。また、高
温酸化勿必要としないtめ半導体基板内部における結晶
欠陥の発生が少なく欠陥に起因するリーク不良も低減さ
せることが可能となる。As described above, according to the embodiments of the present invention, the semiconductor surface can be smoothed through a much simpler process than in the past, and the dimensions of the element area are determined by the dimensions of the initial photoresist mask, making it easier to design. Characteristic values close to the values can be obtained. Further, crystal defects are less likely to occur inside the semiconductor substrate, which does not require high-temperature oxidation, and leakage defects caused by defects can be reduced.
以上詳細に説明し几ように9本発明によれば。 As described above in detail, nine aspects of the invention are in accordance with the present invention.
フィールド領域をエツチングし、この部分に塗布法によ
り絶縁膜を形成することにLり、フィールド領域と累子
形成佃域と?平滑化し、信頼性が高く、集積度の向上し
t半導体装置の製造方法が得られるのでその効果は大き
い。The field area is etched and an insulating film is formed on this part by a coating method. The effect is great because it provides a method for manufacturing a semiconductor device that is smooth, highly reliable, and has an improved degree of integration.
第1図は(al〜(e)は本発明の一冥施flik説明
する定めの工程断面図である。
1・・・PMシリコン基板、2・・・酸化膜、3・・・
不純物拡散源膜、4・・・ホトレジスト膜、5・・・絶
縁膜。1A to 1E are cross-sectional views of certain steps to explain the implementation of the present invention. 1... PM silicon substrate, 2... Oxide film, 3...
Impurity diffusion source film, 4... photoresist film, 5... insulating film.
Claims (1)
域以外の前記酸化膜を除去する工程と、素子形成領域以
外の前記半導体基板表面を所定の深さ迄エッチングする
工程と、全面に不純物拡散源液を塗布したのち絶縁膜形
成用液を塗布し焼成して絶縁膜を形成する工程と、前記
酸化膜と前記絶縁膜とをエッチングし素子形成領域にお
ける半導体基板表面を露出させる工程とを含むことを特
徴とする半導体装置の製造方法。A step of forming an oxide film on a semiconductor substrate, a step of removing the oxide film in areas other than the element formation region, a step of etching the surface of the semiconductor substrate other than the element formation region to a predetermined depth, and a step of diffusing impurities over the entire surface. The method includes a step of applying a source solution and then applying an insulating film forming liquid and baking it to form an insulating film, and a step of etching the oxide film and the insulating film to expose the surface of the semiconductor substrate in the element formation region. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8930585A JPS61248437A (en) | 1985-04-25 | 1985-04-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8930585A JPS61248437A (en) | 1985-04-25 | 1985-04-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61248437A true JPS61248437A (en) | 1986-11-05 |
Family
ID=13966950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8930585A Pending JPS61248437A (en) | 1985-04-25 | 1985-04-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61248437A (en) |
-
1985
- 1985-04-25 JP JP8930585A patent/JPS61248437A/en active Pending
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