JPS63308932A - Interelement isolating method for semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the contraction of element forming region, and increase the interelement density, by forming a masking member having side-wall parts, etching the interelement isolating region of a semiconductor substrate by using the masking member, and forming a groove part having inclination, on the semiconductor substrate. CONSTITUTION:A silicon oxide film 3 is formed on the surface 2 of a silicon substrate 1, and a photoresist layer 4 of a desired pattern is formed. By using the photoresist layer 4 as a mask, an anisotropic etching is performed. After the photoresist layer 4 is dissolved and eliminated, silicon oxide 5 is formed, and then silicon oxide side-wall parts 5 are formed by a reactive ion etching. By using a photoresist 3 having the sidewall parts 5' as a mask, the silicon substrate 1 is subjected to a reactive ion etching, and a groove part having inclination is formed on an interelement isolating region 6. As the element forming region is not contracted, thereby, the interelement density can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in an element isolation method for insulating each active element in, for example, an MO8 type semiconductor device.

<Prior Art> For example, in a semiconductor device using silicon as a semiconductor, especially an MO5 type semiconductor device, as an element isolation method for isolating each active element, the method shown in FIGS.
The method shown in i) is used.

That is, first, a silicon oxide layer 23 is formed on the surface 22 of the Noricon substrate 21 shown in FIG. A silicon nitride layer 24 is formed to obtain the structure shown in FIG. 2(b). Next, a photoresist layer 25 having a desired pattern is formed on the silicon nitride layer 24 by photolithography to obtain the structure shown in FIG. 2(c). Next, using this photoresist layer 25 as a mask, the silicon nitride layer 24 is etched by reactive ion etching (CRIE method), as shown in FIG. 2(d).
The structure is as shown in . Next, as shown in FIG. 2(e), in order to prevent field reversal, impurities of the same conductivity type as the silicon substrate 21, such as boron ions B+ in the case of a p-type substrate, are ion-implanted into the element isolation region. Layer 26 is formed. Thereafter, the photoresist layer 25 is dissolved to obtain the structure shown in FIG. 2(f). Next, the obtained substrate is thermally oxidized at high temperature for a long time to form a thick oxide film 2.
7 to obtain the structure shown in FIG. 2(g). In this case, the oxide film 27 is formed below the silicon nitride layer 24. Next, the silicon nitride layer 24 is removed by RIE to obtain the structure shown in FIG. 2(b). Next, a part of the thick oxide film 27 and the thin oxide film 23 are removed by immersion in a hydrofluoric acid buffer solution to form the structure shown in FIG. It is formed. Next, desired elements are formed on the element formation region 28 thus obtained to manufacture a semiconductor device.

<Problems to be Solved by the Invention> However, in the above-mentioned conventional method, as shown in FIGS. Since the area is also narrow, it is not possible to increase the density of the elements. Further, as shown in FIG. 2(i), a large step is formed on the substrate 21, which tends to cause disconnection of the wiring arranged on the element forming region 28 and to reduce the processing accuracy of the pattern by photolithography. Furthermore, the impurities ion-implanted to prevent field reversal are diffused into the element formation region 28 by the subsequent high-temperature thermal oxidation treatment, and as a result, it becomes impossible to control the threshold voltage of the active element. There are drawbacks such as malfunction of the device.

The present invention was made in order to improve the above-mentioned problems, and it is an object of the present invention to provide a method for isolating elements of a high-density semiconductor device having excellent insulation properties and a flat structure.

<Means for Solving the Problems> In order to achieve the above object, the method for isolating elements in a semiconductor device of the present invention includes:
a step of forming a mask material having a side wall portion; a step of etching the element isolation region of the semiconductor substrate using the mask material to form a groove portion having an inclination in the semiconductor substrate; A step of selectively removing only the side wall portion of the material to expose the peripheral portion of the surface of the element formation region on the semiconductor surface surrounded by the groove portion, and then using a mask material from which the side wall portion has been removed. A process of ion-implanting impurities of the same conductivity type as the semiconductor substrate into the element isolation region and the peripheral part of the surface of the element formation area of the semiconductor substrate, and then etching the mask material from which the side walls have been removed, and then element isolation. The method includes a step of continuously forming a plurality of insulating films only in the region, flattening the element isolation region and the element forming region, and then forming a desired element in the element forming region. Examples of semiconductor substrates to which the present invention can be applied even though they are configured include semiconductor substrates made of silicon, gallium arsenide, gallium aluminum arsenide, and the like.

<Examples> Next, the present invention will be explained by examples with reference to the drawings, but the present invention is not limited to the following.

FIGS. 1(a) to 1(1) each show each step of an embodiment of the present invention.

First, the p-type (10
0) A silicon oxide film 3 with a thickness of 0.5μ is formed on the surface 2 of the silicon substrate 1 by a thermal oxidation method as shown in FIG. 1(b),
Next, a photoresist layer 4 having a desired pattern as shown in FIG. 1(c) is formed by ordinary photolithography.

Next, using the photoresist layer 4 as a mask, anisotropic etching and soching are performed by reactive ion etching to obtain the structure shown in FIG. 4(d).

Next, the photoresist layer 4 is dissolved and removed as shown in FIG.
We obtain the structure shown in .

Next, as shown in (4) of the same figure, ECR (Electro
Silicon dioxide 5 is formed to a thickness of 0.2 μm by plasma CVD (Cyclotron Re5onance), and then subjected to reactive ion etching (RIE) to form silicon oxide side walls 5' (for example, 0.2 μm wide). The structure shown in FIG. 4(g) is obtained.

Next, using the photoresist 3 having the side wall portion 5' as a mask, the silicon substrate 1 is etched to a depth of 0.6 μm and about 0.1 μm from the outer edge of the mask toward the edge of the oxide film by reactive ion etching. Then, a groove portion having an inclination is formed in the element isolation region 6 as shown in FIG. 6(h).

Next, a wet etching process is performed to selectively remove a portion of the mask to the extent that the periphery of the oxide film 3 is exposed.
The peripheral part 7 of the surface of the element formation region of the silicon substrate 1 is exposed to obtain the structure shown in FIG.
For example, boron ion 16, which is an impurity of the same conductivity type, is
The impurity layer 8, which is an ion-implanted layer, is formed at the bottom and slope of the groove-shaped element isolation region 6, as shown in FIG. 1(j). The reason why the ion implantation is performed while exposing the peripheral part of the element formation region is to prevent parasitic channels in the peripheral part.

Next, the mask layer 3 is immersed in a hydrofluoric acid buffer solution.
is removed to obtain the structure shown in FIG.

Next, bias sputtering conditions are set so that the deposition rate and etching rate on the surface of the element forming region are balanced and the deposition rate at the bottom of the element isolation region 6 is higher than the etching rate.

As shown in FIG. 1 (1), a silicon oxide film 9 and a silicon oxynitride film 1o are deposited by bias sputtering, for example, with a total of 0.
The semiconductor substrate is continuously deposited to a thickness of 7 μm only on the element isolation region 6 to obtain a semiconductor substrate having an element forming surface 12 separated by an element isolation part 11.

Next, a desired element is formed on this element forming surface 11 through normal steps, thereby completing the semiconductor device.

According to the above method, the element formation area does not become narrow.
It becomes possible to increase the density of elements. Furthermore, by using the sidewalls of the silicon oxide film, it is possible to simultaneously implant ions into the periphery of the surface of the element formation region and the element isolation region, preventing inversion of the groove in the element isolation region and preventing parasitic channels on the sidewalls of the groove. It is possible to do so. Furthermore, a flat structure can be realized by bias sputtering and this flat structure can be maintained until the final process, making it possible to prevent wiring breakage and to perform high-precision processing by photolithography.

Furthermore, since a long-time thermal oxidation process at high temperature is not required to form the element isolation region, the process can be simplified, impurity diffusion to prevent field reversal can be prevented, and the threshold voltage of active elements can be reduced. It has many advantages such as controllability and the ability to realize a good semiconductor device. Furthermore, it goes without saying that the present invention can be applied not only to N-channel MO5) transistors but also to various semiconductor devices.

<Effect of the invention> As described above, the method of the present invention has the following advantages.

(1) Since the element forming area does not become narrow as in the conventional case, the density of elements can be increased.

(11) By using the sidewalls of the silicon oxide film, it is possible to simultaneously implant ions into the peripheral part of the surface of the element formation region and the element isolation region, and as a result, the inversion of the trench in the element isolation region is prevented and the parasitic growth of the trench sidewall is prevented. Channel prevention can be done.

(...) A flat structure can be achieved and maintained until the final process, making it possible to prevent wire breakage and perform high-precision processing using photolithography.

(iv) Since a long thermal oxidation process at high temperature is not required to form the element isolation region, the process can be simplified, and the diffusion of impurities to prevent field reversal can be prevented and the threshold voltage of active elements can be lowered. Control becomes possible, and a device can be manufactured with a good semiconductor layer.

[Brief explanation of drawings]

FIGS. 1(a) to (1) are process explanatory diagrams showing one embodiment of the present invention, and FIGS. 2(a) to (i) are process explanatory diagrams showing a conventional method, respectively. 1... Silicon substrate, 2... Silicon substrate surface, 3
...Oxide film, 4. Photoresist layer, 5.. Oxide film, 6.. Element isolation region, 5.. Side wall portion, 8.. Impurity layer (ion implantation layer), 9.. Oxide film, 10...
Oxynitride silicone film, 11... element isolation section, 12...
Element formation area. Agent Patent attorney Takeshi Sugiyama (and 1 other person) Figure 1 Figure 71 Figure 1

Claims (1)

[Claims] 1. A step of forming a mask material having a side wall portion on an element formation region of a semiconductor substrate, and etching an element isolation region of the semiconductor substrate using the mask material to form a slope in the semiconductor substrate. a step of selectively removing only the sidewall portions of the mask material to expose a peripheral portion of the surface of the element formation region on the semiconductor surface surrounded by the groove portion; using the removed mask material to ion-implant impurities of the same conductivity type as the semiconductor substrate into the periphery of the surface of the element isolation region and element formation region of the semiconductor substrate, and then etching the mask material from which the side wall portions were removed. After that, a step of continuously forming a plurality of insulating films only in the device isolation region to flatten the device isolation region and the device formation region, and then a step of forming a desired device in the device formation region. A method for isolating elements in a semiconductor device, characterized by comprising: