JPH06275710A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a method for manufacturing a semiconductor device in which a selective oxide film having a sufficient thickness can be formed on an element isolation region without increasing many steps even when narrow and wide element isolation regions exist in mixture. CONSTITUTION:After a silicon nitride film 33 and a pad oxide film 32 are deposited on a semiconductor substrate 31, only a part corresponding to an element isolating region of the film 33 is etched to form an opening, a surface of the substrate 31 of the opening is etched to form trenches 34, 34' having sidewalls inclined to a normal plane of the substrate. With a mask pattern of the film 33 remaining on an element region 39 as an oxidation resistant mask selective oxide films 36, 36' are formed by selective oxidation, the films 33, 32 are eventually removed to conduct complete isolation and formation of an element region 38 and an element isolation region 39.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure and manufacturing method of a semiconductor device, and more particularly to an element isolation technique on a semiconductor substrate having an improved degree of integration.

[0002]

2. Description of the Related Art Semiconductor elements and integrated circuit elements are being miniaturized in order to improve the element characteristics and increase the degree of integration, and element isolation technology is essential for their manufacture. This technique is a technique for electrically insulating / isolating each device (active element as each constituent element of a circuit) on a chip, and one of the important requirements thereof.
First, it is required to reduce the area required for isolation as much as possible and effectively provide the chip area for active devices.

A selective oxidation method (LOCOS method = Local Oxidation of Silicon), which is the mainstream of conventional element isolation methods, is disclosed in, for example, Japanese Patent Laid-Open No. 63-253640. In this method, the element isolation region is formed on the semiconductor substrate as shown in FIG. For example, FIG.
As shown in FIG. 1, a silicon oxide film 12 is formed on a p-type semiconductor substrate 11, a silicon nitride film 13 is further formed on the silicon oxide film 12, and the silicon nitride film 13 is selectively etched by a well-known photolithography method. The film 13 serves as a mask during selective oxidation. That is, the silicon nitride film 1
3 is provided with an opening 14 and ions 15 for preventing field edge inversion are implanted, and then selective oxidation is performed. Then, this silicon nitride film 13 is used as an oxidation resistant mask to form a selective oxide film 16
(FIG. 7B) is formed, and this becomes an insulating film called a field oxide film that separates the element regions 17 that are adjacent to each other later. After that, the silicon nitride film 13 which is an oxidation resistant mask is peeled off to obtain the state shown in FIG. 1B, and then elements such as transistors are formed in the element region 17 by a known method.

A so-called trench isolation method has also been devised, for example, as disclosed in Japanese Patent Laid-Open No. 60-189237. A general trench isolation method is shown in FIG.

As shown in FIG. 4A, a relatively thick oxide film 21 is grown on a p-type silicon substrate 26 by a thermal oxidation method or a CVD method, and then a predetermined portion 28 of the oxide film 21 is grown.
Is opened by a well-known photolithography method, and then the silicon substrate 26 is formed using the oxide film 21 as an etching mask.
A trench (groove) 22 is formed in the trench 22. Further, using the oxide film 21 as a mask, a channel stopper ion 23 is implanted into the bottom of the trench 22, and then the oxide film 21 is removed.

After the oxide film 21 on the silicon substrate 26 is removed, a thin thermal oxide film 24 is formed on the inner wall of the trench 22 and the surface of the silicon substrate 26, as shown in FIG. Then, as shown in FIG. 3C, a BPSG (boron-phosphorus-glass) film 25 is deposited by a CVD method to completely fill the inside of the trench 22 and further annealed in a nitrogen atmosphere to form a BPSG on the trench 22. The film 25 is reflowed and planarized.

Further, as shown in FIG. 3D, when the BPSG film 25 on the silicon substrate is etched back, the surface of the silicon substrate 26 is exposed at the portion which will later become the element region 7, and the trench 22 which becomes the element isolation region. Is BPS
The G film 25 remains. This BPSG film 25 is a field oxide film and separates each element. After that, elements such as transistors are formed by a known method.

[0008]

However, of the two element isolation methods described above, the selective oxidation method of FIG.
A so-called bird's beak, in which the selective oxide film 16 penetrates into the bird's beak shape, is generated at 7, and the effective area of the element region 17 is greatly reduced. In addition, as the degree of integration increases, the opening 1 of the silicon nitride film 13, which is an oxidation resistant mask, is formed.
When the width of 4 is 0.8 μm or less, the oxidizing agent is not sufficiently supplied through this opening at the time of selective oxidation, so that the film thickness of the selective oxide film 16 (that is, the field oxide film) formed is equal to that of the opening portion. The phenomenon occurs that the thickness becomes thinner than that when the width is wide. The thinning of the field oxide film lowers the threshold voltage of the parasitic MOS transistor formed in the element isolation region, which deteriorates the element isolation characteristic. Therefore, unless a sufficient element isolation width is taken, the required isolation characteristics cannot be obtained, so that it cannot be used in the process of manufacturing a highly integrated semiconductor element.

On the other hand, although it is possible to form a highly integrated semiconductor device by the trench method of FIG. 4, the two steps of burying BPSG after trench etching and reflowing are different from those of the conventional selective oxidation method. Compared to it, it is necessary. Therefore, there is a problem that the manufacturing cost increases.

When a narrow element isolation region and a wide element isolation region are mixed, it is impossible to simultaneously form a field oxide film in these regions only by depositing / etching back the BPSG film once. Must be provided. This is for the following reason. That is, in the trench of the narrow element isolation region, the deposition of the BPSG film also occurs on the side wall of the trench. Therefore, at the end of the deposition, the field oxide film thickness inside the trench is B deposited on other portions.
It is considerably thicker than the PSG film thickness. Therefore, it is possible to leave the field oxide film inside the trench groove even after the etch back. However, the field oxide film thickness in the trench of the wide element isolation region does not become equal to or larger than the BPSG film thickness deposited in the other regions, and if the etching back is performed as it is, the field oxide film thickness becomes significantly thin. In this case, the threshold voltage of the parasitic MOS transistor is also greatly reduced, and sufficient element isolation characteristics cannot be obtained.

As described above, when the narrow element isolation region and the wide element isolation region coexist, a process for leaving the BPSG film in the wide element isolation region portion must be separately provided, which increases the manufacturing cost. There was a problem of inviting.

The present invention has been made to solve the above problems, and even when a narrow element isolation region and a wide element isolation region are mixed, the element isolation region is not particularly increased in number of steps. An object of the present invention is to obtain a semiconductor manufacturing method capable of forming a selective oxide film having a sufficient thickness.

[0013]

A method of manufacturing a semiconductor device according to a first aspect of the present invention corresponds to a step of depositing an oxidation resistant film on a semiconductor substrate and an element isolation region of the oxidation resistant film. A step of forming a mask pattern made of an oxidation resistant film remaining in a portion corresponding to the element region by etching only the portion to provide an opening, and performing selective oxidation using the mask pattern as an oxidation resistant mask In the method of manufacturing a semiconductor device, the method further comprising the step of forming a selective oxide film, wherein the selective oxide film is used as an element isolation insulating film of a semiconductor device, after the step of forming a mask pattern, the element isolation region is further formed. The step of forming a trench having a side wall inclined with respect to the normal surface of the semiconductor substrate is provided on the surface of the semiconductor substrate.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein an angle between a sidewall of the trench and a slope of the semiconductor substrate is in a range of 15 ° to 45 °. It is what

[0015]

According to the first aspect of the present invention, when the element isolation region is extremely narrow by forming the trench having the side wall inclined with respect to the normal surface of the substrate in the semiconductor substrate in the element isolation region portion. Even in this case, it becomes possible to form a thicker selective oxide film than that obtained by the conventional selective oxidation method. This also improves the element isolation characteristics.

According to the second aspect of the present invention, the angle between the sidewall of the trench and the slope of the semiconductor substrate is 15 ° to 4 °.
By setting the angle to 5 °, the compressive stress applied to the semiconductor substrate when the selective oxide film is grown inside the trench can be reduced, and the head of the selective oxide film can be flattened. In particular, it is formed by etching. It is suitable for manufacturing a semiconductor device having a minimum opening width of 0.1 to 0.3 μm.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.
Hereinafter, each step will be described separately.

(1) As shown in FIG. 1A, a pad oxide film 32 having a thickness of 150 nm is formed on a p-type semiconductor substrate 31 by thermal oxidation in a dry oxygen atmosphere at 850 ° C. .

(2) Next, a silicon nitride film 33 is deposited on the pad oxide film 32 by a CVD method in an atmosphere of 720 ° C. to a thickness of about 200 nm, and then the silicon nitride film 33 is formed by a well-known photolithography method. A portion to be an element isolation region in the future is etched by RIE (reactive ion etching) method. The pattern of the silicon nitride film 33 left by this etching acts as an oxidation resistant film in the selective oxidation step.

(3) As shown in FIG. 1B, after the pad oxide film 32 is etched using the silicon nitride film 33 as a mask, the semiconductor substrate 31 is further etched to form trenches 34 and 34 '. At this time, the etching conditions by the RIE method are appropriately adjusted so that the angle θ formed by the trench side wall 41 with respect to the normal surface of the substrate is about 30 °. At the minimum trench width, the opening width at the top of the trench is about 0.14 μm, and the width at the bottom of the trench is about 0.
It is 04 μm. At this time, the depth of the trench is about 0.15 μm.

(4) After that, channel stopper ions 35 are implanted into the entire surface of the semiconductor substrate 31. For example, BF ₂ ⁺ is used as the channel stopper ion 35, and the implantation is performed under the conditions of energy of 80 KeV and dose amount of 4 × 10 ¹³ cm ⁻² , for example.

(5) Next, as shown in FIG. 1C, selective oxidation (LOCOS oxidation) is performed. Selective oxidation is 1000
It is performed for about 150 minutes in a wet oxygen atmosphere at 0 ° C. so that the oxide film thickness is 500 nm on the flat surface of the semiconductor substrate 31. The trench 34 in the narrow element isolation portion is completely filled with the selective oxide film 36 which grows also from the side wall, and also in the trench 34 'in the wide element isolation region, the selective oxide film 36' is formed so as to fill the trench. It

(6) After that, as shown in FIG.
The silicon nitride film 33 used as the oxidation resistant film is removed by hot phosphoric acid, and the pad oxide film 32 is removed by hydrofluoric acid. Thereby, the element region 38 and the element isolation region 3
The separation formation with 9 is completed.

Then, after that, desired elements are formed in the element regions by a known method to complete the semiconductor device.

As described above, according to this embodiment, when an extremely narrow element isolation region having a minimum width of 0.1 to 0.3 μm is provided, the semiconductor substrate in that region is separated from the normal surface of the substrate by 15 °.
By forming the trench having the side wall forming an angle of ˜45 °, it becomes possible to form a thicker selective oxide film than in the case of the conventional selective oxidation method (FIG. 3). This is for the following reason.

That is, as shown in FIGS. 1B and 1C, the cross section of the element isolation region has a width of 0.1 to 0.3.
In the narrow element isolation region of μm, the selective oxide film grows not only from the bottom of the trench but also from both side walls due to the existence of the trench having the inclined side wall, and the trench is filled with the selective oxide film. The thickness of this selective oxide film is increased by the depth of the trench as compared with the conventional selective oxidation method in which only the oxidation resistant film is etched and no trench is formed in the semiconductor substrate (when there is no trench). It is possible. Therefore, a selective oxide film having a sufficient thickness is formed even in a narrow element isolation region. Since this selective oxide film becomes a field oxide film, the threshold value of the parasitic MOS transistor can be kept sufficiently high, and the element isolation characteristics can be kept good.

Further, the step of etching back the BPSG film, which is required in the conventional manufacturing method by the so-called trench isolation method (FIG. 4), is not required, and it is sufficiently thick not only in the narrow element isolation region but also in the wide element isolation region. It is possible to leave the field oxide film. That is, the number of steps is not significantly increased as in the conventional trench isolation method, and only the number of steps for etching the trench in the semiconductor substrate is increased as compared with the conventional selective oxidation method. Therefore, the cost increase is minimized.

Further, the selective oxide film, which later becomes the field oxide film, is formed below the surface of the semiconductor substrate in both the narrow element isolation region and the wide element isolation region as compared with the conventional selective oxidation method. Therefore, the surface of the semiconductor substrate becomes flatter at the end of the element isolation process.

In this embodiment, the angle formed between the side surface of the trench and the normal surface of the semiconductor substrate is 30 °, but the angle is not limited to this and may be in the range of 15 ° to 45 °. This is for the following reason.

That is, when the angle is 15 ° or less, even if an attempt is made to grow the selective oxide film inside the trench, the amount of deformation of the selective oxide film is limited by the oxidation resistant film, so that a very large compression occurs. Stress is applied to the semiconductor substrate. This induces defects in the semiconductor substrate and causes junction leakage.

On the other hand, when the angle is 45 ° or more,
If the selective oxide film is not grown more than necessary, the trench groove is not completely filled, and the head of the selective oxide film has a V-shaped scooped shape. This causes yield deterioration such as etching residue in the etching step of a polysilicon gate for forming a gate electrode later.

FIG. 2 shows the relationship between the opening width (trench width) of the silicon nitride film and the selective oxide film thickness in the case of the method of this embodiment and the case of the conventional selective oxidation method. Is. However, in this figure, the data in the method of the present invention shows that the angle between the sidewall of the trench and the slope of the substrate is about 20.
It is for the case of °. As is clear from this figure, according to the method for forming the element isolation region of the present embodiment,
Thinning of the selective oxide film is sufficiently suppressed as compared with the conventional selective oxidation method.

In this embodiment, the silicon nitride film 33 is used as the oxidation resistant film in the step of FIG. 1A, but the present invention is not limited to this, and any other substance may be used as long as it has oxidation resistance. You may use.

Further, about 50 nm of polycrystalline silicon is deposited between the pad oxide film 32 and the silicon nitride film 33, and this is used as a pad polycrystalline silicon film to prevent defects that may occur during selective oxidation. Is also possible.

Further, in this embodiment, BF ₂ ⁺ is used as the channel stopper ion 35, but it is not limited to this and other channel stopper ions (B ⁺ etc.) may be used.

[0037]

As described above, according to the first aspect of the invention, the trench having the side wall forming an angle of 15 ° to 45 ° with the normal surface of the semiconductor substrate surface is formed in the semiconductor substrate surface of the element isolation region. Since it is formed, the film thickness of the selective oxide film can be made thicker than in the case of the conventional selective oxidation method even in an extremely narrow element isolation region.
As a result, the threshold value of the parasitic MOS transistor is kept sufficiently high, and good element isolation characteristics can be secured. In addition, the manufacturing cost of the so-called trench isolation method can be minimized because the number of steps required for etching is increased.

According to the second aspect of the invention, the angle between the sidewall of the trench provided on the surface of the semiconductor substrate in the element isolation region and the slope of the semiconductor substrate is 15 ° to 45 °.
Since the compressive stress applied to the semiconductor substrate when the selective oxide film is grown inside the trench can be reduced and the head of the selective oxide film can be flattened, subsequent steps such as gate formation can be performed more stably. It becomes possible. This method is particularly suitable for manufacturing a semiconductor device in which the minimum opening width formed by etching is 0.1 to 0.3 μm.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an explanatory view showing a comparison between a selective oxide film thickness of an element isolation region of a semiconductor device manufactured by the process of FIG. 1 and a selective oxide film thickness of an element isolation region manufactured by a conventional selective oxidation method.

FIG. 3 is an explanatory view showing a manufacturing process of a semiconductor device by a conventional selective oxidation method.

FIG. 4 is an explanatory view showing a manufacturing process of a semiconductor device by a conventional trench method.

[Explanation of symbols]

 31 semiconductor substrate 32 pad oxide film 33 silicon nitride film 34 trench 35 channel stopper ion 36 selective oxide film 38 device region 39 device isolation region 41 trench sidewall

Claims (2)

[Claims] 1. Corresponding to an element region by depositing an oxidation resistant film on a semiconductor substrate, and by etching only a portion corresponding to the element isolation region of the oxidation resistant film to provide an opening. The method includes a step of forming a mask pattern made of an oxidation resistant film remaining in a portion, and a step of forming a selective oxide film by performing selective oxidation using the mask pattern as an oxidation resistant mask. In a method for manufacturing a semiconductor device that uses an element isolation insulating film of a device, after the step of forming the mask pattern, a sidewall that is inclined with respect to the slope of the semiconductor substrate is further formed on the semiconductor substrate surface of the element isolation region. A method of manufacturing a semiconductor device, comprising the step of forming a trench having the same. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an angle formed by a sidewall of the trench with respect to a slope of the semiconductor substrate is in a range of 15 ° to 45 °.