JPH0244143B2 - HANDOTAISOCHINOSEIZOHOHO - Google Patents
HANDOTAISOCHINOSEIZOHOHOInfo
- Publication number
- JPH0244143B2 JPH0244143B2 JP19140685A JP19140685A JPH0244143B2 JP H0244143 B2 JPH0244143 B2 JP H0244143B2 JP 19140685 A JP19140685 A JP 19140685A JP 19140685 A JP19140685 A JP 19140685A JP H0244143 B2 JPH0244143 B2 JP H0244143B2
- Authority
- JP
- Japan
- Prior art keywords
- interlayer insulating
- insulating film
- semiconductor device
- manufacturing
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 229910052782 aluminium Inorganic materials 0.000 claims description 20
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000005530 etching Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000002844 melting Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関するもの
で、特に層間絶縁膜の形成に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to the formation of an interlayer insulating film.
半導体装置の高集積化に伴い素子形成後の配線
は一層のみでは足りず多層配線が通常用いられ
る。
As semiconductor devices become more highly integrated, a single layer of wiring after element formation is no longer sufficient, and multilayer wiring is usually used.
この多層配線は第２図の工程別素子断面図に示
されるようにまず素子形成後の半導体基板１上に
第１層目のアルミニウ配線層２をアルミニウムの
蒸着およびエツチングによるパターニングで形成
し、その周囲に200〜250℃の比較的低温でプラズ
マCVD法により厚さ約3000Åのシリコン酸化膜
３を形成する（第２図ａ）。 As shown in the step-by-step device cross-sectional diagram of FIG. 2, this multilayer wiring is first formed by forming a first aluminum wiring layer 2 on the semiconductor substrate 1 after the device is formed by vapor deposition of aluminum and patterning it by etching. A silicon oxide film 3 with a thickness of about 3000 Å is formed around the substrate by plasma CVD at a relatively low temperature of 200 to 250° C. (FIG. 2a).
次にこの上に同様にプラズマCVD法により約
300℃の温度でシリコン酸化膜４を形成し、先に
形成されたシリコン酸化膜３と合わせて約1μｍ
の厚さになるようにする（第２図ｂ）。 Next, approximately 100% of
Silicon oxide film 4 is formed at a temperature of 300°C, and together with the previously formed silicon oxide film 3, it has a thickness of about 1 μm.
(Figure 2b).
次にこの上にシリコン窒化膜（Si3N4）５を
CVD法により形成し（第２図ｃ）、さらにこれを
反応性イオンエツチング（RIE）によりエツチバ
ツクすると、平坦化されたシリコン酸化膜４′が
得られる（第２図ｄ）。 Next, a silicon nitride film (Si 3 N 4 ) 5 is placed on top of this.
When it is formed by CVD (FIG. 2c) and then etched back by reactive ion etching (RIE), a planarized silicon oxide film 4' is obtained (FIG. 2d).
次に再度シリコン酸化膜６をプラズマCVD法
で形成し、その上に上層の第２の配線層７をアル
ミニウム蒸着およびフオトエツチングによるパタ
ーニングによつて形成する（第２図ｅ）。 Next, a silicon oxide film 6 is formed again by the plasma CVD method, and an upper second wiring layer 7 is formed thereon by aluminum evaporation and patterning by photoetching (FIG. 2e).
このように第１の配線１上のシリコン酸化膜を
２段階で形成しているのはヒロツク防止のためで
ある。 The reason why the silicon oxide film on the first wiring 1 is formed in two steps is to prevent hillocks.
すなわち、アルミニウムの配線層を形成後層間
絶縁のためのシリコン酸化膜を従来行われている
ように300℃前後の比較的高温で形成すると、ア
ルミニウムの結晶再配列に伴い表面に応力集中が
起つて盛り上るヒロツクとよばれる突起が発生
し、第３図に示されるようにヒロツク８はシリコ
ン酸化膜４中を成長して上層に形成されたアルミ
ニウム配線層７に達してシヨートを発生させて歩
留りを低下させ、シヨートに至らない場合にも信
頼性を低下させる。 In other words, if a silicon oxide film for interlayer insulation is formed at a relatively high temperature of around 300°C as is conventionally done after forming an aluminum wiring layer, stress concentration will occur on the surface due to aluminum crystal rearrangement. A raised protrusion called a hillock is generated, and as shown in FIG. 3, the hillock 8 grows in the silicon oxide film 4 and reaches the aluminum wiring layer 7 formed in the upper layer, generating a short and reducing the yield. The reliability is also lowered even if short-circuiting does not occur.
ヒロツクの発生を抑制するためには応力集中が
生じないように層間絶縁膜の形成温度を低下させ
ればよいが、この場合下層の第１アルミニウム配
線層の段差部での被覆性が悪化し、上層の第２ア
ルミニウム配線層を形成した際に断線を招くとい
う問題があり、また低温で形成した層間絶縁膜は
膜質が良好でなく、絶縁性の低下、エツチングの
不均一性等の欠陥を招く。 In order to suppress the occurrence of hillocks, the temperature at which the interlayer insulating film is formed may be lowered to prevent stress concentration, but in this case, the coverage of the step portion of the first aluminum wiring layer in the lower layer deteriorates. There is a problem that disconnection occurs when the upper second aluminum wiring layer is formed, and the interlayer insulating film formed at low temperature has poor film quality, leading to defects such as reduced insulation and non-uniform etching. .
ヒロツクの発生を抑制する他の方法としてはア
ルミニウム層の表面にチタン等の高融点金属ある
いはTiSi等の高融点金属珪化物を形成する方法
がある。しかしこの方法ではまず高融点金属層の
形成等、工程が増加する上、エツチングに困難が
伴い、さらにアルミニウム配線側面には高融点金
属等が存在しないことから側面におけるヒロツク
成長を抑えることができず、微細化上の要求に対
しては有効ではない。 Another method for suppressing the occurrence of hillocks is to form a high melting point metal such as titanium or a high melting point metal silicide such as TiSi on the surface of the aluminum layer. However, this method first requires more steps such as forming a high-melting point metal layer, and etching is difficult.Furthermore, since there is no high-melting point metal on the side surfaces of the aluminum wiring, it is not possible to suppress the growth of hills on the side surfaces. , it is not effective against miniaturization requirements.
このような観点から最初に述べた方法が採用さ
れるがこの方法にも問題がある。 From this point of view, the first method mentioned above is adopted, but this method also has its problems.
すなわち、第１のアルミニウム配線層上に形成
されたシリコン酸化膜４を平坦化する際シリコン
酸化膜４の厚さが所期の厚さよりも薄かつたと
き、あるいはRIEによるエツチング量が多すぎた
ときには第４図に示すようにアルミニウム配線層
２の表面が露出してしまう場合がある。この状態
で通常の比較的高温の条件で第２のシリコン酸化
膜を形成すると第３図に示す状態となり、ヒロツ
ク８が発生する。 That is, when the silicon oxide film 4 formed on the first aluminum wiring layer is planarized, the thickness of the silicon oxide film 4 is thinner than the expected thickness, or the amount of etching by RIE is too large. In some cases, the surface of the aluminum wiring layer 2 may be exposed as shown in FIG. If a second silicon oxide film is formed in this state under normal relatively high temperature conditions, the state shown in FIG. 3 will occur, and hillocks 8 will occur.
本発明はこのような問題を解決するためなされ
たもので、ヒロツクの発生を有効に防止できる多
層配線を含む半導体装置の製造方法を提供するこ
とを目的とする。
The present invention has been made to solve such problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device including multilayer wiring, which can effectively prevent the occurrence of hillocks.
上記目的達成のため、本発明によれば素子形成
後第１の配線層を形成し、その上に第１の層間絶
縁膜を形成してエツチバツクによる平坦化処理を
行なつた後第２の層間絶縁膜をヒロツクの発生し
ない温度範囲およびその後のより高温の温度範囲
の２段階で形成し、さらにその上に第２の配線層
を形成するようにしている。このように第２の層
間絶縁膜を２段階で形成することにより、エツチ
バツク時に第１の配線層表面が露出してもヒロツ
クの発生を有効に防止することができる。
In order to achieve the above object, according to the present invention, after forming a device, a first wiring layer is formed, a first interlayer insulating film is formed thereon, a planarization process is performed by etching back, and then a second interlayer insulating film is formed. The insulating film is formed in two stages: in a temperature range where hillocks do not occur and then in a higher temperature range, and then a second wiring layer is formed thereon. By forming the second interlayer insulating film in two steps in this way, it is possible to effectively prevent the occurrence of hills even if the surface of the first wiring layer is exposed during etchback.
以下図面を参照しながら本発明の一実施例を詳
細に説明する。
An embodiment of the present invention will be described in detail below with reference to the drawings.
第１図は本発明にかかる半導体装置の製造方法
を示す工程別断面図であつて、素子形成後の半導
体基板１上に多層配線を形成する様子を示すもの
である。 FIG. 1 is a step-by-step cross-sectional view showing a method for manufacturing a semiconductor device according to the present invention, and shows how multilayer wiring is formed on a semiconductor substrate 1 after forming elements.
この方法においてはエツチバツク工程までは従
来と同様である。すなわち、素子形成後の半導体
基板１上に第１のアルミニウム配線層２を形成し
てその周囲に厚さ約3000Åのシリコン酸化膜３を
200〜250℃の温度範囲でプラズマCVD法により
形成し（第１図ａ）。その上にシリコン酸化膜４
を約300℃の温度でプラズマCVD法により全体が
約1μｍになるようにし（第１図ｂ）、さらにシリ
コン窒化膜５をCVD法により形成して（第１図
ｃ）、RIE法によりエツチバツクを行うと、平坦
化されたシリコン酸化膜４″が得られる（第１図
ｄ）。このとき、第１層のアルミニウム配線層の
表面には通常はシリコン酸化膜が残存するのであ
るが、ここでは極端な場合として形成されたシリ
コン酸化膜４の厚さが不足であるかRIEによるエ
ツチング量が過大であるための第１層のアルミニ
ウム配線層２の表面が全面的に露出した状態とな
つているものとして以下の説明を行なう。 This method is the same as the conventional method up to the etchback step. That is, a first aluminum wiring layer 2 is formed on the semiconductor substrate 1 after the element formation, and a silicon oxide film 3 with a thickness of about 3000 Å is formed around it.
It is formed by plasma CVD method at a temperature range of 200 to 250°C (Fig. 1a). On top of that is a silicon oxide film 4.
The silicon nitride film 5 is formed to have a total thickness of about 1 μm by plasma CVD at a temperature of about 300°C (Fig. 1b), and then a silicon nitride film 5 is formed by CVD (Fig. 1c), and then etched back by RIE. When this is done, a flattened silicon oxide film 4'' is obtained (Fig. 1d).At this time, normally a silicon oxide film remains on the surface of the first aluminum wiring layer, but here In extreme cases, the thickness of the silicon oxide film 4 formed is insufficient or the amount of etching by RIE is excessive, so that the surface of the first aluminum wiring layer 2 is completely exposed. The following explanation is given as follows.
この上にシリコン酸化膜１１をプラズマCVD
法を用い、200〜250℃の温度範囲で厚さ約3000Å
に形成する（第１図ｅ）。 A silicon oxide film 11 is deposited on top of this by plasma CVD.
thickness of approximately 3000Å in the temperature range of 200 to 250℃.
(Fig. 1e).
次にこの上に同様にプラズマCVD法により約
300℃の温度でシリコン酸化膜１２を形成し、先
に形成されたシリコン酸化膜１１を含め合計約
1.5μｍの厚さになるようにし、その上にアルミニ
ウムの蒸着およびパターニングにより第２のアル
ミニウム配線層１３が形成される。 Next, approximately 100% of
The silicon oxide film 12 is formed at a temperature of 300°C, and the total amount including the previously formed silicon oxide film 11 is approximately
A second aluminum wiring layer 13 is formed thereon by vapor deposition and patterning of aluminum to a thickness of 1.5 μm.
このようにエツチバツク後に再度シリコン酸化
膜を形成する際に、始めはヒロツクの発生しにく
い比較的低温で、続いてこれよりも高温で厚く形
成するようにしているので、実施例のように第１
のアルミニウム配線の表面が露出してしまつた場
合等においてもヒロツクが発生しにくくなる。 In this way, when forming the silicon oxide film again after etching back, the film is first formed at a relatively low temperature where hillocks are less likely to occur, and then at a higher temperature to form a thicker film.
Hillocks are less likely to occur even when the surface of the aluminum wiring is exposed.
以上の実施例においてはシリコン酸化膜の形成
にあたつて、初期とその後で温度範囲を切換える
ようにしているが、記載した厚さの膜厚が得られ
るような温度上昇曲線を選択して連続的な温度変
化を行うようにしてもよい。 In the above examples, when forming the silicon oxide film, the temperature range is changed between the initial stage and the subsequent stage, but a temperature rise curve that provides the described film thickness is selected and the temperature range is continuously changed. Temperature changes may also be made.
また、エツチバツク工程においては、実施例で
はシリコン窒化膜を使用しているが、これに限る
ことなくRIEで酸化膜と同様のエツチングレート
でエツチングされるものであればよく、例えばレ
ジスト等を使用することができる。 In addition, in the etchback process, although a silicon nitride film is used in the embodiment, the silicon nitride film is not limited to this, and any material that can be etched at the same etching rate as an oxide film by RIE may be used, for example, a resist or the like may be used. be able to.
なお、上述した温度変化は同一工程内での変化
であり実質的な工程の増加はない。 Note that the temperature change described above is a change within the same process, and there is no substantial increase in the number of processes.
以上のように本発明によれば層間絶縁膜の平坦
化処理後に形成される層間絶縁膜をヒロツクの発
生しない温度範囲およびその後のより高温の温度
範囲の２段階で形成し、その上に上層の配線層を
設けるようにしているので、平坦化処理時に下層
配線層が露出してもヒロツクの発生を防止しつつ
良好な膜質を有する層間絶縁膜が得られ、歩留り
および信頼性の高い多層配線構造を得ることがで
きる。
As described above, according to the present invention, the interlayer insulating film formed after the interlayer insulating film is planarized is formed in two stages: the temperature range where no hillocks occur and the subsequent higher temperature range, and then the upper layer is formed on top of the interlayer insulating film. Since a wiring layer is provided, even if the lower wiring layer is exposed during the planarization process, it is possible to prevent the occurrence of hillocks and to obtain an interlayer insulating film with good film quality, resulting in a multilayer wiring structure with high yield and reliability. can be obtained.
第１図は本発明の一実施例を示す工程別断面
図、第２図は従来の方法を示す工程別断面図、第
３図および第４図は従来方法の問題点を示す説明
図である。
１……基板、２，７……アルミニウム配線層、
３，６，１１……低温で形成された酸化膜、４，
６，１２……高温で形成された酸化膜。
FIG. 1 is a sectional view of each step showing an embodiment of the present invention, FIG. 2 is a sectional view of each step of a conventional method, and FIGS. 3 and 4 are explanatory diagrams showing problems with the conventional method. . 1... Board, 2, 7... Aluminum wiring layer,
3, 6, 11...Oxide film formed at low temperature, 4,
6, 12...Oxide film formed at high temperature.
Claims (1)
所定のパターンで形成する工程と、 この第１の配線層上に第１の層間絶縁膜を形成
する工程と、 この層間絶縁膜を平坦化処理する工程と、 この上に第２の層間絶縁膜をヒロツクの発生し
ない温度範囲およびその後のより高温の温度範囲
の２段階で形成する工程と、 を備えた半導体装置の製造方法。 ２ 層間絶縁膜がシリコン酸化膜である特許請求
の範囲第１項記載の半導体装置の製造方法。 ３ 層間絶縁膜がプラズマCVD法で形成される
特許請求の範囲第２項記載の半導体装置の製造方
法。 ４ 第１の層間絶縁膜がヒロツクの発生しない温
度範囲およびその後のより高温の温度範囲の２段
階で形成される特許請求の範囲第３項記載の半導
体装置の製造方法。 ５ 平坦化処理が反応性イオンエツチングによる
エツチバツクにより行われる特許請求の範囲第１
項記載の半導体装置の製造方法。 ６ 第１および第２の配線層がパターニングされ
たアルミニウム層である特許請求の範囲第１項記
載の半導体装置の製造方法。 ７ 第２の層間絶縁膜の形成が連続的な温度上昇
下で行われる特許請求の範囲第１項記載の半導体
装置の製造方法。[Claims] 1. A step of forming a first wiring layer in a predetermined pattern on a semiconductor substrate after forming an element, and a step of forming a first interlayer insulating film on the first wiring layer, A semiconductor device comprising: a step of planarizing the interlayer insulating film; and a step of forming a second interlayer insulating film thereon in two stages: in a temperature range where no hillocks occur and then in a higher temperature range. manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a silicon oxide film. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the interlayer insulating film is formed by a plasma CVD method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the first interlayer insulating film is formed in two steps: a temperature range where hillocks do not occur and a subsequent higher temperature range. 5. Claim 1 in which the planarization process is performed by etchback using reactive ion etching.
A method for manufacturing a semiconductor device according to section 1. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second wiring layers are patterned aluminum layers. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the formation of the second interlayer insulating film is performed under continuous temperature rise.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19140685A JPH0244143B2 (en) | 1985-08-30 | 1985-08-30 | HANDOTAISOCHINOSEIZOHOHO |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19140685A JPH0244143B2 (en) | 1985-08-30 | 1985-08-30 | HANDOTAISOCHINOSEIZOHOHO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6251243A JPS6251243A (en) | 1987-03-05 |
| JPH0244143B2 true JPH0244143B2 (en) | 1990-10-02 |
Family
ID=16274071
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19140685A Expired - Lifetime JPH0244143B2 (en) | 1985-08-30 | 1985-08-30 | HANDOTAISOCHINOSEIZOHOHO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0244143B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR910003742B1 (en) * | 1986-09-09 | 1991-06-10 | 세미콘덕터 에너지 라보라터리 캄파니 리미티드 | Cvd apparatus |
| JPH02106968A (en) * | 1988-10-17 | 1990-04-19 | Hitachi Ltd | Semiconductor integrated circuit device and forming method thereof |
-
1985
- 1985-08-30 JP JP19140685A patent/JPH0244143B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6251243A (en) | 1987-03-05 |
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Legal Events
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| EXPY | Cancellation because of completion of term |