KR20020053949A - Method for forming metal interconnection layer of semiconductor device - Google Patents
Method for forming metal interconnection layer of semiconductor device Download PDFInfo
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- KR20020053949A KR20020053949A KR1020000081928A KR20000081928A KR20020053949A KR 20020053949 A KR20020053949 A KR 20020053949A KR 1020000081928 A KR1020000081928 A KR 1020000081928A KR 20000081928 A KR20000081928 A KR 20000081928A KR 20020053949 A KR20020053949 A KR 20020053949A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성방법에 관한 것으로, 보다 상세하게는, 베리어막의 증착 불량을 방지하면서 공정 마진을 확보할 수 있는 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device capable of securing a process margin while preventing deposition failure of a barrier film.
주지된 바와 같이, 금속배선의 재료로서는 전기 전도도가 매우 우수한 알루미늄(Al)이 주로 이용되고 있으며, 알루미늄 배선은 물리기상증착(Physical Vapor Deposition : 이하, PVD) 공정에 의한 알루미늄의 증착 및 패터닝을 통해 형성하고 있다. 또한, 상기 알루미늄 배선을 포함한 통상의 금속배선의 형성시에는 실질적인 배선 재료의 하부에 베리어막(barrier layer)을 배치시키고, 그리고, 상부에는 반사방지막을(Anti Reflective Coating layer)을 배치시킨 상태로 형성하고 있다.As is well known, aluminum (Al), which has excellent electrical conductivity, is mainly used as a material for metal wiring, and aluminum wiring is formed through deposition and patterning of aluminum by a physical vapor deposition (PVD) process. Forming. In addition, when forming a conventional metal wiring including the aluminum wiring, a barrier layer is disposed under the substantial wiring material, and an anti-reflective coating layer is disposed on the upper portion. Doing.
여기서, 상기 베리어막은 배선 재료, 예를들어, 알루미늄막의 접착력를 증대시키면서, 알루미늄과 기판 실리콘간의 반응이 일어나는 것을 방지하기 위해 형성되는 것으로서, 통상, 티타늄/티타늄질화(Ti/TiN)막이 이용되고 있다.Here, the barrier film is formed to prevent the reaction between the aluminum and the substrate silicon from occurring while increasing the adhesion of the wiring material, for example, the aluminum film, and a titanium / titanium nitride (Ti / TiN) film is usually used.
한편, 반도체 소자의 고집적화에 따라, 금속배선과 하부 구조물간의 전기적 연결 통로를 제공하는 콘택홀의 크기도 작아지고 있는데, 이 경우, PVD 공정을 이용한 알루미늄의 콘택홀의 완전 매립에 어려움이 있으며, 심한 경우, 오픈 불량이 발생하기도 한다. 따라서, 이러한 콘택홀 매립의 문제를 해결하기 위해, 종래에는 매립 특성이 우수한 금속막, 예컨데, 텅스텐막으로 콘택홀을 완전하게 매립시켜, 이것을 콘택 플러그로 이용하고 있다.On the other hand, according to the high integration of the semiconductor device, the size of the contact hole providing the electrical connection path between the metal wiring and the lower structure is also decreasing, in this case, it is difficult to completely fill the contact hole of aluminum using the PVD process, in severe cases, Open failure may occur. Therefore, in order to solve such a problem of contact hole embedding, conventionally, a contact hole is completely filled with a metal film excellent in embedding characteristics, for example, a tungsten film, and this is used as a contact plug.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 각 공정별 단면도로서, 이를 설명하면 다음과 같다.1A to 1D are cross-sectional views of respective processes for explaining a method for forming metal wirings of a semiconductor device according to the prior art.
먼저, 도 1a에 도시된 바와 같이, 트랜지스터와 같은 소정의 하부 구조물(도시안됨)이 형성된 실리콘 기판(1) 상에 상기 하부 구조물을 덮도록 두껍게 절연막(2)을 증착한 상태에서, 상기 절연막(2)의 일부분은 공지의 포토리소그라피 공정으로 식각해서, 상기 실리콘 기판의 소정 부분을 노출시키는 콘택홀(3)을 형성한다.First, as illustrated in FIG. 1A, the insulating film 2 is deposited on the silicon substrate 1 on which a predetermined lower structure (not shown), such as a transistor, is formed so as to cover the lower structure. A portion of 2) is etched by a known photolithography process to form a contact hole 3 exposing a predetermined portion of the silicon substrate.
그 다음, 도 1b에 도시된 바와 같이, 스퍼터링 공정을 통해서 콘택홀(3)의 내면 및 절연막(2) 상에 베리어막(4), 예컨데, Ti/TiN막을 균일한 두께로 증착하고, 연이어서, 상기 콘택홀(3)이 완전히 매립되도록 텅스텐막(5)을 증착한다.Then, as shown in FIG. 1B, a barrier film 4, for example, a Ti / TiN film, is deposited on the inner surface of the contact hole 3 and the insulating film 2 through a sputtering process to a uniform thickness, and subsequently The tungsten film 5 is deposited to completely fill the contact hole 3.
다음으로, 도 1c에 도시된 바와 같이, 베리어막(4)이 노출될 때까지, 상기 텅스텐막을 에치백, 또는, 연마해서 콘택 플러그(5a)를 형성하고, 이어서, 스퍼터링 공정으로 상기 콘택 플러그(5a) 및 베리어막(4) 상에 알루미늄막(6)과 반사방지막(7), 예컨데, Ti/TiN막을 차례로 증착한다.Next, as shown in Fig. 1C, the tungsten film is etched back or polished until the barrier film 4 is exposed, thereby forming the contact plug 5a, and then the contact plug (sputtering process) On the 5a) and barrier film 4, an aluminum film 6 and an antireflection film 7, for example, a Ti / TiN film, are deposited in this order.
그리고나서, 도 1d에 도시된 바와 같이, 공지된 포토리소그라피 공정을 이용하여 반사방지막(7), 알루미늄막(6) 및 베리어막(4)을 패터닝함으로써, 콘택 플러그(5a)를 갖는 알루미늄 배선(10)을 완성한다.Then, as shown in FIG. 1D, by using a known photolithography process, the anti-reflection film 7, the aluminum film 6, and the barrier film 4 are patterned to form an aluminum wiring having the contact plug 5a ( Complete 10).
그러나, 전술한 바와 같은 종래의 금속배선 형성방법은, 콘택홀의 크기 대비 높이의 비율이 작은 경우에는 커다란 문제점이 없지만, 예컨데, 상기 비율이 1 : 5 이상으로 매우 클 경우에는 베리어막이 콘택홀의 저면에 제대로 증착되지 못하는 현상이 초래되며, 이에 따라, 후속 공정이 진행되면서 실리콘 기판과 베리어막의계면에서 실리사이드가 형성되지 못함은 물론, 상기 베리어막이 그 자체의 기능을 제대로 수행하지 못함으로써, 기판 실리콘과 알루미늄간의 반응이 초래될 수 있으며, 그래서, 접촉 저항이 증가되는 등의 소자 신뢰성에 문제가 발생된다.However, the conventional metal wiring forming method as described above does not have a big problem when the ratio of the height to the size of the contact hole is small. For example, when the ratio is very large, such as 1: 5, the barrier film is formed on the bottom of the contact hole. As a result, the deposition process may not be performed properly. Thus, as the subsequent process proceeds, silicide is not formed at the interface between the silicon substrate and the barrier film, and the barrier film does not perform its own function. The reaction of the liver can be caused, and thus problems in device reliability such as an increase in contact resistance arise.
또한, 반도체 소자의 고집적화에 따라 콘택홀과 트랜지스터의 게이트 사이의 거리가 짧아지는 추세에서, 예컨데, 후속의 포토 공정에서 노광 마스크의 오정렬이 발생될 확률이 커지며, 그래서, 트랜지스터의 게이트와 금속배선간의 전기적 쇼트가 발생되는 등의 공정 마진이 확보되지 못하는 문제가 있다.In addition, in the trend of shortening the distance between the contact hole and the gate of the transistor according to the high integration of the semiconductor device, for example, there is a high probability that misalignment of the exposure mask occurs in a subsequent photo process, and thus, between the gate of the transistor and the metal wiring There is a problem that a process margin such as an electrical short occurs is not secured.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 베리어막의 증착 불량을 방지하면서, 공정 마진을 확보할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of securing a process margin while preventing deposition failure of a barrier film.
도 1a 내지 도 1d는 종래 기술에 따른 금속배선 형성방법을 설명하기 위한 각 공정별 단면도.1A to 1D are cross-sectional views for each process for explaining a metal wire forming method according to the prior art.
도 2a 내지 도 2f는 본 발명의 실시예에 따른 금속배선 형성방법을 설명하기 위한 각 공정별 단면도.2A to 2F are cross-sectional views for each process for explaining a method for forming metal wiring according to an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
21 : 실리콘 기판 22 : 제1절연막21 silicon substrate 22 first insulating film
23 : 제1콘택홀 24 : 산화막 스페이서23: first contact hole 24: oxide film spacer
25 : 베리어막 26 : 텅스텐막25: barrier film 26: tungsten film
26a : 제1콘택 플러그 27 : 제2절연막26a: first contact plug 27: second insulating film
28 : 제2콘택홀 29 : 글루막28: second contact hole 29: glue film
30 : 제2콘택 플러그 31 : 알루미늄막30: second contact plug 31: aluminum film
32 : 반사방지막 40 : 알루미늄 배선32: antireflection film 40: aluminum wiring
상기와 같은 목적을 달성하기 위한 본 발명의 금속배선 형성방법은, 소정의 하부 구조물이 형성된 실리콘 기판 상에 소정 두께로 제1절연막을 증착하는 단계; 상기 제1절연막의 일부분을 선택적으로 식각해서, 상기 실리콘 기판의 소정 부분을 노출시키는 제1콘택홀을 형성하는 단계; 상기 제1콘택홀의 측벽에 산화막 스페이서를 형성하는 단계; 상기 단계까지의 결과물 상에 균일한 두께로 베리어막과 상기 제1콘택홀을 완전하게 매립시키는 두께로 플러그용 금속막을 차례로 증착하는 단계; 상기 제1절연막이 노출될 때까지, 상기 플러그용 금속막과 베리어막을 연마해서 상기 제1콘택홀 내에 제1콘택 플러그를 형성하는 단계; 상기 단계까지의 결과물 상에 제2절연막을 소정 두께로 증착하는 단계; 상기 제2절연막의 일부분을 선택적으로 식각해서, 상기 제1콘택 플러그를 노출시키는 제2콘택홀을 형성하는 단계; 상기 제2콘택홀의 내면 및 제2절연막 상에 균일한 두께로 글루막을 증착하는 단계; 상기 제2콘택홀 내에 제2콘택 플러그를 형성하는 단계; 상기 글루막 및 제2콘택 플러그 상에 배선용 금속막과 반사방지막을 차례로 증착하는 단계; 및 상기 반사방지막과 배선용 금속막 및 글루막을 패터닝하는 단계를 포함한다.Metal wiring forming method of the present invention for achieving the above object comprises the steps of: depositing a first insulating film to a predetermined thickness on a silicon substrate having a predetermined lower structure; Selectively etching a portion of the first insulating layer to form a first contact hole exposing a portion of the silicon substrate; Forming an oxide spacer on a sidewall of the first contact hole; Depositing a metal film for plugs in order to completely fill the barrier film and the first contact hole with a uniform thickness on the result up to the step; Forming a first contact plug in the first contact hole by polishing the plug metal film and the barrier film until the first insulating film is exposed; Depositing a second insulating film to a predetermined thickness on the resultant up to the step; Selectively etching a portion of the second insulating layer to form a second contact hole exposing the first contact plug; Depositing a glue film with a uniform thickness on an inner surface of the second contact hole and a second insulating film; Forming a second contact plug in the second contact hole; Sequentially depositing a wiring metal film and an antireflection film on the glue film and the second contact plug; And patterning the antireflection film, the wiring metal film, and the glue film.
본 발명에 따르면, 콘택홀 및 콘택 플러그의 형성을 2층 구조로 형성하기 때문에, 베리어막의 증착 불량이 발생되는 것을 방지할 수 있으며, 아울러, 하부에 배치된 제1콘택홀의 측벽에 산화막 스페이서를 형성하는 것에 기인해서 포토 공정에서의 공정 마진을 확보할 수 있다.According to the present invention, since the contact holes and the contact plugs are formed in a two-layer structure, deposition failure of the barrier film can be prevented from occurring, and an oxide film spacer is formed on the sidewalls of the first contact holes disposed below. Due to this, the process margin in the photo process can be secured.
(실시예)(Example)
이하, 첨부된 도면을 참조해서 본 발명의 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도2f는 본 발명의 실시예에 따른 금속배선 형성방법을 설명하기 위한 각 공정별 단면도로서, 이를 설명하면 다음과 같다.2A to 2F are cross-sectional views for each process for explaining a method for forming metal wiring according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이, 트랜지스터와 같은 소정의 하부 구조물(도시안됨)이 형성된 실리콘 기판(21) 상에 제1절연막(22)을 증착한다. 그런다음, 상기 제1절연막(22)의 일부분을 선택적으로 식각해서 상기 실리콘 기판(21)의 소정 부분을 노출시키는 제1콘택홀(23)을 형성한다. 여기서, 상기 제1절연막(22)은 종래의 층간절연막(Inter Metal Dielectric : IMD)의 두께 보다는 낮은 두께, 예컨데, 1/2 정도의 두께로 증착함이 바람직하며, 또한, 상기 제1콘택홀(23)은 크기 대비높이의 비율이 1 : 5 이하, 예컨데, 1 : 1∼4 정도로 형성함이 바람직하다. 이어서, 상기 제1콘택홀(23)의 내면 및 절연막(22) 상에 균일한 두께로 산화막을 증착한 후, 상기 산화막을 에치백하여 상기 제1콘택홀(23)의 측벽에 산화막 스페이서(24)를 형성한다.First, as shown in FIG. 2A, a first insulating layer 22 is deposited on a silicon substrate 21 on which a predetermined substructure (not shown) such as a transistor is formed. Then, a portion of the first insulating layer 22 is selectively etched to form a first contact hole 23 exposing a predetermined portion of the silicon substrate 21. Here, the first insulating layer 22 is preferably deposited to a thickness lower than that of a conventional intermetal dielectric (IMD), for example, a thickness of about 1/2, and the first contact hole ( 23), the ratio of height to size is preferably 1: 5 or less, for example, about 1: 1 to 4. Subsequently, an oxide film is deposited to a uniform thickness on the inner surface of the first contact hole 23 and the insulating film 22, and then the oxide film is etched back to form an oxide spacer 24 on the sidewall of the first contact hole 23. ).
다음으로, 도 2b에 도시된 바와 같이, 스퍼터링 공정을 이용해서 상기 결과물 상에 균일한 두께로 Ti/TiN막으로 이루어진 베리어막(25)을 증착하고, 그런다음, 상기 제1콘택홀(23)이 완전 매립되도록, 상기 베리어막(25) 상에 플러그용 금속막, 예컨데, 텅스텐막(26)을 증착한다. 여기서, 상기 베리어막(25)은 상기 제1콘택홀(23)의 크기 대비 높이의 비율이 크지 않은 것, 예컨데, 종래의 1/2 정도의 수준인 것에 기인해서 증착 불량은 일어나지 않는다.Next, as shown in FIG. 2B, a barrier film 25 made of a Ti / TiN film is deposited on the resultant material using a sputtering process with a uniform thickness. Then, the first contact hole 23 is formed. A plug metal film, for example, a tungsten film 26, is deposited on the barrier film 25 so as to be completely buried. Here, the barrier film 25 is not a large ratio of the height to the size of the first contact hole 23, for example, due to the level of about 1/2 of the conventional deposition failure does not occur.
이어서, 도 2c에 도시된 바와 같이, 제1절연막이 노출될 때까지, 상기 텅스텐막과 베리어막을 화학적 기계적 연마(Chemcial mechanical Polishing : 이하, CMP) 공정을 통해 연마해서 상기 제1콘택홀(23) 내에 제1콘택 플러그(26a)를 형성한다.Subsequently, as shown in FIG. 2C, the tungsten film and the barrier film are polished through a chemical mechanical polishing (CMP) process until the first insulating film is exposed to form the first contact hole 23. The first contact plug 26a is formed in the inside.
다음으로, 도 2d에 도시된 바와 같이, 상기 결과물 상에 제2절연막(27)을 증착하고, 그런다음, 상기 제2절연막(27)의 일부분을 선택적으로 식각하여, 상기 제2절연막(27)에 상기 제1콘택 플러그(26a)를 노출시키는 제2콘택홀(28)을 형성한다. 여기서, 상기 제2절연막(27)의 증착 두께는 상기 제1절연막(22)과의 두께 합이 종래의 IMD의 두께와 유사한 두께를 갖도록 함이 바람직하다. 또한, 상기 제2콘택홀(28)은 크기 대비 높이의 비율이 제1콘택홀과 마찬가지로 1 : 5 이하, 예컨데, 1 : 1∼4 정도로 형성함이 바람직하다.Next, as shown in FIG. 2D, a second insulating layer 27 is deposited on the resultant, and then a portion of the second insulating layer 27 is selectively etched to form the second insulating layer 27. A second contact hole 28 exposing the first contact plug 26a is formed in the second contact hole 28. Here, the deposition thickness of the second insulating layer 27 is preferably such that the sum of the thicknesses with the first insulating layer 22 has a thickness similar to that of the conventional IMD. In addition, the second contact hole 28 is preferably formed to have a ratio of height to size equal to or less than 1: 5, for example, about 1: 1 to 4, similarly to the size of the first contact hole.
계속해서, 도 2e에 도시된 바와 같이, 상기 제2콘택홀(28)의 내면 및 제2절연막(27) 상에 Ti/TiN막으로 이루어진 글루막(glue layer : 29)을 증착한다. 이어서, 상기 제2콘택홀(28)이 완전 매립되도록 상기 글루막(29) 상에 플러그용 금속막으로서 텅스텐막을 증착한 후, 상기 글루 금속막(29)이 노출되도록 상기 텅스텐막을 에치백하여 상기 제2콘택홀(28) 내에 제2콘택 플러그(30)를 형성한다.Subsequently, as shown in FIG. 2E, a glue layer 29 made of a Ti / TiN film is deposited on the inner surface of the second contact hole 28 and the second insulating layer 27. Subsequently, after depositing a tungsten film as a plug metal film on the glue film 29 to completely fill the second contact hole 28, the tungsten film is etched back to expose the glue metal film 29. The second contact plug 30 is formed in the second contact hole 28.
그리고나서, 도 2f에 도시된 바와 같이, 상기 결과물 상에 배선용 금속막, 예컨데, 알루미늄막(31)과 Ti/TiN막으로 이루어진 반사방지막(32)을 스퍼터링 공정을 통해 차례로 증착하고, 그런다음, 상기 반사방지막(32), 알루미늄막(31) 및 글루막(29)을 공지된 포토리소그라피 공정으로 패터닝해서 상기 제1 및 제2콘택 플러그(26a, 30)를 통해 실리콘 기판(21)의 소정 부분과 전기적으로 연결되는 알루미늄 배선(40)의 형성을 완성한다.Then, as shown in FIG. 2F, an antireflection film 32 composed of a wiring metal film, for example, an aluminum film 31 and a Ti / TiN film, is sequentially deposited on the resultant through a sputtering process. The antireflection film 32, the aluminum film 31, and the glue film 29 are patterned by a known photolithography process, and a predetermined portion of the silicon substrate 21 through the first and second contact plugs 26a and 30 is formed. Completion of the formation of the aluminum wiring 40 that is electrically connected to the.
상기와 같은 공정을 통해 형성되는 본 발명의 금속배선은 콘택홀 및 콘택 플러그의 형성을 2층 구조로 형성하기 때문에, 베리어막의 증착 불량을 방지할 수 있고, 그래서, 금속배선의 오픈 불량과 같은 결함의 발생을 방지할 수 있다. 또한, 베리어막의 Ti과 기판 Si 사이의 반응에 기인하는 실리사이드의 형성이 안정적으로 이루어지도록 할 수 있기 때문에 접촉 저항의 증가도 방지할 수 있다. 게다가, 콘택홀의 크기 대비 높이의 비율을 낮추면서, 제1콘택홀의 측벽에 산화막 스페이서를 형성시킨 것에 기인해서 공정 마진도 확보할 수 있다.Since the metal wiring of the present invention formed through the above process forms the formation of the contact hole and the contact plug in a two-layer structure, it is possible to prevent the deposition failure of the barrier film, so that the defect such as the open defect of the metal wiring. Can be prevented. In addition, since the formation of the silicide resulting from the reaction between Ti of the barrier film and the substrate Si can be made stable, an increase in contact resistance can also be prevented. In addition, a process margin can be secured due to the formation of an oxide film spacer on the sidewall of the first contact hole while lowering the ratio of the height to the size of the contact hole.
이상에서와 같이, 본 발명은 금속배선의 형성시에 콘택홀의 크기 대비 높이의 비율을 고려해서 콘택홀 및 콘택 플러그의 형성을 2층 구조로 형성하기 때문에, 상기 콘택홀의 크기 대비 높이의 비율이 크지 않은 것에 기인해서 베리어막의 증착 불량에 기인하는 접촉 저항의 증가 및 금속배선의 오픈 불량과 같은 결함의 발생을 방지할 수 있으며, 그래서, 금속배선의 신뢰성은 물론, 소자의 신뢰성을 확보할 수 있다.As described above, since the present invention forms the contact hole and the contact plug in a two-layer structure in consideration of the ratio of the height to the size of the contact hole when the metal wiring is formed, the ratio of the height to the size of the contact hole is not large. It is possible to prevent the occurrence of defects such as an increase in contact resistance and an open defect of the metal wiring due to poor deposition of the barrier film due to the absence of the barrier film, so that the reliability of the metal wiring and the device can be ensured.
또한, 콘택홀의 크기 대비 높이의 비율을 낮추면서 하부에 배치된 제1콘택홀의 측벽에 산화막 스페이서를 형성하기 때문에 포토리소그라피 공정시의 노광 마스크의 오정렬에 기인하는 공정 결함을 최소화시킬 수 있으며, 아울러, 누설 전류의 발생도 방지할 수 있고, 그래서, 공정 마진을 확보할 수 있는 바, 공정 상의 잇점도 얻을 수 있다.In addition, since the oxide spacers are formed on the sidewalls of the first contact holes disposed below while lowering the ratio of the height to the size of the contact holes, process defects due to misalignment of the exposure mask during the photolithography process can be minimized. The generation of leakage current can also be prevented, so that a process margin can be secured, so that a process advantage can also be obtained.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서, 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes, in the range which does not deviate from the summary.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000081928A KR20020053949A (en) | 2000-12-26 | 2000-12-26 | Method for forming metal interconnection layer of semiconductor device |
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| KR1020000081928A KR20020053949A (en) | 2000-12-26 | 2000-12-26 | Method for forming metal interconnection layer of semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050056419A (en) * | 2003-12-10 | 2005-06-16 | 동부아남반도체 주식회사 | Method for forming a metal line in semiconductor device |
| CN115332162A (en) * | 2022-08-02 | 2022-11-11 | 桂林电子科技大学 | Method for preparing metalized polymer through hole with shielding layer based on photoetching technology |
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2000
- 2000-12-26 KR KR1020000081928A patent/KR20020053949A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20050056419A (en) * | 2003-12-10 | 2005-06-16 | 동부아남반도체 주식회사 | Method for forming a metal line in semiconductor device |
| CN115332162A (en) * | 2022-08-02 | 2022-11-11 | 桂林电子科技大学 | Method for preparing metalized polymer through hole with shielding layer based on photoetching technology |
| CN115332162B (en) * | 2022-08-02 | 2023-10-27 | 桂林电子科技大学 | Preparation method of metallized polymer through hole with shielding layer based on photoetching technology |
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