KR100304701B1 - semiconductor device buried via hole with aluminum and tungsten, and manufacturing method thereof - Google Patents
semiconductor device buried via hole with aluminum and tungsten, and manufacturing method thereof Download PDFInfo
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- KR100304701B1 KR100304701B1 KR1019990002180A KR19990002180A KR100304701B1 KR 100304701 B1 KR100304701 B1 KR 100304701B1 KR 1019990002180 A KR1019990002180 A KR 1019990002180A KR 19990002180 A KR19990002180 A KR 19990002180A KR 100304701 B1 KR100304701 B1 KR 100304701B1
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- metal layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 229910052782 aluminium Inorganic materials 0.000 title claims abstract description 22
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 title claims abstract description 22
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 21
- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 21
- 239000010937 tungsten Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010410 layer Substances 0.000 claims abstract description 139
- 229910052751 metal Inorganic materials 0.000 claims abstract description 130
- 239000002184 metal Substances 0.000 claims abstract description 130
- 230000004888 barrier function Effects 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
Abstract
본 발명의 반도체 장치는 반도체 기판 상에 하부 금속층이 형성되어 있고, 상기 하부 금속층 상에 비아홀을 갖는 층간 절연막이 형성되어 있다. 상기 비아홀의 바닥 및 내벽에 Ti막과 TiN막의 이중막으로 제1 배리어 금속층이 형성되어 있고, 상기 제1 배리어 금속층의 바닥 및 내벽에 텅스텐막을 이용하여 제2 배리어 금속층이 형성되어 있다. 상기 제2 배리어 금속층의 내부에 알루미늄막을 이용하여 상기 비아홀을 매립하는 플러그가 형성되어 있고, 상기 플러그, 제1 배리어 금속층 및 제2 배리어 금속층 상에 상부 금속층이 형성되어 있다. 이러한 본 발명의 반도체 장치는 플러그, 제2 배리어 금속층 및 제2 배리어 금속층으로 비아 콘택을 구성하여 비아 콘택 저항값을 낮게 가져갈 수 있다. 그리고, 비아홀의 종횡비가 커져도 비아 콘택 저항값이 낮아 반도체 소자의 성능 저하를 막을 수 있다.In the semiconductor device of the present invention, a lower metal layer is formed on a semiconductor substrate, and an interlayer insulating film having via holes is formed on the lower metal layer. A first barrier metal layer is formed on the bottom and the inner wall of the via hole as a double layer of the Ti film and the TiN film, and a second barrier metal layer is formed on the bottom and the inner wall of the first barrier metal layer by using a tungsten film. A plug is formed in the second barrier metal layer to fill the via hole using an aluminum film, and an upper metal layer is formed on the plug, the first barrier metal layer, and the second barrier metal layer. In the semiconductor device of the present invention, a via contact may be formed of a plug, a second barrier metal layer, and a second barrier metal layer to reduce the via contact resistance. Further, even if the aspect ratio of the via hole is increased, the via contact resistance value is low, thereby preventing the performance of the semiconductor device.
Description
본 발명은 반도체 장치 및 그 제조방법에 관한 것으로, 특히 알루미늄으로 비아홀이 매립된 반도체 장치 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a via hole filled with aluminum and a method for manufacturing the same.
일반적으로, 고집적화된 반도체 장치일수로 금속층은 얇아진다. 이로 인해 하부 금속층과 상부 금속층을 비아홀을 이용하여 연결하는 비아 콘택은 반도체 장치의 성능을 결정하는 중요한 요인이 된다. 그리고, 고집적 반도체 장치에서 임계크기가 작은 금속층과 비아홀간의 오버랩 마진은 적어지므로 사진공정에서 미스얼라인 관리가 중요하다. 또한, 비아홀의 종횡비가 증가함에 따라 비아 콘택의 저항값이 증가하여 반도체 장치의 특성에 악영향을 미치게 된다. 여기서, 종래기술에 의한 비아 콘택을 갖는 반도체 장치를 설명한다.In general, the more integrated semiconductor devices, the thinner the metal layer. As a result, a via contact connecting the lower metal layer and the upper metal layer using via holes becomes an important factor in determining the performance of the semiconductor device. In the highly integrated semiconductor device, since overlap margin between the metal layer and the via hole having a small critical size decreases, misalignment management is important in the photographing process. In addition, as the aspect ratio of the via hole increases, the resistance value of the via contact increases to adversely affect the characteristics of the semiconductor device. Here, a semiconductor device having a via contact according to the prior art will be described.
도 1은 종래 기술에 의한 비아 콘택을 갖는 반도체 장치를 설명하기 위한 단면도이다.1 is a cross-sectional view for describing a semiconductor device having a via contact according to the prior art.
구체적으로, 반도체 기판(1) 상에 알루미늄막으로 하부 금속층(3)이 형성되어 있고, 상기 하부 금속층(3) 상에 캡핑 금속층(5)이 형성되어 있다. 상기 하부 금속층(3) 상에는 비아홀(6)을 갖는 층간 절연막(7)이 형성되어 있으며, 상기 비아홀(6)의 내벽 및 바닥에는 배리어 금속층(9)이 형성되어 있다. 상기 배리어 금속층(9)이 형성된 비아홀(6)의 내부에는 텅스텐 플러그(11)가 형성되어 있다. 결과적으로, 종래의 반도체 장치는 상기 텅스텐 플러그(11) 및 배리어 금속층(9)으로 비아 콘택이 형성되는데, 주로는 텅스텐 플러그(11)로 비아 콘택이 형성된다. 그리고, 상기 텅스텐 플러그(11) 및 배리어 금속층(9) 상에 상부 금속층(13)이 형성되어 있다.Specifically, the lower metal layer 3 is formed of an aluminum film on the semiconductor substrate 1, and the capping metal layer 5 is formed on the lower metal layer 3. An interlayer insulating film 7 having via holes 6 is formed on the lower metal layer 3, and a barrier metal layer 9 is formed on inner walls and bottoms of the via holes 6. A tungsten plug 11 is formed in the via hole 6 in which the barrier metal layer 9 is formed. As a result, in the conventional semiconductor device, via contacts are formed by the tungsten plug 11 and the barrier metal layer 9, mainly via contacts are formed by the tungsten plug 11. The upper metal layer 13 is formed on the tungsten plug 11 and the barrier metal layer 9.
그런데, 상술한 바와 같은 종래의 비아 콘택을 갖는 반도체 장치는 텅스텐 플러그의 높은 비저항값으로 인하여 비아 콘택 저항값이 높고, 더욱이 비아홀의 종횡비가 커짐에 따라 비아 콘택 저항값이 더욱 증가하여 반도체 소자의 성능을 떨어뜨리게 된다.However, in the semiconductor device having the conventional via contact as described above, the via contact resistance is high due to the high resistivity of the tungsten plug, and the via contact resistance is further increased as the aspect ratio of the via hole is increased, thereby increasing the performance of the semiconductor device. Will drop.
따라서, 본 발명이 이루고자 하는 기술적 과제는 비아 콘택 저항값이 낮은 반도체 장치를 제공하는 데 있다.Accordingly, an object of the present invention is to provide a semiconductor device having a low via contact resistance value.
또한, 본 발명의 다른 기술적 과제는 상기 반도체 장치를 제조하는 데 적합한 반도체 장치의 제조방법을 제공하는 데 있다.In addition, another technical problem of the present invention is to provide a method for manufacturing a semiconductor device suitable for manufacturing the semiconductor device.
도 1은 종래의 기술에 의한 반도체 장치를 도시한 단면도이다.1 is a cross-sectional view showing a semiconductor device according to the prior art.
도 2는 본 발명에 의한 반도체 장치를 도시한 단면도이다.2 is a cross-sectional view showing a semiconductor device according to the present invention.
도 3 내지 도 8은 본 발명에 의한 반도체 장치의 제조방법을 도시한 단면도들이다.3 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
상기 기술적 과제를 달성하기 위하여, 본 발명의 반도체 장치는 반도체 기판 상에 하부 금속층이 형성되어 있고, 상기 하부 금속층 상에 비아홀을 갖는 층간 절연막이 형성되어 있다. 상기 비아홀의 바닥 및 내벽에 Ti막과 TiN막의 이중막으로 제1 배리어 금속층이 형성되어 있고, 상기 제1 배리어 금속층의 바닥 및 내벽에 텅스텐막을 이용하여 제2 배리어 금속층이 형성되어 있다. 상기 제2 배리어 금속층의 내부에 알루미늄막을 이용하여 상기 비아홀을 매립하는 플러그가 형성되어 있고, 상기 플러그, 제1 배리어 금속층 및 제2 배리어 금속층 상에 상부 금속층이 형성되어 있다. 이러한 본 발명의 반도체 장치는 플러그, 제2 배리어 금속층 및 제1 배리어 금속층으로 비아 콘택을 구성하여 비아 콘택 저항값을 낮게 가져갈 수 있다. 그리고, 비아홀의 종횡비가 커져도 비아 콘택 저항값이 낮아 반도체 소자의 성능 저하를 막을 수 있다.In order to achieve the above technical problem, in the semiconductor device of the present invention, a lower metal layer is formed on a semiconductor substrate, and an interlayer insulating film having via holes is formed on the lower metal layer. A first barrier metal layer is formed on the bottom and the inner wall of the via hole as a double layer of the Ti film and the TiN film, and a second barrier metal layer is formed on the bottom and the inner wall of the first barrier metal layer by using a tungsten film. A plug is formed in the second barrier metal layer to fill the via hole using an aluminum film, and an upper metal layer is formed on the plug, the first barrier metal layer, and the second barrier metal layer. In the semiconductor device of the present invention, a via contact may be formed of a plug, a second barrier metal layer, and a first barrier metal layer to reduce the via contact resistance. Further, even if the aspect ratio of the via hole is increased, the via contact resistance value is low, thereby preventing the performance of the semiconductor device.
또한, 본 발명의 다른 기술적 과제를 달성하기 위하여, 본 발명은 반도체 기판 상에 하부 금속층을 형성한 후 상기 하부 금속층 상에 비아홀을 갖는 층간 절연막을 형성하는 단계를 포함한다. 이어서, 상기 비아홀을 갖는 반도체 기판의 전면에 제1 배리어 금속층 및 제2 배리어 금속층을 순차적으로 형성한다. 상기 제1 배리어 금속층은 Ti막과 TiN막의 이중막으로 형성하고, 상기 제2 배리어 금속층은 텅스텐막으로 형성한다. 다음에, 상기 제2 배리어 금속층 상에 알루미늄막을 이용하여 상기 비아홀을 매립하도록 플러그를 형성한다. 상기 플러그는 매립특성이 좋은 화학기상증착법을 이용한다. 다음에, 상기 플러그, 제1 배리어 금속층 및 제2 배리어 금속층 상에 상부 금속층을 형성한다. 이때, 상기 상부 금속층의 형성을 위한 사진공정의 미스 얼라인이 발생하더라도 상기 텅스텐막으로 이루어진 제2 배리어 금속층으로 인하여 상기 플러그가 손상되지 않는다.In addition, in order to achieve another technical problem of the present invention, the present invention includes forming a lower metal layer on the semiconductor substrate and then forming an interlayer insulating film having via holes on the lower metal layer. Subsequently, a first barrier metal layer and a second barrier metal layer are sequentially formed on the entire surface of the semiconductor substrate having the via holes. The first barrier metal layer is formed of a double film of a Ti film and a TiN film, and the second barrier metal layer is formed of a tungsten film. Next, a plug is formed on the second barrier metal layer so as to fill the via hole using an aluminum film. The plug uses a chemical vapor deposition method having good buried characteristics. Next, an upper metal layer is formed on the plug, the first barrier metal layer, and the second barrier metal layer. At this time, even if a misalignment of the photo process for forming the upper metal layer occurs, the plug is not damaged due to the second barrier metal layer made of the tungsten film.
이하, 첨부 도면을 참조하여 본 발명의 실시예를 상세히 설명한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 의한 비아 콘택을 갖는 반도체 장치를 설명하기 위한 단면도이다.2 is a cross-sectional view for describing a semiconductor device having a via contact according to the present invention.
구체적으로, 반도체 기판(31) 상에 알루미늄막으로 하부 금속층(33)이 형성되어 있고, 상기 하부 금속층 상에 캡핑 금속층(35)이 형성되어 있다. 상기 하부 금속층을 노출하도록 비아홀(36)을 갖는 층간절연막(37)이 형성되어 있으며, 상기 비아홀의 내벽 및 바닥에는 제1 배리어 금속층(39)이 형성되어 있다. 상기 제1 배리어 금속층(39)은 Ti막과 TiN막의 이중막으로 구성한다.Specifically, the lower metal layer 33 is formed of an aluminum film on the semiconductor substrate 31, and the capping metal layer 35 is formed on the lower metal layer. An interlayer insulating layer 37 having a via hole 36 is formed to expose the lower metal layer, and a first barrier metal layer 39 is formed on inner walls and bottoms of the via hole. The first barrier metal layer 39 is composed of a double film of a Ti film and a TiN film.
상기 제1 배리어 금속층(39)의 내벽 및 바닥에는 텅스텐막으로 제2 배리어 금속층(41)이 형성되어 있다. 상기 제2 배리어 금속층(41)의 내부에 형성되고, 상기 비아홀(36)을 매립하도록 플러그(43)가 형성되어 있다. 상기 플러그(43)는 비아홀(36)을 잘 매립할 수 있도록 화학기상증착법(chemical vapor deposition)을 이용하여 알루미늄막으로 형성한다. 이렇게 되면, 제1 배리어 금속층(39), 제2 배리어 금속층(41) 및 플러그(43)로 비아 콘택이 형성되는데, 주로 플러그로 비아 콘택이 형성된다. 그리고, 상기 제1 배리어 금속층(39), 제2 배리어 금속층(41) 및 플러그(43) 상에 알루미늄막으로 상부 금속층(45)이 형성되어 있다.A second barrier metal layer 41 is formed on the inner wall and the bottom of the first barrier metal layer 39 using a tungsten film. A plug 43 is formed in the second barrier metal layer 41 and fills the via hole 36. The plug 43 is formed of an aluminum film by chemical vapor deposition so that the via hole 36 may be well buried. In this case, a via contact is formed by the first barrier metal layer 39, the second barrier metal layer 41, and the plug 43. The via contact is mainly formed by the plug. The upper metal layer 45 is formed of an aluminum film on the first barrier metal layer 39, the second barrier metal layer 41, and the plug 43.
이러한 비아 콘택을 갖는 반도체 장치는 종래의 텅스텐 플러그의 비저항이낮아 비아 콘택 저항값이 낮게 된다. 즉, 본 발명의 알루미늄 플러그는 비저항이 2.8정도인데, 종래의 텅스텐 플러그의 비저항은 5.5 정도로써, 본 발명의 반도체 장치가 비아 콘택 저항값이 낮게 된다. 그리고, 본 발명은 비아홀의 종횡비가 커져도 비아 콘택 저항값이 낮아 반도체 소자의 성능 저하를 막을 수 있다. 더욱이, 상기 상부 금속층(45)을 형성하기 위한 사진식각공정시 미스 얼라인이 발생하더라도 상부 금속층(45)이 알루미늄층이고 상기 제2 배리어 금속층(41)이 텅스텐층이기 때문에 상기 알루미늄막으로 구성된 상기 플러그(43)가 손상되지 않는다.A semiconductor device having such a via contact has a low resistivity of a conventional tungsten plug, resulting in a low via contact resistance. That is, the aluminum plug of the present invention has a specific resistance of about 2.8, and the conventional tungsten plug has a specific resistance of about 5.5, so that the semiconductor device of the present invention has a low via contact resistance. According to the present invention, even if the aspect ratio of the via hole increases, the via contact resistance value is low, thereby preventing the performance of the semiconductor device. Furthermore, even if a misalignment occurs in the photolithography process for forming the upper metal layer 45, the upper metal layer 45 is an aluminum layer and the second barrier metal layer 41 is a tungsten layer. The plug 43 is not damaged.
도 3 내지 도 8은 본 발명에 의한 반도체 장치의 제조방법을 도시한 단면도들이다.3 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 3을 참조하면, 반도체 기판(31), 예컨대 실리콘 기판 상에 하부 금속층(33)을 형성한다. 상기 하부 금속층(33)은 알루미늄막을 스퍼터링 방법 또는 화학기상증착법을 이용하여 1000∼7000Å의 두께로 형성한다. 이어서, 상기 하부 금속층(33) 상에 캡핑 금속층(35)을 형성한다. 상기 캡핑 금속층(35)은 Ti막과 TiN막의 이중막으로 형성한다. 다음에, 상기 캡핑 금속층(35) 상에 층간 절연막(37)을 형성한다.Referring to FIG. 3, a lower metal layer 33 is formed on a semiconductor substrate 31, for example, a silicon substrate. The lower metal layer 33 forms an aluminum film in a thickness of 1000 to 7000 kPa using a sputtering method or a chemical vapor deposition method. Subsequently, a capping metal layer 35 is formed on the lower metal layer 33. The capping metal layer 35 is formed of a double film of a Ti film and a TiN film. Next, an interlayer insulating film 37 is formed on the capping metal layer 35.
도 4를 참조하면, 사진식각공정을 이용하여 상기 층간 절연막(37) 및 캡핑 금속층(35)을 패터닝하여 상기 하부 금속층(33)을 노출하는 비아홀(36)을 형성한다. 상기 비아홀(36)은 상기 하부 금속층(33)과 후의 상부 금속층을 연결하는 역할을 한다.Referring to FIG. 4, a via hole 36 exposing the lower metal layer 33 is formed by patterning the interlayer insulating layer 37 and the capping metal layer 35 using a photolithography process. The via hole 36 serves to connect the lower metal layer 33 and the later upper metal layer.
도 5를 참조하면, 상기 비아홀(36)이 형성된 반도체 기판(31)의 전면에 제1배리어 금속층(39)을 형성한다. 상기 제1 배리어 금속층(39)은 Ti막과 TiN막의 이중막으로 형성한다. 이어서, 상기 제1 배리어 금속층(39)이 형성된 반도체 기판(31)의 전면에 제2 배리어 금속층(41)을 형성한다. 제2 배리어 금속층(41)은 알루미늄막과 식각선택비가 우수한 텅스텐막을 500∼1500Å의 두께로 형성한다.Referring to FIG. 5, the first barrier metal layer 39 is formed on the entire surface of the semiconductor substrate 31 on which the via holes 36 are formed. The first barrier metal layer 39 is formed of a double film of a Ti film and a TiN film. Subsequently, a second barrier metal layer 41 is formed on the entire surface of the semiconductor substrate 31 on which the first barrier metal layer 39 is formed. The second barrier metal layer 41 forms an aluminum film and a tungsten film excellent in etching selectivity with a thickness of 500-1500 kPa.
도 6을 참조하면, 상기 제1 배리어 금속층(39) 및 제2 배리어 금속층(41)이 형성된 반도체 기판(31)의 전면에 상기 비아홀을 매립하도록 제1 금속층(42)을 형성한다. 상기 제1 금속층(42)은 알루미늄막을 매립특성이 좋은 화학기상증착법(CVD)으로 형성한다.Referring to FIG. 6, a first metal layer 42 is formed to fill the via hole in the entire surface of the semiconductor substrate 31 on which the first barrier metal layer 39 and the second barrier metal layer 41 are formed. The first metal layer 42 forms an aluminum film by chemical vapor deposition (CVD) with good buried characteristics.
도 7을 참조하면, 상기 제1 금속층(42), 제1 배리어 금속층(39) 및 제2 배리어 금속층(41)을 상기 층간 절연막(37)이 노출될 때까지 전면식각하여 상기 비아홀(36)에 매립되는 플러그(43)를 형성한다. 상기 전면 식각은 에치백(etch back) 또는 화학기계적연마(chemical mechanical polishing )방법을 이용하여 수행한다. 이렇게 되면, 상기 비아홀(36)의 내벽 및 바닥에 제1 배리어 금속층(39)이 형성되며, 상기 제1 배리어 금속층(39)의 내벽 및 바닥에 제2 배리어 금속층(41)이 형성된다.Referring to FIG. 7, the first metal layer 42, the first barrier metal layer 39, and the second barrier metal layer 41 are etched on the via hole 36 until the interlayer insulating layer 37 is exposed. A plug 43 to be embedded is formed. The front side etching is performed using an etch back or chemical mechanical polishing method. In this case, the first barrier metal layer 39 is formed on the inner wall and the bottom of the via hole 36, and the second barrier metal layer 41 is formed on the inner wall and the bottom of the first barrier metal layer 39.
결과적으로, 본 발명의 반도체 장치는 플러그(43), 제1 배리어 금속층(39) 및 제2 배리어 금속층(41)으로 비아 콘택이 형성되는데, 주로는 알루미늄막으로 이루어진 플러그로 비아콘택이 형성된다. 따라서, 본 발명의 반도체 장치는 알루미늄막으로 플러그를 형성하기 때문에 종래의 텅스텐 플러그보다 비아 콘택 저항값을 낮출 수 있다. 더욱이, 비아 콘택홀의 종횡비가 커져도 비아 콘택 저항값이 낮아반도체 소자의 성능 저하를 막을 수 있다.As a result, in the semiconductor device of the present invention, a via contact is formed of the plug 43, the first barrier metal layer 39, and the second barrier metal layer 41, and the via contact is formed mainly of a plug made of an aluminum film. Therefore, since the semiconductor device of the present invention forms a plug with an aluminum film, the via contact resistance value can be lower than that of the conventional tungsten plug. Furthermore, even if the aspect ratio of the via contact hole is increased, the via contact resistance value is low, and the performance degradation of the semiconductor device can be prevented.
도 8을 참조하면, 상기 층간 절연막(37), 제1 배리어 금속층(39), 제2 배리어 금속층(41) 및 플러그(43)가 형성된 반도체 기판(31)의 전면에 제2 금속층(44)을 알루미늄막으로 형성한다. 이어서, 사진식각공정을 이용하여 상기 제2 금속층을 패터닝하여 도 2에 도시한 바와 같은 상부 금속층(45)을 형성한다. 여기서, 상기 상부 금속층(45)의 형성을 위한 사진식각공정시 미스 얼라인이 발생하더라도 상기 텅스텐막으로 이루어진 제2 배리어 금속층(43)으로 인하여 상기 알루미늄막의 플러그(43)가 손상되지 않는다.Referring to FIG. 8, a second metal layer 44 is formed on the entire surface of the semiconductor substrate 31 on which the interlayer insulating layer 37, the first barrier metal layer 39, the second barrier metal layer 41, and the plug 43 are formed. It is formed of an aluminum film. Subsequently, the second metal layer is patterned using a photolithography process to form an upper metal layer 45 as shown in FIG. 2. Here, even if a misalignment occurs during the photolithography process for forming the upper metal layer 45, the plug 43 of the aluminum layer is not damaged by the second barrier metal layer 43 made of the tungsten film.
이상, 실시예를 통하여 본 발명을 구체적으로 설명하였지만, 본 발명은 이에 한정되는 것이 아니고, 본 발명의 기술적 사상 내에서 당 분야에서 통상의 지식으로 그 변형이나 개량이 가능하다.As mentioned above, although this invention was demonstrated concretely through the Example, this invention is not limited to this, A deformation | transformation and improvement are possible with the conventional knowledge in the art within the technical idea of this invention.
상술한 바와 같이 본 발명의 반도체 장치는 비아홀의 내벽을 둘러싸도록 텅스텐막으로 배리어 금속층을 형성하고, 상기 배리어 금속층의 내벽을 둘러싸도록 알루미늄막으로 플러그를 형성함으로써 비아콘택을 형성한다. 이렇게 되면, 종래의 텅스텐 플러그 보다 비아 콘택저항을 줄일 수 있고, 상부 금속층 형성을 위한 사진식각공정시 미스얼라인이 되더라도 상기 배리어 금속층으로 인하여 알루미늄 플러그의 식각을 방지할 수 있다.As described above, the semiconductor device of the present invention forms a via contact by forming a barrier metal layer with a tungsten film so as to surround the inner wall of the via hole, and forming a plug with an aluminum film so as to surround the inner wall of the barrier metal layer. In this case, the via contact resistance may be reduced than that of the conventional tungsten plug, and the etching of the aluminum plug may be prevented due to the barrier metal layer even if misaligned during the photolithography process for forming the upper metal layer.
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| JPH08203899A (en) * | 1995-01-30 | 1996-08-09 | Nec Corp | Fabrication of semiconductor device |
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| KR20000051627A (en) | 2000-08-16 |
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