KR100546146B1 - Method for manufacturing via contact of semiconductor device - Google Patents

Method for manufacturing via contact of semiconductor device Download PDF

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Publication number
KR100546146B1
KR100546146B1 KR1019980062011A KR19980062011A KR100546146B1 KR 100546146 B1 KR100546146 B1 KR 100546146B1 KR 1019980062011 A KR1019980062011 A KR 1019980062011A KR 19980062011 A KR19980062011 A KR 19980062011A KR 100546146 B1 KR100546146 B1 KR 100546146B1
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South Korea
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upper wiring
forming
conductive layer
wiring
via hole
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KR1019980062011A
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Korean (ko)
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KR20000045453A (en
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오세중
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Abstract

본 발명은 반도체장치의 비어콘택 제조방법에 관한 것으로서, 비어홀를 매립하는 텅스텐을 형성하고 이를 CMP 한 다음, 상기 비어홀 상측에만 상부배선용 제1도전층을 남기고 후속 공정으로 상부배선용 제2도전층을 형성한 다음, 상부배선용 마스크를 이용하여 사진식각하고 이를 평탄화식각하여 상부배선을 형성함으로써 비어홀과 상부배선의 오정렬(misalign)을 근본적으로 해결되고, EM 등의 신뢰성을 개선할 수 있도록 하는 기술이다.The present invention relates to a method for fabricating a via contact of a semiconductor device, comprising forming tungsten for filling a via hole, CMP, and then leaving a first conductive layer for upper wiring only on the upper side of the via hole, and forming a second conductive layer for upper wiring in a subsequent process. Next, the photo etching using the upper wiring mask and flattening etching to form the upper wiring to fundamentally solve the misalignment of the via hole and the upper wiring, and to improve the reliability of the EM.

Description

반도체소자의 비어 콘택 제조방법Method for manufacturing via contact of semiconductor device

반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 비어홀 ( via hole) 과 상부배선간의 오정렬을 해결하는데 적합한 반도체소자의 비어콘택 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a via contact of a semiconductor device suitable for solving a misalignment between a via hole and an upper wiring.

반도체 제조기술이 개발되고 디자인룰이 줄어(shrink) 들면서 공정자체에 의하여 불량이 발생되고 있다.As semiconductor manufacturing technology is developed and design rules shrink, defects are generated by the process itself.

즉, 비어와 상부배선간의 오버랩 마진은 현재 약 0∼0.02 μm이나, 금속마스크에서의 장비에 의한 오정렬 정도는 약 0.08∼0.15 μm이다.That is, the overlap margin between the via and the upper wiring is currently about 0 to 0.02 μm, but the misalignment degree by the equipment in the metal mask is about 0.08 to 0.15 μm.

이러한 관점에서, 종래기술에 따른 반도체소자의 비어콘택 제조방법을 도 1을 참조하여 설명하면 다음과 같다.In this regard, a method of manufacturing a via contact of a semiconductor device according to the prior art will be described with reference to FIG. 1.

도 1 은 종래기술에 따른 반도체소자의 비어콘택 형성방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a via contact forming method of a semiconductor device according to the prior art.

도 1 에 도시된 바와같이, 상기 하부배선(1)상에 IMD산화막(2)을 증착하고 IMD산화막(2)을 CMP 공정으로 평탄화시킨다.As shown in FIG. 1, an IMD oxide film 2 is deposited on the lower interconnection 1, and the IMD oxide film 2 is planarized by a CMP process.

이어서, 비어홀을 형성하기 위한 노광마스크를 이용한 사진식각공정으로 상기 IMD층(2)을 식각하여 상기 하부배선(11)을 노출시키는 비어홀(2a)을 형성한다.Subsequently, the IMD layer 2 is etched by a photolithography process using an exposure mask for forming a via hole, thereby forming a via hole 2a exposing the lower wiring 11.

그 다음, 상기 비어홀(2a)을 매립하는 텅스텐을 전체표면상부에 증착하고, 이를 CMP 하여 텅스텐 플러그(3)를 형성한다.Then, tungsten, which fills the via hole 2a, is deposited on the entire surface, and CMP is formed to form a tungsten plug 3.

그리고, 전체구조상부에 상부배선용 도전층(미도시)을 형성하고 이를 패터닝하여 상부배선(4)을 형성한다.Then, the upper wiring conductive layer (not shown) is formed on the entire structure and patterned to form the upper wiring 4.

이때, 상기 상부배선(4)은 상부배선을 형성하기 위한 노광마스크를 이용한 사진식각공정으로 상기 상부배선용 도전층을 패터닝하여 형성한 것이다.At this time, the upper wiring 4 is formed by patterning the conductive layer for the upper wiring by a photolithography process using an exposure mask for forming the upper wiring.

상기한 바와 같이, 종래기술에 따른 반도체소자의 비어콘택 형성방법에 있어서는 다음과 같은 문제점이 있다.As described above, the via contact forming method of the semiconductor device according to the prior art has the following problems.

도 1 에서와 같이, 현재의 기술에서는 하부배선 상에 있는 비어홀(2a) 상의 배선은 항상 0.06 ∼ 0.13 ㎛ 정도가 비어홀(2a)을 벗어나서 정의되고 있는 실정이다.As shown in FIG. 1, in the current technology, the wiring on the via hole 2a on the lower wiring is always defined as about 0.06 to 0.13 μm outside the via hole 2a.

즉, 하부배선을 정의한 도 1 에서와 같이, 비어홀의 저항 값이 스펙(spec)을 맞추지 못하며, 오정렬(miss align)이 심해지면 비어홀 ( via hole ) 이 불량하게 되는 경우가 흔히 발생되고 있다.That is, as shown in FIG. 1 in which the lower wiring is defined, the resistance value of the via hole does not meet the spec, and when the misalignment becomes severe, the via hole is often poor.

따라서, 이와 같은 종래의 구조는 비어콘택의 신뢰성(reliability)을 저하시키는 문제점이 있다.Therefore, this conventional structure has a problem of lowering the reliability of the via contact.

이에 본 발명은 상기 종래기술의 문제점을 해결하기 위하여 안출한 것으로서, 비어홀과 상부배선과의 오정렬 문제를 방지하고 그에 따른 반도체소자의 수율, 신뢰성을 향상시킬 수 있도록 하는 반도체소자의 비어콘택 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the problems of the prior art, and provides a method for manufacturing a via contact of a semiconductor device to prevent the misalignment of the via hole and the upper wiring, thereby improving the yield and reliability of the semiconductor device. The purpose is to provide.

상기 목적을 달성하기 위해 본 발명에 따른 반도체소자의 비어콘택 제조방법은,In order to achieve the above object, a via contact manufacturing method of a semiconductor device according to the present invention includes

하부배선 상에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the lower wiring;

비어홀용 노광마스크를 이용한 사진식각공장으로 상기 제1층간절연막을 식각하여 상기 하부배선을 노출시키는 비어홀을 형성하는 공정과,Forming a via hole for exposing the lower wiring by etching the first interlayer insulating film using a photolithography factory using an exposure mask for via holes;

상기 비어홀을 매립하는 전체표면상부에 텅스텐을 형성하고 상기 제1층간절연막을 노출시키도록 CMP 하는 공정과,Forming a tungsten on the entire surface of the via hole and CMP to expose the first interlayer insulating film;

전체표면상부에 상부배선용 제1도전층을 형성하는 공정과,Forming a first conductive layer for upper wiring on the entire surface;

비어홀용 노광마스크를 이용한 사진식각공정으로 상기 상부배선용 제1도전층을 식각하여 상기 비어홀 상측에만 남기는 공정과,Etching the first conductive layer for upper wiring by a photolithography process using an exposure mask for via holes, and leaving only the upper side of the via holes;

전체표면상부에 상부배선용 제2도전층을 형성하는 공정과,Forming a second conductive layer for upper wiring on the entire surface;

상부배선용 노광마스크를 이용한 사진식각공정으로 상기 상부배선용 제2도전층을 패터닝하는 공정과,Patterning the second conductive layer for upper wiring by a photolithography process using an exposure mask for upper wiring;

전체표면상부에 제2층간절연막을 형성하고 상기 상부배선용 제1도전층을 노출시키도록 CMP 하는 공정을 포함하는 것과,Forming a second interlayer insulating film over the entire surface and performing a CMP to expose the first conductive layer for upper wiring;

상기 비어홀 형성공정 및 상부배선용 제2도전층의 패터닝공정은 포지티브 감광막을 사용하는 것과,The via hole forming process and the patterning process of the second conductive layer for upper wiring use a positive photosensitive film,

상기 상부배선용 제1도전층의 패터닝공정은 네거티브 감광막을 사용하는 것과,The patterning process of the first conductive layer for the upper wiring is to use a negative photosensitive film,

상기 제1 및 제2 층간절연막은 산화막을 사용하는 것을 제1특징으로 한다.The first and second interlayer insulating films have a first feature of using an oxide film.

또한, 이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 비어콘택 제조방법은,In addition, the via contact manufacturing method of the semiconductor device according to the present invention in order to achieve the above object,

하부배선 상에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the lower wiring;

비어홀용 노광마스크를 이용한 사진식각공정으로 상기 제1층간절연막을 식각하여 상기 하부배선을 노출시키는 비어홀을 형성하는 공정과,Forming a via hole for exposing the lower wiring by etching the first interlayer insulating film by a photolithography process using an exposure mask for via holes;

상기 비어홀을 매립하는 전체표면상부에 텅스텐을 형성하고 상기 제1층간절연막을 노출시키도록 CMP 하여 텅스텐 플러그를 형성하는 공정과,Forming a tungsten plug by forming tungsten on the entire surface of the via hole and CMP to expose the first interlayer insulating film;

상기 텅스텐 플러그를 마스크로 하여 상기 제1층간산화막을 전면식각하여 소정두께 식각하되, 상부배선의 두께만큼을 타겟으로 하여 실시하는 공정과,Etching the entire surface of the first interlayer oxide layer using the tungsten plug as a mask to etch a predetermined thickness, and performing the target by the thickness of the upper wiring;

전체표면상부에 상부배선용 도전층을 형성하는 공정과,Forming a conductive layer for upper wiring on the entire surface;

상부배선용 노광마스크를 이용한 사진식각공정으로 상기 상부배선용 도전층을 식각하여 패터닝하는 공정과,Etching and patterning the conductive layer for upper wiring by a photolithography process using an exposure mask for upper wiring;

전체표면상부에 제2층간산화막을 증착하고 상기 텅스텐 플러그를 노출시키는 CMP 공정으로 텅스텐 플러그와 상부배선용 도전층으로 형성된 상부배선을 형성하는 공정을 포함하는 것과,A CMP process of depositing a second interlayer oxide film on the entire surface and exposing the tungsten plug, including forming a top wiring formed of a tungsten plug and an upper conductive layer;

상기 제1층간절연막은 종래보다 상부배선의 두께만큼 더 두껍게 형성하는 형성하는 것을 제2 특징으로 한다.The first interlayer dielectric film may be formed to be thicker by the thickness of the upper wiring than in the prior art.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2 내지 도 7 는 본 발명의 제1실시예에 따른 반도체소자의 비어콘택 제조 공정 단면도이다.2 to 7 are cross-sectional views illustrating a via contact manufacturing process of the semiconductor device according to the first embodiment of the present invention.

도 2를 참조하면, 실리콘기판(미도시) 상에 하부배선용 도전층(미도시)을 증착하고 이를 패터닝하여 하부배선(11)을 형성한다.Referring to FIG. 2, a lower wiring 11 is formed by depositing and patterning a lower conductive layer (not shown) on a silicon substrate (not shown).

도 3을 참조하면, 상기 하부배선(11) 상에 제1층간산화막(12)을 증착하고 제1층간산화막(12)을 CMP 공정으로 평탄화시킨다.Referring to FIG. 3, a first interlayer oxide layer 12 is deposited on the lower interconnection 11, and the first interlayer oxide layer 12 is planarized by a CMP process.

그 다음, 상기 제1층간산화막(12)에 비어홀(12a)을 형성한다. 이때, 상기 비어홀(12a)은 비어홀을 형성하기 위한 노광마스크를 이용한 사진식각공정으로 상기 제1층간산화막(12)을 식각하여 형성한 것이다.Next, a via hole 12a is formed in the first interlayer oxide film 12. In this case, the via hole 12a is formed by etching the first interlayer oxide layer 12 by a photolithography process using an exposure mask for forming the via hole.

도 4를 참조하면, 상기 비어홀(12a)을 매립하는 텅스텐(미도시)을 전체표면상부에 형성하고 이를 평탄화식각하여 텅스텐 플러그(13)을 형성한다. 이때, 상기 평탄화식각공정은 CMP 공정으로 실시한다.Referring to FIG. 4, a tungsten (not shown) filling the via hole 12a is formed on the entire surface and flattened to form a tungsten plug 13. In this case, the planarization etching process is performed by a CMP process.

그 다음, 전체표면상부에 상부배선용 제1도전층(14)을 형성하고 그 상부에 감광막패턴(15)을 형성한다. 이때, 상기 감광막패턴(15)은 비아홀 마스크를 이용한 노광 및 현상 공정으로 형성한 것으로, 상기 비아홀(12a)을 형성하기 위한 사진식각공정시 사용된 감광막과 반대타입의 감광막을 이용하여 형성함으로써 비아홀(12a) 상측에만 형성한 것이다.Then, the first conductive layer 14 for upper wiring is formed on the entire surface, and the photosensitive film pattern 15 is formed on the upper surface. In this case, the photoresist pattern 15 is formed by an exposure and development process using a via hole mask, and is formed by using a photoresist film of a type opposite to that of the photoresist film used in the photolithography process for forming the via hole 12a. 12a) It is formed only on the upper side.

도 5를 참조하면, 상기 감광막패턴(15)을 마스크로 하여 상기 상부배선용 제1도전층(14)을 식각하여 비아홀(12a) 상부에만 남긴다.Referring to FIG. 5, the first conductive layer 14 for upper wiring is etched using the photoresist pattern 15 as a mask, leaving only the upper portion of the via hole 12a.

그 다음, 전체표면상부에 상부배선용 제2도전층(16)을 형성한다.Then, the second conductive layer 16 for upper wiring is formed on the entire surface.

도 6을 참조하면, 상부배선용 노광마스크(미도시)를 이용한 사진식각공정으로 상기 상부배선용 제2도전층(16)을 식각하여 패터닝하되, 상기 제1도전층(14)의 측벽에 배선 스페이서(16a)를 형성한다.Referring to FIG. 6, the second conductive layer 16 for the upper wiring is etched and patterned by a photolithography process using an exposure mask (not shown) for the upper wiring, and the wiring spacers are formed on the sidewalls of the first conductive layer 14. 16a).

이때, 상기 상부배선용 제2도전층(16)은 상기 비어홀(12a)과 오정렬되어 구비되었으나, 상기 상부배선용 제1도전층(14)과 중첩되어 구비된다.In this case, the upper conductive second conductive layer 16 is misaligned with the via hole 12a, but overlaps with the upper conductive first conductive layer 14.

도 7을 참조하면, 전체표면상부에 제2층간산화막(17)을 증착하고, 상기 제2층간산화막(17)을 CMP 하여 상기 상부배선용 제1도전층(14)을 노출시키도록 평탄화시킴으로써 상기 상부배선용 제1도전층(14), 상부배선용 제2도전층(16) 및 배선 스페이서(16a)로 구비되는 상부배선을 형성한다.Referring to FIG. 7, the second interlayer oxide layer 17 is deposited on the entire surface, and the upper layer is planarized to expose the first conductive layer 14 for upper wiring by CMPing the second interlayer oxide layer 17. An upper wiring formed of the first conductive layer 14 for wiring, the second conductive layer 16 for upper wiring, and the wiring spacer 16a is formed.

도 8 내지 14 는 본 발명의 제2실시예에 따른 반도체소자의 비어콘택 제조공정 단면도이다.8 to 14 are cross-sectional views illustrating a via contact manufacturing process of a semiconductor device in accordance with a second embodiment of the present invention.

도 8을 참조하면, 실리콘기판(미도시) 상에 하부배선용 도전층(미도시)을 증착하고 이를 패터닝하여 하부배선(21)을 형성한다.Referring to FIG. 8, a lower wiring conductive layer (not shown) is deposited on a silicon substrate (not shown) and patterned to form a lower wiring 21.

그 다음, 상기 하부배선(21)상에 제1층간산화막(22)을 증착하고 제1층간산화막(22)을 CMP 공정에 의해 평탄화시킨다.Next, a first interlayer oxide film 22 is deposited on the lower interconnection 21, and the first interlayer oxide film 22 is planarized by a CMP process.

이때, 상기 제1층간산화막(22)은 종래기술에서 사용되는 비아홀(도 1의 2a)의 에스펙트비인 2.2 : 1 보다 높은 3 : 1 정도의 에스펙트비를 가질 수 있도록 상부배선의 두께만큼 두께를 증가시켜 형성한 것이다.At this time, the first interlayer oxide film 22 is thick by the thickness of the upper wiring so as to have an aspect ratio of about 3: 1 higher than the ratio of 2.2: 1, which is the aspect ratio of the via hole (2a of FIG. 1) used in the prior art. It is formed by increasing.

도 9를 참조하면, 상기 제1층간산화막(22)에 비어홀(22a)을 형성한다. 이때, 상기 비어홀(22a)은 비어홀을 형성하기 위한 노광마스크를 이용한 사진식각공정으로 상기 제1층간산화막(22)을 식각하여 형성한 것이다.Referring to FIG. 9, a via hole 22a is formed in the first interlayer oxide film 22. In this case, the via hole 22a is formed by etching the first interlayer oxide layer 22 by a photolithography process using an exposure mask for forming the via hole.

그 다음, 상기 비어홀(22a)을 매립하는 텅스턴(미도시)을 전체표면상부에 증착하고 이를 평탄화식각하여 텅스텐 플러그(23)를 형성한다. 이때, 상기 텅스텐 증착공정은 에스펙트비가 4 : 1 의 비어홀도 매립할 수 있을 정도의 갭매립(gap fill) 능력이 우수하므로 상기 비어홀(22a)을 완전히 매립하며, 상기 평탄화식각공정은 CMP 공정으로 실시한 것이다.Next, a tungsten (not shown) filling the via hole 22a is deposited on the entire surface and planarized to form a tungsten plug 23. In this case, the tungsten deposition process is excellent enough to fill the via hole of the aspect ratio 4: 1, so the via hole 22a is completely filled, and the planarization etching process is a CMP process. It was done.

도 10을 참조하면, 상기 텅스텐 플러그(23)를 마스크로 하여 상기 제1층간산화막(22)을 전면식각하여 소정두께 식각하되, 상부배선의 두께만큼을 타겟으로 하여 실시한다.Referring to FIG. 10, the first interlayer oxide layer 22 is etched by etching the entire surface of the first interlayer oxide layer 22 using the tungsten plug 23 as a mask, and the target layer is formed using the thickness of the upper wiring.

이때, 상기 제1층간산화막(22)의 식각공정은 산화막과 텅스텐의 식각선택비차이를 이용하여 실시한 것으로, 텅스텐 플러그(23)가 제1층간산화막(22)위로 올라와 있는 모양을 하게 한다.In this case, the etching process of the first interlayer oxide film 22 is performed by using an etching selectivity difference between the oxide film and tungsten, and the tungsten plug 23 is formed on the first interlayer oxide film 22.

도 11을 참조하면, 전체표면상부에 상부배선용 도전층(24)을 형성한다.Referring to FIG. 11, an upper wiring conductive layer 24 is formed over the entire surface.

도 12를 참조하면, 상부배선용 노광마스크를 이용한 사진식각공정으로 상기 상부배선용 도전층(24)을 식각하여 패터닝함으로써 상부배선 영역에 상기 상부배선용 도전층(24)을 남기되, 상기 노출된 텅스텐 플러그(23)의 측벽에도 스페이서 형태의 상부배선용 도전층(24)이 남게 된다.Referring to FIG. 12, the upper wiring conductive layer 24 is left in the upper wiring region by etching and patterning the upper wiring conductive layer 24 by a photolithography process using an exposure mask for upper wiring, wherein the exposed tungsten plug An upper conductive layer 24 for spacers also remains on the side wall of the spacer 23.

도 13 및 도 14를 참조하면, 전체표면상부에 제2층간산화막(25)을 증착하고 상기 텅스텐 플러그(23)를 노출시키는 CMP 공정으로 텅스텐 플러그(23)와 상부배선용 도전층(24)으로 형성된 상부배선을 형성하는 동시에 평탄화된 제2층간산화막(25a)을 형성한다.13 and 14, a CMP process of depositing a second interlayer oxide film 25 on the entire surface and exposing the tungsten plug 23 is formed of a tungsten plug 23 and an upper conductive layer 24. While forming the upper wiring, the planarized second interlayer oxide film 25a is formed.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 비어콘택 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the via contact forming method of the semiconductor device according to the present invention has the following effects.

본 발명에 있어서는 비어홀과 상부배선의 오정렬 문제가 제거되므로써 안정화된 비어홀의 저항값을 얻을 수 있어 비어홀의 저항 증가에 의한 RC 딜레이(delay)에 의한 수율 저하를 방지할 수 있으며 EM(electro migration) 특성을 향상시킬 수 있 반도체소자의 신뢰성을 개선시킬 수 있다.In the present invention, since the problem of misalignment between the via hole and the upper wiring is eliminated, the resistance value of the stabilized via hole can be obtained, thereby preventing a decrease in yield due to the RC delay due to the increase in the resistance of the via hole, and the EM (electro migration) characteristics. It is possible to improve the reliability of the semiconductor device.

도 1 는 종래기술에 따른 반도체소자의 비어콘택 제조공정 단면도이다.1 is a cross-sectional view of a via contact manufacturing process of a semiconductor device according to the prior art.

도 2 내지 도 7 는 본 발명의 제1실시예에 따른 반도체소자의 비어콘택 제조공정 단면도이다.2 to 7 are cross-sectional views illustrating a via contact manufacturing process of the semiconductor device according to the first embodiment of the present invention.

도 8 내지 14 는 본 발명의 제2실시예에 따른 반도체소자의 비어콘택 제조공정 단면도이다.8 to 14 are cross-sectional views illustrating a via contact manufacturing process of a semiconductor device in accordance with a second embodiment of the present invention.

＜ 도면의주요부분에대한부호의설명＞<Description of Symbols for Major Parts of Drawings>

11 : 하부배선 12 : 제1층간절연막11 lower wiring 12 first interlayer insulating film

12a : 비어콘택 13 : 텅스텐플러그12a: Beer contact 13: Tungsten plug

14 : 제1상부배선 15 : 감광막패턴14: first upper wiring 15: photosensitive film pattern

16 : 제2상부배선 16a : 배선스페이서16: second upper wiring 16 a: wiring spacer

17 : 제2층간절연막17: second interlayer insulating film

Claims (6)

하부배선 상에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the lower wiring; 비어홀용 노광마스크를 이용한 사진식각공정으로 상기 제1층간절연막을 식각하여 상기 하부배선을 노출시키는 비어홀을 형성하는 공정과,Forming a via hole for exposing the lower wiring by etching the first interlayer insulating film by a photolithography process using an exposure mask for via holes; 상기 비어홀을 매립하는 전체표면상부에 텅스텐을 형성하고 상기 제1층간절연막을 노출시키도록 CMP 하는 공정과,Forming a tungsten on the entire surface of the via hole and CMP to expose the first interlayer insulating film; 전체표면상부에 상부배선용 제1도전층을 형성하는 공정과,Forming a first conductive layer for upper wiring on the entire surface; 비어홀용 노광마스크를 이용한 사진식각공정으로 상기 상부배선용 제1도전층을 식각하여 상기 비어홀 상측에만 남기는 공정과,Etching the first conductive layer for upper wiring by a photolithography process using an exposure mask for via holes, and leaving only the upper side of the via holes; 전체표면상부에 상부배선용 제2도전층을 형성하는 공정과,Forming a second conductive layer for upper wiring on the entire surface; 상부배선용 노광마스크를 이용한 사진식각공정으로 상기 상부배선용 제2도전층을 패터닝하는 공정과,Patterning the second conductive layer for upper wiring by a photolithography process using an exposure mask for upper wiring; 전체표면상부에 제2층간절연막을 형성하고 상기 상부배선용 제1도전층을 노출시키도록 CMP 하는 공정을 포함하는 것을 특징으로 하는 반도체소자의 비어콘택 제조방법.And forming a second interlayer insulating film over the entire surface and performing CMP to expose the first conductive layer for upper wiring. 제1항에 있어서,The method of claim 1, 상기 비어홀 형성공정 및 상부배선용 제2도전층의 패터닝공정은 포지티브 감광막을 사용하는 것을 특징으로하는 반도체소자의 비어콘택 제조방법.The via hole forming process and the patterning process of the second conductive layer for upper wiring use a positive photoresist film manufacturing method of the via contact of the semiconductor device. 제1항에 있어서,The method of claim 1, 상기 상부배선용 제1도전층의 패터닝공정은 네거티브 감광막을 사용하는 것을 특징으로하는 반도체소자의 비어콘택 제조방법.The patterning process of the first conductive layer for the upper wiring is a via contact manufacturing method of a semiconductor device, characterized in that using a negative photosensitive film. 제1항에 있어서,The method of claim 1, 상기 제1 및 제2 층간절연막은 산화막을 사용하는 것을 특징으로하는 반도체소자의 비어콘택 제조방법.The first and second interlayer insulating film is a via contact manufacturing method of a semiconductor device, characterized in that using an oxide film. 하부배선 상에 제1층간절연막을 형성하는 공정과,Forming a first interlayer insulating film on the lower wiring; 비어홀용 노광마스크를 이용한 사진식각공정으로 상기 제1층간절연막을 식각하여 상기 하부배선을 노출시키는 비어홀을 형성하는 공정과,Forming a via hole for exposing the lower wiring by etching the first interlayer insulating film by a photolithography process using an exposure mask for via holes; 상기 비어홀을 매립하는 전체표면상부에 텅스텐을 형성하고 상기 제1층간절연막을 노출시키도록 CMP 하여 텅스텐 플러그를 형성하는 공정과,Forming a tungsten plug by forming tungsten on the entire surface of the via hole and CMP to expose the first interlayer insulating film; 상기 텅스텐 플러그를 마스크로 하여 상기 제1층간산화막을 전면식각하여 소정두께 식각하되, 상부배선의 두께만큼을 타겟으로 하여 실시하는 공정과,Etching the entire surface of the first interlayer oxide layer using the tungsten plug as a mask to etch a predetermined thickness, and performing the target by the thickness of the upper wiring; 전체표면상부에 상부배선용 도전층을 형성하는 공정과,Forming a conductive layer for upper wiring on the entire surface; 상부배선용 노광마스크를 이용한 사진식각공정으로 상기 상부배선용 도전층을 식각하여 패터닝하는 공정과,Etching and patterning the conductive layer for upper wiring by a photolithography process using an exposure mask for upper wiring; 전체표면상부에 제2층간산화막을 증착하고 상기 텅스텐 플러그를 노출시키는 CMP 공정으로 텅스텐 플러그와 상부배선용 도전층으로 형성된 상부배선을 형성하는 공정을 포함하는 것을 특징으로하는 반도체소자의 비어콘택 제조방법.And depositing a second interlayer oxide layer over the entire surface and exposing the tungsten plug to form an upper wiring formed of a tungsten plug and an upper wiring conductive layer. 제1항에 있어서,The method of claim 1, 상기 제1층간절연막은 종래의 상부배선 두께만큼 더 두껍게 형성한 것을 특징으로하는 반도체소자의 비어콘택 제조방법.The first interlayer insulating film is a via contact manufacturing method of a semiconductor device, characterized in that formed thicker than the conventional upper wiring thickness.
KR1019980062011A 1998-12-30 1998-12-30 Method for manufacturing via contact of semiconductor device KR100546146B1 (en)

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