KR100935188B1 - Method for manufacturing metal line in semiconductor device - Google Patents

Method for manufacturing metal line in semiconductor device Download PDF

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KR100935188B1
KR100935188B1 KR1020020069671A KR20020069671A KR100935188B1 KR 100935188 B1 KR100935188 B1 KR 100935188B1 KR 1020020069671 A KR1020020069671 A KR 1020020069671A KR 20020069671 A KR20020069671 A KR 20020069671A KR 100935188 B1 KR100935188 B1 KR 100935188B1
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film
metal wiring
forming
metal
via hole
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KR20040041794A (en
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한승희
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매그나칩 반도체 유한회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
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  • General Chemical & Material Sciences (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 Ti 금속막-산화막의 이중 스페이서를 이용하여 금속 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관해 개시한 것으로서, 하부 금속배선을 포함한 반도체 기판을 제공하는 단계와, 기판 상에 비아 홀 및 비아 홀을 매립시키는 도전 플러그를 가진 절연막을 형성하는 단계와, 절연막 상에 적어도 도전 플러그의 일부분과 연결되는 상부 금속배선을 형성하는 단계와, 결과물 전면에 Ti 금속막 및 산화막을 차례로 형성하는 단계와, 산화막 및 Ti 금속막을 건식 식각하여 상부 금속배선 측면에 도전 플러그 표면을 덮는 Ti 금속막-산화막 이중 스페이서를 형성하는 단계를 포함한다.The present invention discloses a method for forming a metal wiring of a semiconductor device capable of improving the reliability of metal wiring by using a double spacer of a Ti metal film-oxide film, comprising: providing a semiconductor substrate including a lower metal wiring; Forming an insulating film having a via hole and a conductive plug filling the via hole on the insulating film; forming an upper metal wiring connected to at least a portion of the conductive plug on the insulating film; and forming a Ti metal film and an oxide film on the entire surface of the resultant. And sequentially forming the oxide film and the Ti metal film by etching the oxide film and the Ti metal film to form a Ti metal film-oxide film double spacer covering the conductive plug surface on the upper metal wiring side.

Description

반도체 소자의 금속 배선 형성 방법{method for manufacturing metal line in semiconductor device}Method for manufacturing metal line in semiconductor device

도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 공정단면도.1A to 1F are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the prior art.

도 2는 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법의 문제점을 설명하기 위해 도시한 공정단면도.Figure 2 is a cross-sectional view showing a process for explaining the problem of the metal wiring formation method of a semiconductor device according to the prior art.

도 3a 내지 도 3d는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 공정단면도.3A to 3D are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 금속막-산화막의 이중 스페이서를 이용하여 금속 배선의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a metal wiring of a semiconductor device capable of improving reliability of metal wiring by using a double spacer of a metal film-oxide film.

반도체 제조 공정 중에서, 다중 레벨의 금속 배선을 전기적으로 연결하는 통로인 비아홀을 형성하는 공정에서는 반도체 소자가 고집적화 및 CD(Critical Dimension) 축소에 따라 미스어라인(mis-align)이 종종 발생한다. 이로 인하여 비 아 홀을 식각하는 과정에서 이온의 차징 데미지(charging demage)가 발생하며, 후처리 공정에서 상기 비아홀을 매립시키는 도전 플러그의 붕괴(corrision) 현상 및 금속 배선의 일부가 손실되는 현상이 발생한다.In the semiconductor manufacturing process, in the process of forming a via hole, which is a passage for electrically connecting multiple levels of metal wiring, mis-alignment is often caused by high integration of semiconductor devices and reduction of critical dimensions (CDs). As a result, charging demage of ions occurs in the process of etching via holes, and a phenomenon in which a portion of a metal wiring is lost and a corrosion of conductive plugs filling the via holes are generated in a post-treatment process. do.

도 1a 내지 도 1f는 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 공정단면도이다. 1A to 1F are cross-sectional views illustrating a method of forming a metal wiring of a semiconductor device according to the prior art.

종래 기술에 따른 반도체 소자의 금속 배선 형성 방법은, 도 1a에 도시된 바와 같이, 하부 금속배선(3)을 포함한 반도체 기판(1) 상에 회전 도포방식으로 저유전상수값을 갖는 절연막(5)을 형성한다. 이때, 상기 절연막(5)은 저유전상수 산화물이 갖고 있는 점착성(viscosity)으로 인해 하부 금속배선(3) 위에 동일한 두께로 도포되지 않고 하부 금속배선의 넓이 또는 밀도에 따라 다르게 도포된다. 일반적으로 하부 금속배선의 면적이 큰 경우는 그렇지 않은 경우에 비해 두껍게 도포되고, 하부 금속배선의 밀도가 높을 경우 그렇지 않은 경우에 비해 두껍게 도포된다. 따라서, 상기 절연막(5)에 화학적-기계적 연마 공정을 진행하여 평탄화시킨다.In the method of forming metal wires of a semiconductor device according to the prior art, as shown in FIG. 1A, an insulating film 5 having a low dielectric constant value is formed on a semiconductor substrate 1 including a lower metal wire 3 by a rotation coating method. Form. At this time, the insulating film 5 is not applied with the same thickness on the lower metal wiring 3 due to the viscosity of the low dielectric constant oxide is applied differently depending on the width or density of the lower metal wiring. In general, when the area of the lower metal wiring is large, the coating is thicker than when it is not, and when the density of the lower metal wiring is high, the coating is thicker than when it is not. Accordingly, the insulating film 5 is subjected to a chemical-mechanical polishing process to planarize it.

이어, 상기 연마 공정이 완료된 절연막 상에 감광막을 도포하고 노광 및 현상하여 비아 홀영역을 노출시키는 제 1감광막 패턴을 형성한다. Subsequently, a photoresist film is coated on the insulating film on which the polishing process is completed, and the photoresist film is exposed and developed to form a first photoresist film pattern exposing the via hole region.

그런 다음, 도 1b에 도시된 바와 같이, 상기 제 1감광막 패턴을 마스크로 하고 상기 절연막을 플라즈마 건식 식각하여 비아 홀(6)을 형성하고 나서, 상기 제 1감광막 패턴을 제거한다. 일반적으로 상기 비아 홀을 플라즈마 건식 식각 공정에서는 기판의 모든 부위에서 절연막 두께오차(variation)에 상관없이 비아 홀이 완전히 식각되도록 하기 위해 일정 정도의 과도 식각(over etch)을 실시한다. Then, as illustrated in FIG. 1B, the via photoresist pattern is formed by using the first photoresist pattern as a mask and plasma dry etching the insulating layer to form a via hole 6, and then the first photoresist pattern is removed. In general, in the plasma dry etching process, the via hole is overetched to some extent so that the via hole is completely etched regardless of the insulation layer thickness variation.                         

이 후, 도 1c에 도시된 바와 같이, 상기 비아 홀(6)을 포함한 기판 전면에 제 1TiN(티타늄나이트라이드)막(7)을 형성한다. 이때, 상기 제 1TiN막(7)은 이 후에 형성되는 텅스텐막 증착 공정에서 텅스텐 성분이 하부로의 확산되는 것을 방지하는 확산방지막으로서, 플라즈마-촉발-화학기상증착(plasma enhanced chemical vapor deposition) 방법에 의해 형성한다. 또한, 상기 절연막(5)과 제 1TiN막(7)을 사이에 제 1Ti(티타늄)막(미도시)을 개재시키어 이들 막간의 접착력을 향상시킨다.Thereafter, as shown in FIG. 1C, a first TiN (titanium nitride) film 7 is formed on the entire surface of the substrate including the via hole 6. In this case, the first TiN film 7 is a diffusion preventing film that prevents the tungsten component from being diffused downward in the tungsten film deposition process formed thereafter. The first TiN film 7 may be used in a plasma enhanced chemical vapor deposition method. By forming. In addition, a first Ti (titanium) film (not shown) is interposed between the insulating film 5 and the first TiN film 7 to improve adhesion between these films.

이어, 상기 제 1Ti(티타늄)/제 1TiN(티타늄나이트라이드)막(7) 전면에 스퍼터링 방법에 의해 텅스텐막(9)을 형성한다. Next, a tungsten film 9 is formed on the entire surface of the first Ti (titanium) / first TiN (titanium nitride) film 7 by a sputtering method.

그런 다음, 도 1d에 도시된 바와 같이, 상기 절연막이 노출되는 시점까지 상기 텅스텐막 및 제 1TiN막을 화학적-기계적 연마(Chemical Mechnical Polishing)하여 텅스텐 플러그(10)를 형성한다.Then, as illustrated in FIG. 1D, the tungsten film and the first TiN film are chemically mechanically polished to form the tungsten plug 10 until the insulating film is exposed.

이 후, 도 1e에 도시된 바와 같이, 상기 텅스텐 플러그(10)를 포함한 기판 전면에 제 2Ti막(11), 알루미늄(Al)막(13) 및 제 2TiN막(15)을 차례로 형성한다. 이때, 상기 제 2Ti막(11)은 접착막 역할을 하며, 알루미늄막(13)은 전기 신호를 전달하는 도전층 역할을 한다. 한편, 상기 제 2TiN막(15)은 이 후의 제 2감광막 패턴 형성 시 빛의 반사를 줄여주는 반사방지막(Anti-Reflective-Coating:ARC) 역할을 담당한다.Thereafter, as shown in FIG. 1E, a second Ti film 11, an aluminum (Al) film 13, and a second TiN film 15 are sequentially formed on the entire surface of the substrate including the tungsten plug 10. In this case, the second Ti film 11 serves as an adhesive film, and the aluminum film 13 serves as a conductive layer for transmitting an electrical signal. On the other hand, the second TiN film 15 serves as an anti-reflective coating (ARC) to reduce the reflection of light in the subsequent formation of the second photoresist pattern.

이어, 상기 제 2TiN막(15) 상에 상부 금속배선영역(미도시)을 노출시키는 제 2감광막 패턴(22)을 형성한다. Subsequently, a second photoresist layer pattern 22 exposing an upper metal wiring region (not shown) is formed on the second TiN layer 15.

그런 다음, 도 1f에 도시된 바와 같이, 상기 제 2감광막 패턴을 마스크로 하 고 Cl2 및 BCl3가스를 활성화시킨 플라즈마 건식 식각 방법에 의해 상기 제 2TiN막, 알루미늄막 및 제 1Ti막을 제거하여 텅스텐 플러그(10)와 전기적으로 연결되는 상부 금속배선(17)을 형성한다. 이 후, 제 2감광막 패턴을 제거한다. 이때, 상기 상부 금속배선(17)은 설계 상으로는 텅스텐 플러그(10)를 완전히 덮는 구조를 가지지만, 실제적으로는 상부 금속배선(17)이 텅스텐 플러그(10)를 완전히 덮지 못하는 경우가 종종 발생한다. 왜냐하면, 금속 배선의 집적도가 높아질수록 금속 배선과 텅스텐 플러그 사이의 겹침-여유분(overlap margin)이 작아지며, 이렇게 겹침-여유분이 충분하지 못한 상태에서는 제 2 감광막 패턴을 형성하는 과정에서 틀어짐(tilt) 현상과 선-끝-축소(line end shortening) 현상이 발생함으로써, 상부 금속 배선(17)이 하부의 텅스텐 플러그(10)를 완전히 덮지 못하는 경우가 발생한다.Then, as shown in FIG. 1F, the second TiN film, the aluminum film, and the first Ti film are removed by a plasma dry etching method using the second photoresist film pattern as a mask and activating Cl2 and BCl3 gases. The upper metal wiring 17 is electrically connected to the 10. Thereafter, the second photosensitive film pattern is removed. In this case, the upper metal wiring 17 has a structure that completely covers the tungsten plug 10 in design, but in practice, the upper metal wiring 17 may not completely cover the tungsten plug 10. Because, as the degree of integration of the metal wiring increases, the overlap-over margin between the metal wiring and the tungsten plug becomes smaller. In this state, the overlap-over margin is insufficient, and thus the second photosensitive film pattern is distorted in the process of forming the second photoresist pattern. As a result of the phenomenon and the line end shortening, the upper metal wiring 17 cannot completely cover the lower tungsten plug 10.

도 2는 종래 기술에 따른 반도체 소자의 금속 배선 형성 방법의 문제점을 설명하기 위해 도시한 공정단면도이다.2 is a cross-sectional view illustrating a process of forming a metal wiring of a semiconductor device according to the prior art.

종래의 기술에서는, 상부 금속배선 형성 시, 감광막 패턴 형성 과정에서 발생하는 틀어짐 현상 및 선-끝-축소 현상의 영향을 받아 상부 금속배선의 끝부분이 일부 축소됨으로써, 도 2에 도시된 바와 같이, 상부 금속 배선이 텅스텐-플러그와 미스어라인되어 상부 금속배선과 텅스텐 플러그 사이의 접촉 면적이 작아지게 된다. 그 결과 상부 금속배선과 텅스텐 플러그 사이의 전기적 접촉이 취약해질 뿐만 아니라, 고밀도 플라즈마를 사용하므로 이들 이온이 차징(charging)된다. In the prior art, when the upper metal wiring is formed, the end portion of the upper metal wiring is partially reduced under the influence of the distortion phenomenon and the line-end-reduction phenomenon occurring during the photoresist pattern forming process, as shown in FIG. 2. The upper metal wiring is misaligned with the tungsten plug and the contact area between the upper metal wiring and the tungsten plug is reduced. The result is a weak electrical contact between the upper metallization and the tungsten plug, as well as the charging of these ions due to the use of high density plasma.                         

또한, 텅스텐의 전위(electric potential)가 증가되어 후처리 세정 공정에서 텅스텐 플러그의 붕괴 현상이 발생되며, 또한 알루미늄막 하부의 제 2Ti막은 스트레스(stress) 또는 후처리 세정 공정에서 손실이 발생된다.(A부분 참조) 이러한 현상에 의해 비아 홀 프로파일 오픈 및 알씨 딜레이(RC Delay) 증가를 가져와서 수율이 저하되는 문제점이 있었다.Further, the electric potential of tungsten is increased to cause the tungsten plug to collapse in the post-treatment cleaning process, and the second Ti film under the aluminum film causes a loss in stress or post-treatment cleaning process. Due to this phenomenon, the via hole profile open and the RC delay increased, resulting in a decrease in yield.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 상부 금속배선 형성을 위한 플라즈마 건식 식각 공정에서, 이온 차징에 의한 텅스텐 플러그 붕괴 및 Ti손실이 발생됨을 억제할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above-mentioned problems. In the plasma dry etching process for forming the upper metal wiring, the tungsten plug collapse and Ti loss due to ion charging can be suppressed. The purpose is to provide a forming method.

상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속 배선 형성 방법은, 하부 금속배선을 포함한 반도체 기판을 제공하는 단계와, 기판 상에 비아 홀 및 비아 홀을 매립시키는 도전 플러그를 가진 절연막을 형성하는 단계와, 절연막 상에 적어도 도전 플러그의 일부분과 연결되는 상부 금속배선을 형성하는 단계와, 결과물 전면에 Ti 금속막 및 산화막을 차례로 형성하는 단계와, 산화막 및 Ti 금속막을 건식 식각하여 상부 금속배선 및 도전 플러그를 덮는 Ti 금속막-산화막 이중 스페이서를 형성하는 단계를 포함한 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a metal wiring of a semiconductor device, the method including: providing a semiconductor substrate including a lower metal wiring, and forming an insulating film having a via hole and a conductive plug filling a via hole on the substrate Forming an upper metal wiring connected to at least a portion of the conductive plug on the insulating film, sequentially forming a Ti metal film and an oxide film on the entire surface of the resultant, and dry etching the oxide film and the Ti metal film to dry the upper metal wiring. And forming a Ti metal film-oxide double spacer covering the conductive plug.

상기 Ti 금속막은 화학기상증착하여 형성한다.The Ti metal film is formed by chemical vapor deposition.

한편, 상기 건식 식각 공정은 CHF3 및 CF4가스를 활성화시킨 플라즈마를 이용한다. On the other hand, the dry etching process uses a plasma activated CHF3 and CF4 gas.                     

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3d는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 공정단면도이다.3A to 3D are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention.

본 발명의 일실시예에 따른 반도체 소자의 금속 배선 형성 방법은, 도 3a에 도시된 바와 같이, 먼저 하부 금속배선(102)을 포함한 반도체 기판(100) 상에 절연막(104)을 형성한 후, 포토리쏘그라피 공정에 의해 상기 절연막(104)을 선택 식각하여 비아 홀(106)을 형성한다. 그런 다음, 상기 비아 홀(106) 내에 텅스텐 플러그(110)를 형성한다. 상기 비아 홀(106)과 텅스텐 플러그(110) 사이에는 제 1Ti막(미도시)을 개재시키어 제 1TiN막(108)을 형성한다. 이때, 상기 제 1Ti막은 접착막이고, 제 1TiN막(108)은 후속의 텅스텐막으로 이루어진 상부 금속배선에서 텅스텐 성분이 하부로 확산되는 것을 방지하는 확산방지막으로서의 역할을 한다. In the method for forming metal wires of a semiconductor device according to an embodiment of the present invention, as shown in FIG. 3A, first, after forming the insulating film 104 on the semiconductor substrate 100 including the lower metal wires 102, The via hole 106 is formed by selectively etching the insulating layer 104 by a photolithography process. Then, a tungsten plug 110 is formed in the via hole 106. A first TiN film 108 is formed between the via hole 106 and the tungsten plug 110 with a first Ti film (not shown) interposed therebetween. In this case, the first Ti film is an adhesive film, and the first TiN film 108 serves as a diffusion barrier to prevent the tungsten component from diffusing downward in the upper metal wiring formed of the subsequent tungsten film.

상기 결과물 상에 제 2Ti막(112), 알루미늄막 및 제 2TiN막(116)을 차례로 형성한 다음, 상기 막들을 플라즈마 건식 식각함으로서 텅스텐 플러그(110)와 전기적으로 연결되는 상부 금속배선(114)을 형성한다. 이때, 상기 텅스텐-플러그(110)와 상기 상부 금속배선(114) 사이에는 확산방지막으로서 제 2Ti막(112)을 개재시켜 접착력을 향상시키고, 상기 상부 금속배선(114) 상부에는 반사방지막으로서 제 2TiN막(116)을 형성한다.A second Ti film 112, an aluminum film, and a second TiN film 116 are sequentially formed on the resultant, and the upper metal wiring 114 electrically connected to the tungsten plug 110 is formed by plasma dry etching the films. Form. At this time, the adhesion between the tungsten plug 110 and the upper metal wiring 114 is interposed with a second Ti film 112 to improve adhesion, and the second TiN as an anti-reflection film on the upper metal wiring 114. A film 116 is formed.

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한편, 상기 상부 금속배선(114) 형성을 위한 플라즈마 건식 식각 공정에서 텅스텐-플러그(110)와 상부 금속 배선(114)이 미스어라인됨으로서, 텅스텐-플러그(110)의 붕괴 현상 및 제 2Ti막(112) 손실 현상이 발생되어 비아 홀(106)이 노출된다. Meanwhile, the tungsten-plug 110 and the upper metal wiring 114 are misaligned in the plasma dry etching process for forming the upper metal wiring 114, so that the tungsten-plug 110 collapses and the second Ti film ( 112) A loss phenomenon occurs and the via hole 106 is exposed.

이 후, 도 3b에 도시된 바와 같이, 상기 구조 전면에 화학기상증착 공정에 의해 제 3Ti막(118)을 형성하고 나서, 도 3c에 도시된 바와 같이, 상기 제 3Ti막(118) 상에 산화막(120)을 형성한다. 이때, 상기 산화막(120)은 실리콘 산화막으로서, 상기 산화막(120)은 상기 제 3Ti막(118)이 형성된 결과물의 프로파일을 따라 형성한다. Thereafter, as shown in FIG. 3B, a third Ti film 118 is formed on the entire structure by a chemical vapor deposition process, and as shown in FIG. 3C, an oxide film is formed on the third Ti film 118. Form 120. In this case, the oxide film 120 is a silicon oxide film, and the oxide film 120 is formed along the profile of the resultant product in which the third Ti film 118 is formed.

그런 다음, 도 3d에 도시된 바와 같이, CHF3 및 CH4 가스를 활성화시킨 플라즈마를 이용하여 상기 실리콘 산화막 및 제 3Ti막을 건식 식각함으로서, 상기 상부 금속배선(114) 측면에 Ti 금속막-실리콘 산화막의 이중 스페이서(119)(121)를 형성한다. 이때, 상기 이중 스페이서(119)(121)는 텅스텐-플러그(110)의 노출된 부분을 덮는다. Then, as shown in FIG. 3D, by dry etching the silicon oxide film and the third Ti film by using a plasma activated with CHF3 and CH4 gas, the double layer of the Ti metal film-silicon oxide film on the side of the upper metal wiring 114. Spacers 119 and 121 are formed. In this case, the double spacers 119 and 121 cover exposed portions of the tungsten plug 110.

본 발명에 따르면, 텅스텐-플러그와 상부 금속배선이 미스어라인됨에 따라,상부 금속배선 형성을 위한 플라즈마 건식 식각 공정에서, 텅스텐-플러그의 일부 붕괴 현상 및 Ti막 손실 현상이 발생될 경우, 상기 텅스텐-플러그 붕괴 및 Ti막 손실이 발생된 부분을 덮는 Ti막-산화막의 이중 스페이서를 형성한다.According to the present invention, as the tungsten-plug and the upper metal wiring are misaligned, when the tungsten-plug partially collapses and the Ti film is lost in the plasma dry etching process for forming the upper metal wiring, the tungsten A double spacer of a Ti film-oxide film is formed to cover a portion where plug collapse and Ti film loss occur.

이상에서와 같이, 상부 금속 배선 및 텅스텐-플러그 간의 미스어라인됨에 따라, 상부 금속배선 형성을 위한 플라즈마 건식 식각 공정에서 텅스텐 플러그의 일부 붕괴 현상 및 Ti막 손실 현상이 발생된 경우, 본 발명에서는 상기 손실된 부분을 덮는 Ti막-산화막의 이중 스페이서를 형성함으로써, 갭필 특성 향상, 비아 홀 오픈 및 알씨 딜레이가 높아지는 현상을 방지하여 금속 배선의 신뢰성 및 수율 향상의 이점이 있다. 또한, 상부 금속배선과 도전 플러그 간의 접촉 면적을 넓힐 수 있다.As described above, when some of the tungsten plugs are collapsed and the Ti film is lost in the plasma dry etching process for forming the upper metal wires due to misalignment between the upper metal wires and the tungsten-plug, in the present invention, By forming the double spacer of the Ti film-oxide film covering the lost portion, there is an advantage of improving the gap fill characteristics, preventing the opening of via holes, and increasing the delay of the Al, thereby improving the reliability and yield of the metal wiring. In addition, the contact area between the upper metal wiring and the conductive plug can be increased.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

하부 금속배선을 포함한 반도체 기판을 제공하는 단계와,Providing a semiconductor substrate comprising a lower metallization, 상기 기판 상에 상기 하부 금속배선의 일부분을 노출시키는 비아 홀 및 상기 비아 홀을 매립시키는 도전 플러그를 가진 절연막을 형성하는 단계와,Forming an insulating film having a via hole exposing a portion of the lower metal wiring on the substrate and a conductive plug filling the via hole; 상기 절연막 상에 적어도 상기 도전 플러그의 일부분과 연결되는 상부 금속배선을 형성하는 단계와,Forming an upper metal interconnection on at least a portion of the conductive plug on the insulating layer; 상기 결과물 전면에 Ti 금속막 및 실리콘 산화막을 차례로 형성하는 단계와,Sequentially forming a Ti metal film and a silicon oxide film on the entire surface of the resultant, 상기 산화막 및 상기 Ti 금속막을 건식 식각하여 상기 상부 금속배선 측면에 상기 도전 플러그의 표면을 덮는 Ti 금속막-실리콘 산화막 이중 스페이서를 형성하는 단계를 포함한 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.Dry etching the oxide film and the Ti metal film to form a Ti metal film-silicon oxide double spacer covering a surface of the conductive plug on the side of the upper metal wiring. 제 1항에 있어서, 상기 Ti 금속막은 화학기상증착하여 형성한 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the Ti metal film is formed by chemical vapor deposition. 제 1항에 있어서, 상기 건식 식각 공정은 CHF3 및 CF4가스를 활성화시킨 플라즈마를 이용한 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The method of claim 1, wherein the dry etching process uses plasma in which CHF 3 and CF 4 gases are activated.
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KR19990051220A (en) * 1997-12-19 1999-07-05 김영환 Method for forming metal wiring of semiconductor device with plug metal film
KR20010004996A (en) * 1999-06-30 2001-01-15 김영환 Method of forming a semiconductor device
KR20030002529A (en) * 2001-06-29 2003-01-09 주식회사 하이닉스반도체 Method for forming a metal line

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KR101103550B1 (en) * 2004-07-15 2012-01-09 매그나칩 반도체 유한회사 A method for forming a metal line in semiconductor device

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