KR20010061614A - Method for shame contact hole of semiconductor device - Google Patents
Method for shame contact hole of semiconductor device Download PDFInfo
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- KR20010061614A KR20010061614A KR1019990064111A KR19990064111A KR20010061614A KR 20010061614 A KR20010061614 A KR 20010061614A KR 1019990064111 A KR1019990064111 A KR 1019990064111A KR 19990064111 A KR19990064111 A KR 19990064111A KR 20010061614 A KR20010061614 A KR 20010061614A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Abstract
Description
본 발명은 반도체 장치에 관한 것으로, 특히 배선 형성시 RC 딜레이에 의한 스피드 개선을 위해 사용되는 저유전체막을 갖는 반도체 장치의 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device having a low dielectric film used for improving speed due to RC delay in forming wiring.
일반적으로 반도체 제조공정의 배선 형성시 RC 딜레이에 의한 스피드 문제를개선시키기 위해 층간 절연막으로 LOW-K 막질(저유전체막)이 주로 사용되고 있다. 상기 LOW-K(K ≤3.5)막으로는 K = 3.5 수준의 FSG(SiOF), K = 3.0 수준의 HSQ(Hydro-silsequioxane), K = 2.6 수준의 MSQ(Methyl-silsequioxane)와 같은 무기물과 K ≤2.5의 기타 유기물(Organics)등이 개발 및 사용되고 있다.In general, LOW-K film quality (low dielectric film) is mainly used as an interlayer insulating film in order to improve the speed problem caused by the RC delay in wiring formation in the semiconductor manufacturing process. As the LOW-K (K ≤3.5) film, inorganic materials such as K = 3.5 FSG (SiOF), K = 3.0 HS-Hydro-silsequioxane (HSQ), K = 2.6 Methyl-silsequioxane (MSQ), and K Other organic materials (≤2.5) and the like have been developed and used.
여기서, MSQ는 Si-CH3를 갖는 구조로써 SiO2와는 다른 식각 특성을 보이고 있다.Here, MSQ has a Si-CH 3 structure and shows etching characteristics different from that of SiO 2 .
이하, 첨부된 도면을 참조하여 종래의 반도체 장치의 콘택홀 형성방법에 대하여 설명하면 다음과 같다.Hereinafter, a method for forming a contact hole in a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1은 종래의 반도체 장치의 콘택홀 형성방법을 나타낸 공정 단면도이다.1 is a cross-sectional view illustrating a conventional method for forming a contact hole in a semiconductor device.
도 1에 도시한 바와 같이 배선 형성시 반도체 기판(도면에 도시하지 않았음)에 하부 도전층으로 이용되는 금속배선(1)을 형성하고, 상기 금속배선(1)상에 제 1 절연막과 저유전체막(2)(3) 및 제 2 절연막(4)을 차례로 형성한다. 그리고 상기 제 2 절연막(4)상에 포토레지스트를 증착하고, 노광 및 현상공정을 이용하여 포토레지스트 패턴(5)을 형성한 후, 상기 포토레지스트 패턴(5)을 마스크로 하여 건식식각 공정을 통해 상기 금속배선(1)이 소정부분 노출되도록 콘택홀(6)을 형성한다.As shown in FIG. 1, a metal wiring 1 used as a lower conductive layer is formed on a semiconductor substrate (not shown) when forming a wiring, and a first insulating film and a low dielectric material are formed on the metal wiring 1. The films 2 and 3 and the second insulating film 4 are sequentially formed. After the photoresist is deposited on the second insulating film 4 and the photoresist pattern 5 is formed by using an exposure and development process, the photoresist pattern 5 is used as a mask through a dry etching process. The contact hole 6 is formed to expose a predetermined portion of the metal wire 1.
이때, 상기 제 1 절연막(2)은 질화티타늄(TiN), 티타늄(Ti)를 사용하고, 제 2 절연막(4)은 산화막을 사용한다. 그리고 상기 건식식각 공정시 CH3가스를 이용한다.In this case, the first insulating film 2 uses titanium nitride (TiN) and titanium (Ti), and the second insulating film 4 uses an oxide film. And CH 3 gas is used in the dry etching process.
여기서, H 또는 CHx를 함유하고 있는 저유전체막의 무기물은 낮은 C/F 비율을 갖는 체미스트(chemistry)에서 식각이 잘 이루어지나 F에 의해서 도면에 점선으로 표시한 부분(7)한 것 같이 측면이 만곡(彎曲) 형태로 식각이 이루어진다.Here, the inorganic material of the low dielectric film containing H or CH x is well etched in a chemistry having a low C / F ratio, but the side as shown by the dotted line 7 in the drawing by F The etching is performed in this curved form.
또한, 저유전체막의 경우 고온 에싱(ashing)시 손상이 발생하여 알루미늄 배선에 경우 저온 에싱 처리 후, 클리닝하여 하부 도전층으로 이용되는 금속배선이 소정부분 노출되도록 콘택홀 형성시 침식 현상이 발생한다.In addition, in the case of the low dielectric film, damage occurs during high temperature ashing, and in the aluminum wiring, after the low temperature ashing treatment, the erosion phenomenon occurs when the contact hole is formed to expose a predetermined portion of the metal wiring used as the lower conductive layer by cleaning.
따라서, 후 공정에 베리어 메탈 및 상부 도전층으로 이용될 금속배선 형성에 있어서, 접착성 문제 및 신뢰성이 저하되고, 스피드에 문제가 발생한다.Therefore, in forming the metal wiring to be used as the barrier metal and the upper conductive layer in a later process, the adhesion problem and the reliability are lowered, and a problem occurs in speed.
또한, 하부 절연막으로 이용되는 질화티타늄(TiN), 티타늄(Ti)과 고선택적 식각이 어렵고 C/F 비율이 높은 체미스트에서는 식각 스톱 현상이 쉽게 발생한다.In addition, the etching stop phenomenon easily occurs in the titanium nitride (TiN), titanium (Ti) used as the lower insulating film and a high chemost with high C / F ratio.
상기와 같은 종래의 반도체 장치의 콘택홀 형성방법에 있어서는 다음과 같은 문제점이 있었다.The above-mentioned conventional method for forming a contact hole in a semiconductor device has the following problems.
배선 형성시 RC 딜레이에 의한 스피드 문제를 개선시키기 위해 이용되는 저유전체막에 있어서, CHx가스를 이용하여 건식식각 공정을 통해 콘택홀 형성시 저유전체막 측면에 만곡 형태로 식각 제거된다.In the low dielectric film used to improve the speed problem due to the RC delay when forming the wiring, the etching is removed in the form of a curved side on the side of the low dielectric film when forming a contact hole through a dry etching process using CH x gas.
따라서 후 공정에 있어, 상부 금속배선 형성시 접착성 문제가 발생하여 신뢰성 및 스피드 저하가 발생한다. 또한, 하부 절연막과 고선택적 식각이 어렵다.Therefore, in a later process, adhesion problems occur when the upper metal wiring is formed, resulting in a decrease in reliability and speed. In addition, the lower insulating film and high selective etching are difficult.
그리고 저유전체막은 고온 에싱 처리시 손상이 발생하므로 알루미늄 배선의경우 저온 에칭처리 후, 클리닝 공정을 통해 하부 금속배선이 노출되도록 콘택홀 형성시 침식현상이 발생한다.In addition, since the low dielectric film is damaged during the high temperature ashing process, after the low temperature etching process in the aluminum wiring, the erosion phenomenon occurs when the contact hole is formed to expose the lower metal wiring through the cleaning process.
상기와 같은 문제점을 해결하기 위하여 본 발명은 저유전체막을 갖는 콘택홀 형성시 혼합가스를 이용한 식각 공정을 통해 신뢰성 및 스피드를 향상시키는데 적당한 반도체 장치의 콘택홀 형성방법을 제공하는데 그 목적이 있다.In order to solve the above problems, an object of the present invention is to provide a method for forming a contact hole in a semiconductor device suitable for improving reliability and speed through an etching process using a mixed gas when forming a contact hole having a low dielectric film.
도 1은 종래의 반도체 장치의 콘택홀 형성방법을 나타낸 공정 단면도1 is a cross-sectional view illustrating a method of forming a contact hole in a conventional semiconductor device.
도 2는 본 발명의 반도체 장치의 콘택홀 형성방법을 나타낸 공정 단면도2 is a cross-sectional view illustrating a method of forming a contact hole in a semiconductor device of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
21 : 금속배선 22 : 제 1 절연막21 metal wiring 22 first insulating film
23 : 제 2 절연막 24 : 제 3 절연막23: second insulating film 24: third insulating film
25 : 포토레지스트 패턴 26 : 콘택홀25 photoresist pattern 26 contact hole
이상에서 설명한 바와 같이 본 발명의 반도체 장치의 콘택홀 형성방법은 하부 도전층의 금속배선을 형성하고, 상기 금속배선상에 무기물 저유전체막과 절연막을 차례로 형성하는 단계와, 상기 무기물 저유전체막 및 절연막을 CxFy/CHxFy/O2/N2를 동시에 혼합 주입하여 건식식각 공정을 통해 선택적으로 상기 금속배선이 소정부분 노출되도록 콘택홀을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.As described above, the method of forming a contact hole in the semiconductor device of the present invention includes forming a metal wiring of a lower conductive layer, sequentially forming an inorganic low dielectric film and an insulating film on the metal wiring, the inorganic low dielectric film, and And forming a contact hole to selectively expose a predetermined portion of the metal wiring through a dry etching process by simultaneously injecting an insulating film with C x F y / CH x F y / O 2 / N 2 at the same time. do.
상기와 같은 특징의 바람직한 실시예에 있어서, 상기 CxFy가스는 C/F 비율이 0.5 이상인 가스를 사용하는 것을 특징으로 한다.In a preferred embodiment of the above features, the C x F y gas is characterized by using a gas having a C / F ratio of 0.5 or more.
상기와 같은 특징의 바람직한 실시예에 있어서, 상기 CHxFy가스는 H/F 비율이 1 이상인 가스를 사용하는 것을 특징으로 한다.In a preferred embodiment of the above features, the CH x F y gas is characterized by using a gas having an H / F ratio of 1 or more.
상기와 같은 특징의 바람직한 실시예에 있어서, 상기 건식식각 공정시 He, Ar, Xe과 같은 불활성 가스를 추가로 혼합주입하는 것을 특징으로 한다.In a preferred embodiment of the above characteristics, in the dry etching process characterized in that the inert gas, such as He, Ar, Xe is additionally mixed.
상기와 같은 특징의 바람직한 실시예에 있어서, 상기 콘택홀 형성시CxFy/CHxFy/N2O/NO 가스를 혼합주입하여 상기 금속배선이 소정부분 노출되도록 상기 무기물 저유전체막과 절연막을 선택적으로 식각제거하는 공정을 포함하여 이루어짐을 특징으로 한다.In a preferred embodiment of the above features, the inorganic low-dielectric film and the inorganic low-dielectric film so as to expose a predetermined portion of the metal wiring by mixing the injection of C x F y / CH x F y / N 2 O / NO gas when forming the contact hole And selectively removing and removing the insulating film.
상기와 같은 특징의 바람직한 실시예에 있어서, 상기 CxFy가스는 5∼30sccm, CHxFy가스는 1∼20sccm, O2가스는 1∼20sccm, N2가스는 3∼200sccm를 사용하며, 압력은 100mT보다 작거나 같게 하는 것을 특징으로 한다.In a preferred embodiment of the above features, the C x F y gas is 5 to 30 sccm, the CH x F y gas is 1 to 20 sccm, the O 2 gas is 1 to 20 sccm, the N 2 gas is 3 to 200 sccm , Pressure is less than or equal to 100mT.
상기와 같은 특징의 바람직한 실시예에 있어서, 상기 He, Ar, Xe과 같은 불활성 가스는 0∼1000sccm를 사용하며, 압력은 100mT보다 작거나 같게 하는 것을 특징으로 한다.In a preferred embodiment of the above features, the inert gas such as He, Ar, Xe is used from 0 to 1000sccm, the pressure is characterized in that less than or equal to 100mT.
상기와 같은 특징의 바람직한 실시예에 있어서, 상기 N2O 가스는 1∼20sccm를 사용하며, 압력은 100mT보다 작거나 같게 하는 것을 특징으로 한다.In a preferred embodiment of the above features, the N 2 O gas is used 1 to 20sccm, the pressure is characterized in that less than or equal to 100mT.
상기와 같은 특징의 바람직한 실시예에 있어서, 상기 금속배선과 저유전체막 사이에 스톱층 TiN, Ti, TaN, Ta, SiN, SiC, SiON을 형성하는 것을 포함하여 이루어짐을 특징으로 한다.In a preferred embodiment of the above features, it characterized in that it comprises forming a stop layer TiN, Ti, TaN, Ta, SiN, SiC, SiON between the metal wiring and the low dielectric film.
이하, 첨부된 도면을 참조하여 본 발명의 반도체 장치의 콘택홀 형성방법에 대하여 보다 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a contact hole in a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 반도체 장치의 콘택홀 형성방법을 나타낸 공정 단면도이다.2 is a cross-sectional view illustrating a method of forming a contact hole in a semiconductor device of the present invention.
도 2에 도시한 바와 같이 배선 형성시 반도체 기판(도면에 도시하지 않았음)에 하부 도전층으로 이용되는 금속배선(21)을 형성하고, 상기 금속배선(21)상에 제 1 절연막과 저유전체막(22)(23) 및 제 2 절연막(24)을 차례로 형성한다. 그리고 상기 제 2 절연막(24)상에 포토레지스트를 증착하고, 노광 및 현상공정을 이용하여 포토레지스트 패턴(25)을 형성한 후, 상기 포토레지스트 패턴(25)을 마스크로 하여 건식식각 공정을 통해 상기 금속배선(21)이 소정부분 노출되도록 콘택홀(26)을 형성한다.As shown in FIG. 2, a metal wiring 21 used as a lower conductive layer is formed on a semiconductor substrate (not shown) when wiring is formed, and a first insulating film and a low dielectric material are formed on the metal wiring 21. The films 22 and 23 and the second insulating film 24 are sequentially formed. After the photoresist is deposited on the second insulating film 24 and the photoresist pattern 25 is formed by using an exposure and development process, the photoresist pattern 25 is used as a mask to perform a dry etching process. The contact hole 26 is formed to expose a predetermined portion of the metal wiring 21.
이때, 이때, 상기 제 1 절연막(22)은 하부 절연막으로 TiN, Ti, Ta, TaN 및 SiN, SiON, SiC를 사용한다. 그리고 제 2 절연막(24)은 산화막을 사용하고 상기 건식식각 공정시 O2, CxFy, CHxFy, N2가스를 이용한다.At this time, the first insulating film 22 uses TiN, Ti, Ta, TaN and SiN, SiON, SiC as the lower insulating film. In addition, an oxide film is used as the second insulating film 24, and O 2 , C x F y , CH x F y , and N 2 gas are used in the dry etching process.
여기서, 상기 CxFy가스는 C/F의 비율을 x/y ≥0.5정도 즉, C4F8, C5F8, C4F6등과 같이 사용한다. 그리고 상기 CHxFy가스는 H/F의 비율을 x/y ≥1 정도 즉, CH2F2,CH3F, CH4등과 같이 사용한다.Here, the C x F y gas uses a ratio of C / F as x / y ≥ 0.5, that is, C 4 F 8 , C 5 F 8 , C 4 F 6, and the like. The CH x F y gas uses a ratio of H / F as x / y ≥ 1, that is, CH 2 F 2 , CH 3 F, CH 4, and the like.
한편, 상기 콘택홀 형성시 CxFy, CHxFy, N2혼합가스에 추가로 He, Ar, Xe등과 같은 불활성 가스를 혼합주입하여 건식식각 공정을 실시한다.Meanwhile, when the contact hole is formed, a dry etching process is performed by injecting an inert gas such as He, Ar, and Xe into the C x F y , CH x F y , and N 2 mixed gases.
여기서, 상기 CxFy는 F에 의해 쉽게 상기 저유전체막(23)의 측면이 식각되어 발생하는 만곡(彎曲) 현상이 발생하나 상기 저유전체막(23) 식각공정시 스퍼터링에 의해 상기 저유전체막(23) 측면에 보호막과 같은 CxFy계 폴리머가 형성된다.Here, the C x F y is a curvature phenomenon caused by the side surface of the low dielectric film 23 is easily etched by F, but the low dielectric material by sputtering during the etching process of the low dielectric film 23 On the side of the film 23, a C x F y- based polymer such as a protective film is formed.
또한, CxFy계 폴리머 형성에 의해 상기 제 1 절연막(22)과 고선택비를 얻을수 있다.In addition, a high selectivity with the first insulating film 22 can be obtained by forming a C x F y based polymer.
그리고 상기 콘택홀(26) 형성을 위한 건식식각 공정시 상기 O2가스는 1∼20sccm, CxFy가스는 5∼30sccm, Ar 가스는 0∼1000sccm, N2가스는 3∼200sccm, CHxFy가스는 1∼20sccm를 혼합주입하여 실시한다.In the dry etching process for forming the contact hole 26, the O 2 gas is 1 to 20 sccm, the C x F y gas is 5 to 30 sccm, the Ar gas is 0 to 1000 sccm, the N 2 gas is 3 to 200 sccm, and CH x The F y gas is carried out by mixing and injecting 1 to 20 sccm.
따라서, 상기 콘택홀(26) 형성시 균일한 형태를 갖게 되므로 후 공정에 있어서 접착성을 높이고, 신뢰성을 향상시킬 수 있다.Therefore, since the contact hole 26 is formed to have a uniform shape, it is possible to increase the adhesiveness in the post-process and to improve the reliability.
이상에서 설명한 바와 같이 본 발명의 반도체 장치의 콘택홀 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the contact hole forming method of the semiconductor device of the present invention has the following effects.
금속배선 형성시 RC 딜레이에 의한 스피드를 문제를 개선시키기 위해 하부 금속배선상에 형성되는 저유전체막에 있어서, 하부 금속배선이 소정부분 노출되도록 콘택홀 형성시 저유전체막 측면이 오버에치되어 발생하는 만곡 현상을 방지하므로 후 공정에 있어, 상부 금속배선 형성시 접착성을 향상시킬 수 있다.In the low dielectric film formed on the lower metal wiring to improve the speed caused by the RC delay when forming the metal wiring, the side of the low dielectric film is overetched when forming the contact hole so that the lower metal wiring is exposed to a predetermined portion. Since the bending phenomenon is prevented, it is possible to improve the adhesiveness at the time of forming the upper metal wiring in a later step.
따라서, 반도체 소자의 신뢰성 및 스피드를 향상시킬 수 있다.Therefore, the reliability and speed of a semiconductor element can be improved.
또한, CxFy계 폴리머 형성에 의해 하부 절연막과 고선택비를 얻을 수 있다.In addition, by forming the C x F y- based polymer, the lower insulating film and the high selectivity can be obtained.
Claims (10)
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| KR1019990064111A KR20010061614A (en) | 1999-12-28 | 1999-12-28 | Method for shame contact hole of semiconductor device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100780594B1 (en) * | 2001-11-19 | 2007-11-29 | 주식회사 하이닉스반도체 | Method of dry etching in semiconductor device |
| US8338861B2 (en) * | 2007-01-10 | 2012-12-25 | International Rectifier Corporation | III-nitride semiconductor device with stepped gate trench and process for its manufacture |
| CN103435003A (en) * | 2013-08-29 | 2013-12-11 | 上海宏力半导体制造有限公司 | Method for etching contact hole for MEMS (Micro Electro Mechanical Systems) AMR (Adaptive Multiple Rate) and method for manufacturing contact hole for MEMS AMR |
-
1999
- 1999-12-28 KR KR1019990064111A patent/KR20010061614A/en not_active Application Discontinuation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100780594B1 (en) * | 2001-11-19 | 2007-11-29 | 주식회사 하이닉스반도체 | Method of dry etching in semiconductor device |
| US8338861B2 (en) * | 2007-01-10 | 2012-12-25 | International Rectifier Corporation | III-nitride semiconductor device with stepped gate trench and process for its manufacture |
| CN103435003A (en) * | 2013-08-29 | 2013-12-11 | 上海宏力半导体制造有限公司 | Method for etching contact hole for MEMS (Micro Electro Mechanical Systems) AMR (Adaptive Multiple Rate) and method for manufacturing contact hole for MEMS AMR |
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