JP2001156169A - Manufacturing method for semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress minute voids produced in the connection parts between plugs and wiring grooves. SOLUTION: An etching stopper film 11 and an insulating film 12 are processed through dry-etching technology, so as to have the dry-etching rate of a plug 10 and the dry-etching rate of the etching stopper film 11 which is approximately equal to each other. For instance, a method, by which the type of the etching gas conforming to the dry-etching conditions is selected, is employed as a method for having the dry-etching rate of the plug 10 and the dry-etching rate of the etching stopper film 11 approximately equal to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly, to a technique for embedding a wiring conductive film in a wiring groove or a connection hole formed in an insulating film on a semiconductor substrate. The present invention relates to a technology which is effective when applied to a buried wiring technology.

[0002]

2. Description of the Related Art As a method of forming wiring of a semiconductor integrated circuit,
There is a process called the Damascene method.
In this method, after forming a wiring groove in an insulating film, a conductive film for forming a wiring is deposited on a main surface of the semiconductor substrate, and further,
A chemical mechanical polishing method (CM
P: Chemical Mechanical Polishing) to form a buried wiring in a groove for forming wiring. This method is particularly suitable as a method for forming an embedded wiring made of a copper-based conductor material (copper or copper alloy), which is difficult to perform fine etching.

[0003] As an application of the damascene method, there is a dual-damascene method. According to this method, after forming a groove for forming a wiring and a connection hole for making a connection with a lower layer wiring in an insulating film, a conductive film for forming a wiring is deposited on a main surface of the semiconductor substrate, and the groove is further formed. By removing the conductive film in a region other than the region by CMP, a buried wiring is formed in a wiring forming groove and a plug is formed in a connection hole. In the case of this method, particularly in a semiconductor integrated circuit having a multilayer wiring structure, the number of steps can be reduced, and the wiring cost can be reduced.

[0004] The wiring formation technology using such a damascene method is described in, for example, (1) K. Abe et.al, in Extended Abstracts 1994 SSD.
M, pp937-940 (2) Valery M. Dubin et.al, in Proceedings 1997 VM
IC, pp69-74.

The above-mentioned document (1) discloses a technique of forming a wiring groove in an insulating film, depositing copper by a sputtering method, and further performing a heat treatment to satisfactorily fill the wiring forming groove. . Further, the above-mentioned document (2) discloses a method in which copper is deposited by sputtering in wiring grooves and connection holes formed in an insulating film, and then copper is buried by plating.

[0006]

In the buried wiring technique, the following problem occurs when a plug for connection to a lower wiring is buried in a lower portion of a wiring groove.

[0007] That is, during the etching of the wiring groove processing, the insulating film is usually over-etched in order to make contact with the plug. Since the etching condition is usually a condition for etching only the insulating film, there may be a case where the plug metal is protruded to the bottom of the wiring groove due to overetching. Depending on the location, a minute concave portion may be formed between the side wall of the plug and the side wall of the wiring groove.

When a conductive film is buried in a wiring groove to form a wiring, if the sputter reflow method is used, the adhesion of the conductive film to the minute concave portion is poor, and the inside of the wiring groove is poor. In some cases, the coverage of the barrier conductor film covering the surface may be insufficient, or voids may occur because the conductive film does not enter the minute recesses.

Also, when a conductive film is buried in the wiring groove by electrolytic plating, a barrier conductor film must be formed, and a seed film must be formed by sputtering. . However, due to poor adhesion of the conductive film and the seed film to the minute concave portion, the coverage of the barrier conductor film covering the inner surface of the wiring groove is insufficient, or the conductive film is In some cases, voids are generated without entering the minute concave portions.

Furthermore, the voids may reduce the adhesion between the conductive film forming the wiring and the plug portion or cause migration of the wiring, and the void may be formed at the connection portion between the wiring and the plug. This causes the resistance to increase. In addition, the plurality of scattered voids and the elongated voids may be formed into a spherical shape by heat treatment, and the spherical voids may cause an increase in the resistance value of the wiring.

An object of the present invention is to provide a technique for preventing a plug from protruding from the bottom of a wiring groove to prevent insufficient coverage of a barrier conductor film and generation of voids when forming a conductive film. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) depositing a first insulating film on a main surface of a semiconductor substrate and etching the first insulating film to form a concave pattern such as a connection hole; (b) inside the connection hole Depositing a first conductive film for embedding a concave pattern such as the connection hole on the surface of the insulation film including: (c) removing the first conductive film outside the connection hole; Forming a plug or a wiring by leaving the first conductive film in the concave pattern such as the connection hole;
Depositing a second insulating film on the surface of the insulating film and the plug or the wiring, and (e) etching the second insulating film to form a wiring groove in the second insulating film above the plug or the wiring. (F) depositing a barrier conductor film on the surface of the second insulating film including the inside of the concave pattern such as the wiring groove, and (g) forming a concave pattern such as the wiring groove. Depositing a second conductive film for embedding a concave pattern such as the wiring groove on the surface of the barrier conductor film including the inside of the pattern; and (h) depositing a second conductive film outside the concave pattern such as the wiring groove. Forming a wiring by chemically and mechanically polishing the conductive film and the barrier conductive film to leave the barrier conductive film and the second conductive film in a concave pattern such as the wiring groove; .

According to the above-described method for manufacturing a semiconductor integrated circuit device, for example, the etching gas is used so that the dry etching rate of the second insulating film in which the wiring groove is formed and the plug immediately below the second insulating film are substantially the same. Since the type is selected, the bottom surface of the wiring groove is flush with the top surface of the plug.
Also, by selecting the type of etching gas so that the dry etching rates of the plug and the first insulating film around the plug become substantially the same, the bottom surface of the wiring groove and the top surface of the plug are flush with each other. become. Accordingly, it is possible to prevent the plug from being formed in a shape protruding at the bottom of the wiring groove, and to prevent a minute concave portion from being formed in a portion sandwiched between the side wall of the plug and the side wall of the wiring groove. . As a result, at the time of depositing the barrier conductor film or the conductive film, insufficient coverage of the barrier conductor film in the minute concave portion or the occurrence of voids due to insufficient coverage of the conductive film is prevented, and the conduction failure is reduced, The yield and reliability of the semiconductor integrated circuit device can be improved.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) In Embodiment 1, an n-channel MISFET (Metal
Insulator Semiconductor Field Effect Transistor)
The technical idea of the present invention is applied to a semiconductor integrated circuit device on which Qn is formed.

Hereinafter, a method of manufacturing the above-described semiconductor integrated circuit device will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 1, a selective oxidation method (L) is applied to the surface of a semiconductor substrate 1 made of p-type silicon single crystal.
After the field insulating film 2 for element isolation is formed by the OCOS method, a p-type impurity (for example, boron) is doped into the p-type well forming region of the semiconductor substrate 1 by ion implantation or the like to form a p-type impurity.
A well 3 is formed.

Next, a silicon oxide film serving as a gate insulating film 4, a polycrystalline silicon film serving as a gate electrode 5, and a silicon oxide film serving as a cap insulating film 6a are sequentially deposited on the main surface of the semiconductor substrate 1 to form a laminated film. Is formed, and the laminated film is etched using a resist patterned by photolithography as a mask to form a gate insulating film 4, a gate electrode 5, and a cap insulating film 6a. The gate insulating film 4 can be formed by, for example, a thermal CVD method, and the polycrystalline silicon constituting the gate electrode 5 can be formed by a CVD method. However, in order to reduce the resistance value, an n-type impurity (for example, Doping with phosphorus (P). Incidentally, WSi _x on the gate electrode 5, MoSi _x, Ti
Si _x, it may be stacked refractory metal silicide film such as TaSi _x or CoSi _x. Cap insulating film 6a
Can be formed by, for example, a CVD method.

Next, after a silicon oxide film is deposited on the semiconductor substrate 1 by the CVD method, reactive ion etching (RI
The silicon oxide film is anisotropically etched by the method E) to form sidewall spacers 6b on the side walls of the gate electrode 5, and ion-implant n-type impurities (phosphorus) to form p-wells on both sides of the gate electrode 5. 3 for n-channel MISF
A semiconductor region 7 constituting source and drain regions of ETQn is formed. Note that a low-concentration impurity semiconductor region may be formed before the formation of the sidewall spacer 6b, and a high-concentration impurity semiconductor region may be formed after the formation of the sidewall spacer 6b.

Next, after a silicon oxide film is deposited on the semiconductor substrate 1 by the CVD method, for example, the silicon oxide film is
By polishing by the P method, the insulating film 8 whose surface is flattened is formed. Further, a connection hole 9 is formed in the insulating film 8 on the semiconductor region 7 on the main surface of the semiconductor substrate 1 by using a photolithography technique.

Next, a barrier conductor film 10 of, for example, titanium nitride is formed on the semiconductor substrate 1 by sputtering.
Then, a conductor film 10b of, for example, tungsten is deposited by, for example, a blanket CVD method.

Next, the plug 10 is formed by removing the barrier conductor film 10a and the conductor film 10b on the insulating film 8 other than the connection holes 9 by, for example, the CMP method.

Next, a silicon nitride film is deposited on the semiconductor substrate 1 by, for example, a plasma CVD method to a thickness of about 50 nm.
An etch stopper film 11 of nm is formed. The etch stopper film 11 is used to prevent the lower layer from being damaged by excessive excavation or to prevent the processing dimensional accuracy from deteriorating when a trench or a hole for forming a wiring is formed in the insulating film on the upper layer. Things.

Next, as shown in FIG. 2, for example, a silicon oxide film is deposited on the surface of the etch stopper film 11 by a CVD method, and an insulating film 12 having a thickness of about 400 nm is deposited. The insulating film 12 is made of SOG (Spin O 2) deposited by a coating method.
n Glass) film, low dielectric constant film such as fluorine-doped CVD oxide film, silicon nitride film, or a combination of multiple types of insulating films may be used. In this method, the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be reduced, and the wiring delay can be improved.

Next, as shown in FIG. 3, the etch stopper film 11 and the insulating film 12 are processed by using the photolithography technique and the dry etching technique to form the wiring groove 13.
To form At the time of this dry etching, the bottom surface of the wiring groove 13 and the top surface of the plug 10 are formed by selecting, for example, the type of etching gas so that the dry etching rates of the plug 10 and the etch stopper film 11 are substantially the same. Become flush. Thereby, the wiring groove 1
3 to prevent the plug 10 from protruding from the bottom portion, and to prevent the side wall of the plug 10 and the wiring groove 1 from forming as shown in FIG.
It is possible to prevent the formation of the minute concave portion 100 sandwiched between the side walls 3 and 3. As a result, when depositing the barrier conductor film 14a or the conductive film 14b, which will be described later, the void 1 due to insufficient coverage of the barrier conductor film 14a in the minute recess 100 or insufficient coverage of the conductive film 14b.
01 can be prevented.

Next, as shown in FIG. 5, the barrier conductor film 14 of the buried wiring 14 to be described later is formed on the entire surface of the semiconductor substrate 1.
For example, a tantalum nitride film serving as a is deposited by performing reactive sputtering on a tantalum target in an argon / nitrogen mixed atmosphere. The tantalum nitride film is deposited for improving the adhesion of the copper film and preventing the diffusion of copper, which will be described later, and has a thickness of about 500 °. Although a tantalum nitride film is exemplified in the first embodiment, a metal film such as tantalum or a titanium nitride film may be used. When the barrier conductor film is tantalum or tantalum nitride, the adhesion to the copper film is better than when titanium nitride is used. When the barrier conductor film 14a is a titanium nitride film, the surface of the titanium nitride film can be sputter-etched immediately before the next step of forming the conductive film 14b. By such sputter etching, water, oxygen molecules and the like adsorbed on the surface of the titanium nitride film are removed,
The adhesiveness of the conductive film 14b can be improved. In particular, after deposition of the titanium nitride film, the effect is great when vacuum breaking is performed to expose the surface to the atmosphere to form the conductive film 14b.

Next, in another chamber in the same apparatus as the apparatus on which the tantalum nitride film is deposited, a thin film of copper, which is a metal to be the conductive film 14b, is deposited by a sputtering method, and this is heat-treated. And is buried well in the wiring groove 13 without any gap. If the surface of the tantalum nitride film is oxidized, the adhesion to the copper film is reduced. Therefore, the copper thin film is formed in another chamber connected in a vacuum or a specific oxidizing atmosphere in the same apparatus. Depositing prevents oxidation. In the first embodiment, the ordinary sputtering method is used for depositing the copper film, but a physical vapor deposition method such as an evaporation method or a plating method may be used. When the plating method is used, it is necessary to deposit a seed film before depositing a copper thin film, and this seed film is deposited by a sputtering method. In addition, the condition of the heat treatment requires a temperature and a time at which copper constituting the conductive film 14b is fluidized, and for example, 350 ° C. to 450 ° C., 3 minutes to 5 minutes can be exemplified. By using a material having a low resistivity as the main conductive layer, such as copper, an increase in wiring resistance due to miniaturization of the embedded wiring can be suppressed. This makes it possible to achieve higher performance of the semiconductor integrated circuit device.

Next, as shown in FIG.
The excess tantalum nitride film and copper film on the upper surface are removed, and a conductive film 14b and a barrier conductor film 14a forming the embedded wiring 14 are formed in the wiring groove 13. The removal of the barrier conductor film 14a and the conductive film 14b is performed by polishing using a CMP method.

Next, as shown in FIG. 7, a silicon nitride film is deposited on the buried wiring 14 and the insulating film 12, and a barrier insulating film 15a is deposited. For deposition of this silicon nitride film, for example, a plasma CVD method can be used, and its thickness is set to about 50 nm. The barrier insulating film 15a has a function of suppressing diffusion of copper forming the conductive film 14b of the embedded wiring 14. This prevents copper from diffusing into the insulating films 8 and 12 together with the barrier conductor film 14a and the insulating film 15 described later, retains their insulating properties, and improves the reliability of the semiconductor integrated circuit device. Further, the barrier insulating film 15a also functions as an etch stopper layer when performing etching in a later step. That is,
In a subsequent step, after opening the insulating film 15b by a resist process, the photoresist film is removed by ashing, and then the barrier insulating film 15a is patterned, so that the surface of the embedded wiring 17 is oxidized by an ashing atmosphere. It also has the effect of preventing such a situation.

Next, an insulating film 15b having a thickness of about 400 nm is deposited on the surface of the barrier insulating film 15a. The insulating film 15b is a SOG film deposited by a coating method, a low dielectric constant film such as a CVD oxide film doped with fluorine, a silicon nitride film, or a combination of a plurality of types of insulating films. Alternatively, when a low dielectric constant film is used, the overall dielectric constant of the wiring of the semiconductor integrated circuit device can be reduced, and the wiring delay can be improved.

Next, a silicon nitride film is deposited on the surface of the insulating film 15b by, for example, a plasma CVD method, and an etch stopper film 15c having a thickness of about 50 nm is deposited. The etch stopper film 15c is used to prevent the lower layer from being damaged by excessive excavation and to prevent the processing dimensional accuracy from deteriorating when a groove or a hole for forming a wiring is formed in the insulating film 15. is there.

Subsequently, an SOG film having a thickness of about 300 nm is deposited on the surface of the insulating film 15c by a coating method.
By depositing d, an insulating film 15 is formed. This insulating film 15
d may be a low dielectric constant film such as a CVD oxide film to which fluorine is added, a silicon nitride film, or a combination of a plurality of types of insulating films. The insulating film 1
When 5d is an SOG film, a silicon oxide film having a thickness of about 100 nm is deposited on the surface of the insulating film 15d by, for example, a plasma CVD method using TEOS (Tetraethoxysilane) gas to form an insulating film 15e. I do. The insulating film 15e has a function of ensuring the mechanical strength of the insulating film 15d which is an organic film.

Next, as shown in FIG. 8, a connection hole 16a for connecting the buried wiring 14 as a lower wiring and the buried wiring 17 as an upper wiring formed in a later step is formed. . The connection hole 16a is formed by forming a photoresist film having the same shape as a connection hole pattern for connecting to the embedded wiring 14 on the insulating film 15e by a photolithography process,
Using this as a mask, a connection hole pattern is formed by a dry etching process. At the time of this dry etching, for example, the conditions of the type of the etching gas are selected so that the dry etching rates of the buried wiring 14 and the barrier insulating film 15a are substantially the same.
The bottom surface of 6a is flush with the top surface of the embedded wiring 14. This suppresses the embedded wiring 14 from protruding at the bottom of the connection hole 16a and forms a minute concave portion sandwiched between the side wall of the embedded wiring 14 and the side wall of the connection hole 16a. Can be prevented. As a result, when depositing the barrier conductor film 17a and the conductive film 17b to be formed in a later step, voids due to insufficient coverage of the barrier conductor film 17a in the minute concave portions and insufficient coverage of the conductive film 17b. Occurrence can be prevented. Subsequently, the photoresist film is removed, a photoresist film having the same shape as the wiring groove pattern is formed on the insulating film 15e by a photolithography process, and the wiring groove 16b is formed by a dry etching process using the photoresist film as a mask. .

Next, as shown in FIG. 9, in the same step as the step of depositing the tantalum nitride film for forming the barrier conductor film 14a, the insulating film 15 including the surfaces of the connection holes 16a and the wiring grooves 16b is formed. A tantalum nitride film to be a barrier conductor film 17a is deposited on the surface of the substrate. This tantalum nitride film is deposited to improve the adhesion of the copper film deposited in a later step and to prevent the diffusion of copper.
Å. Although a tantalum nitride film is exemplified in the first embodiment, a metal film such as tantalum or a titanium nitride film may be used. When the barrier conductor film 17a is a titanium nitride film, the surface of the titanium nitride film can be sputter-etched immediately before the formation of the conductive film 17b in the next step.

Subsequently, a thin film of copper, which is a metal to be the conductive film 17b, is deposited by a sputtering method in another chamber in the same apparatus as that for depositing the tantalum nitride film to be the barrier conductor film 17a. , Heat-treat it and fluidize it,
It is satisfactorily embedded in the connection hole 16a and the wiring groove 16b without any gap. In the first embodiment, the ordinary sputtering method is used for depositing the copper film, but a physical vapor deposition method such as an evaporation method or a plating method may be used. The heat treatment requires a temperature and a time at which copper constituting the conductive film 17b is fluidized.
Minutes to 5 minutes.

Next, as shown in FIG.
Excess tantalum nitride film and copper film on 5e are removed by polishing using a CMP method, and conductive film 17b and barrier conductor film 17a forming embedded wiring 17 in connection hole 16a and wiring groove 16b are removed. Thus, the semiconductor integrated circuit device according to the first embodiment is almost completed.

In the first embodiment, the plug 10 can be prevented from projecting to the bottom of the wiring groove 13 by making the etching rate of the plug 10 substantially equal to the etching rate of the etching stopper film 11. As a result, insufficient coverage of the barrier conductor film 14a and generation of minute voids 100 when the conductive film 14b is formed can be suppressed. Also, by making the etching rate of the embedded wiring 14 substantially equal to the etching rate of the barrier insulating film 15a, insufficient coverage of the barrier conductor film 17a and generation of minute voids at the bottom of the connection hole 16a can be suppressed. Accordingly, conduction defects can be reduced, and the yield and reliability of the semiconductor integrated circuit device can be improved.

(Embodiment 2) In the method of manufacturing a semiconductor integrated circuit device according to the second embodiment, the dry etching rate is substantially equal to that of the plug 10 on the surface of the insulating film 8 of the semiconductor integrated circuit device according to the first embodiment. An insulating film of the same material and lower than the etch stopper film 11 is formed.
The technical idea of the present invention is used to form an insulating film having a dry etching rate substantially equal to that of the buried wiring 14 and a material lower than that of the barrier insulating film 15a on the surface of the substrate 2. Other members and steps are the same as those in the first embodiment. Therefore, description of those similar members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIGS.

The method of manufacturing the semiconductor integrated circuit device of the second embodiment is the same as that of the first embodiment up to the step of forming the insulating film 8 in FIG.

Next, as shown in FIG. 11, an insulating film 8a is deposited on the surface of the insulating film 8. The material of the insulating film 8a is selected so that the dry etching rate is substantially the same as that of the plug 10 and lower than that of the etch stopper film 11 in an etching step of forming the wiring groove 13 in a later step. In an etching step for forming the wiring groove 13 in a later step, an etching gas is selected so that the dry etching rate of the insulating film 8a is substantially the same as that of the plug 10 and lower than the etching stopper film 11. According to the configuration of the second embodiment, the insulating film 8a can be used as an etch stopper without using the etch stopper film 11, which is particularly effective when copper is not used for the plug 10.

Thereafter, connection holes 9 are formed in the same steps as those in FIG. 1 in the first embodiment, and the steps up to the step in FIG. 2 are the same as those in the first embodiment.

Next, as shown in FIG. 12, an insulating film 12a is deposited on the surface of the insulating film 12. This insulating film 12a
In the etching step of forming the connection hole 16a in a later step, the material is selected so that the dry etching rate is substantially the same as that of the embedded wiring 14 and lower than the barrier insulating film 15a. In an etching step for forming the connection hole 16a in a later step, the dry etching rate of the connection hole 16a is substantially the same as that of the buried wiring 14, and the barrier insulating film 1 is formed.
The etching gas is selected so as to be lower than 5a.

The subsequent steps are the same as in FIGS. 3 to 10 in the first embodiment.

According to the second embodiment, by forming on the surface of the insulating film 8 an insulating film 8a having a dry etching rate substantially equal to that of the plug 10 and lower than the etch stopper film 11, the plug 10 is connected to the wiring. Projection to the bottom of the groove 13 can be prevented. As a result, insufficient coverage of the barrier conductor film 14a as shown in FIG. 14A and generation of minute voids 100 when the conductive film 14b is formed can be suppressed. Also, by forming an insulating film 12a on the surface of the insulating film 12 having a dry etching rate substantially equal to that of the buried wiring 14 and lower than the barrier insulating film 15a, insufficient coverage of the barrier conductor film 17a and the formation of the connection hole 1
Since the generation of minute voids at the bottom of 6a is suppressed,
It is possible to reduce conduction defects and improve the yield and reliability of the semiconductor integrated circuit device.

Third Embodiment In a method of manufacturing a semiconductor integrated circuit device according to a third embodiment, the diameter of the top of the plug 10 is made larger than the width of the bottom of the wiring groove 13, and the side wall of the wiring groove 13 is formed. Is to make contact with the plug 10. The width of the uppermost portion of the embedded wiring 14 is made larger than the diameter of the bottom of the connection hole 16a, and the side wall of the connection hole 16a is
In order to make contact with No. 4, the technical idea of the present invention is used. Other members and processes are the same as those in the first embodiment.
Or the same as 2. Therefore, description of those similar members and steps will be omitted.

Next, a method of manufacturing the above-described semiconductor integrated circuit device will be described with reference to FIG.

The method of manufacturing the semiconductor integrated circuit device of the third embodiment is the same as that of the first or second embodiment.
As shown in FIG. 13, the diameter of the uppermost part of the plug 10 is made larger than the width of the bottom part of the wiring groove 13. Further, the width of the uppermost part of the wiring groove 13 is made larger than the diameter of the bottom part of the connection hole 16a.

According to the third embodiment, the diameter of the top of the plug 10 is made larger than the width of the bottom of the wiring groove 13, and the bottom of the side wall of the wiring groove 13 is brought into contact with the top of the plug 10. In addition, it is possible to prevent a minute concave portion from being formed over the entire circumference of the uppermost portion of the plug 10, and to suppress the growth into a large void even if a minute void is formed when the embedded wiring 14 is formed. The embedded wiring 14 and the connection hole 16a
In the contact portion, the width of the top of the embedded wiring 14 is made larger than the diameter of the bottom of the connection hole 16a, and the bottom of the side wall of the connection hole 16a is brought into contact with the top of the embedded wiring 14 so that the embedding is performed. Insufficient coverage of the barrier conductor film 17a at the time of forming the wiring 17 and generation of minute voids at the bottom of the connection hole 16a can be suppressed. Further, the method for manufacturing a semiconductor integrated circuit device according to the third embodiment is combined with the method for manufacturing a semiconductor integrated circuit device according to the first embodiment or the method for manufacturing a semiconductor integrated circuit device according to the second embodiment. It is possible to more effectively reduce the conduction failure than in the first and second embodiments, and to improve the yield and reliability of the semiconductor integrated circuit device.

[0053]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.

(1) It is possible to prevent the plug from protruding from the bottom of the wiring groove and to suppress insufficient coverage of the barrier metal in the wiring groove and generation of minute voids when forming the conductive film. .

(2) Even if the plug protrudes at the bottom of the wiring groove, the way of protruding is eased to prevent the formation of a minute concave portion over the entire periphery of the uppermost portion of the plug. Even if voids are formed, growth into large voids can be suppressed.

(3) The occurrence of voids at the connection between the plug and the wiring groove can be suppressed, conduction defects can be reduced, and the yield and reliability of the semiconductor integrated circuit device can be improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1 in the order of steps;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 1;

3 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 2;

FIG. 4 is a cross-sectional view of a main part for explaining generation of minute concave portions and voids.

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5;

7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9;

FIG. 11 is an essential part cross sectional view showing an example of a method of manufacturing a semiconductor integrated circuit device of Embodiment 2 in the order of steps;

12 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 11;

FIG. 13 is an essential part cross sectional view showing a connection part between a plug and an embedded wiring of the semiconductor integrated circuit device of the third embodiment;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 field insulating film 3 p well 4 gate insulating film 5 gate electrode 6a cap insulating film 6b sidewall spacer 7 semiconductor region 8 insulating film 8a insulating film 9 connecting hole 10 plug 10a barrier conductive film 10b conductive film 11 etch stopper film REFERENCE SIGNS LIST 12 insulating film 12 a insulating film 13 wiring groove 14 buried wiring 14 a barrier conductor film 14 b conductive film 15 insulating film 15 a barrier insulating film 15 b insulating film 15 c insulating film 15 d insulating film 15 e insulating film 16 a connection hole 16 b wiring groove 17 embedded wiring 17a barrier conductor film 17b conductive film 100 recess 101 void Qn n-channel MISFET

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) SS15 TT02 VV06 XX02 XX09 XX13 XX14 XX23 XX27 XX28

Claims (6)

[Claims] (A) depositing a first insulating film on a main surface of a semiconductor substrate and etching the first insulating film to form a concave pattern such as a connection hole; Depositing a first conductive film for embedding a concave pattern such as the connection hole on the surface of the insulating film including the inside of the hole; (c) removing the first conductive film outside the connection hole Forming a plug or a wiring by leaving the first conductive film in the concave pattern such as the connection hole, and (d) forming a second insulating film and a second surface on the plug or the wiring.
(E) etching the second insulating film to form a concave pattern such as a wiring groove in the second insulating film above the plug or the wiring, and (f).
Depositing a barrier conductor film on the surface of the second insulating film including the inside of the concave pattern such as the wiring groove; and (g) forming a barrier conductor film on the surface of the barrier conductor film including the inside of the concave pattern such as the wiring groove. Depositing a second conductive film filling the wiring groove, and (h) chemically and mechanically polishing the second conductive film and the barrier conductive film outside the concave pattern such as the wiring groove. Forming a wiring by leaving the barrier conductive film and the second conductive film in the concave pattern such as the wiring groove. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein when the second insulating film is a single-layer film or a laminated film, at least a lowermost layer of the second insulating film. A method for manufacturing a semiconductor integrated circuit device, wherein an etching rate is substantially the same as that of the first conductive film. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein when the first insulating film is a single-layer film or a laminated film, at least the first insulating film has A method of manufacturing a semiconductor integrated circuit device, wherein an etching rate of an upper layer is substantially the same as an etching rate of a first conductive film forming the plug and the like. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film and said second insulating film are a single-layer film or a stacked film. Wherein the etching rate of at least the uppermost layer of the first insulating film is lower than the etching rate of the second insulating film. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a width of said wiring groove at a portion where said plug contacts said plug is larger than a diameter of an upper end of said plug. A method of manufacturing a semiconductor integrated circuit device, wherein the method is small. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said first insulating film, said second insulating film, and said first conductive film are provided. Wherein the etching rate is controlled by selecting an etching gas.