KR100313529B1 - Wiring forming method for semiconductor device - Google Patents
Wiring forming method for semiconductor device Download PDFInfo
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- KR100313529B1 KR100313529B1 KR1019990053457A KR19990053457A KR100313529B1 KR 100313529 B1 KR100313529 B1 KR 100313529B1 KR 1019990053457 A KR1019990053457 A KR 1019990053457A KR 19990053457 A KR19990053457 A KR 19990053457A KR 100313529 B1 KR100313529 B1 KR 100313529B1
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- contact
- film
- metal barrier
- forming
- barrier film
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 230000004888 barrier function Effects 0.000 claims abstract description 40
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 31
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 31
- 239000010937 tungsten Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 238000000206 photolithography Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 229920000642 polymer Polymers 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 3
- 238000007796 conventional method Methods 0.000 abstract description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체소자의 컨택 형성방법에 관한 것으로, 종래 반도체소자의 컨택 형성방법은 비트라인과 컨택의 전기적 접합은 컨택 하부면과의 접촉에 의지하므로 제 2산화막을 식각하면서 컨택홀 하부에 잔류하는 잔존폴리머의 영향으로 그 상부에 제 2금속 배리어막이 완전하게 증착되지 않고, 그 상부에 증착되는 제 2텅스텐막 또한 완전하게 증착되지 않아 오픈이 발생하는 문제점이 있었다. 따라서 본 발명은 소자가 형성된 반도체기판 상에 차례로 제 1산화막, 제 1금속 배리어막, 제 1텅스텐막, 제 2산화막을 증착하는 제 1공정과; 상기 형성한 제 2산화막, 제 1텅스텐막, 제 1금속 배리어막 및 제 1산화막의 일부를 사진식각공정을 통해 식각하여 컨택홀을 형성하는 제 2공정과; 상기 형성한 구조물의 상부전면에 제 2금속 배리어막을 형성하는 제 3공정과; 상기 형성한 제 2금속 배리어막의 상부 전면에 제 2텅스텐막을 형성하고 상기 제 2금속 배리어막이 드러나도록 평탄화한 후 그 구조물 상부 전면에 금속배선을 형성하는 제 4공정으로 이루어지는 반도체소자의 컨택 형성방법을 통해 컨택홀을 깊이 형성하여 컨택의 하부 측면이 비트라인과 완전히 접촉하도록 함으로써 컨택 하부에 식각 잔류물이 있더라도 비트라인과 완전한 전기적 접합을 이룰 수 있어 오픈불량을 방지할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact of a semiconductor device. In the conventional method of forming a contact of a semiconductor device, since the electrical contact between the bit line and the contact depends on the contact with the bottom surface of the contact, the second oxide film is etched and remains under the contact hole. Due to the influence of the remaining polymer, the second metal barrier film is not completely deposited thereon, and the second tungsten film deposited thereon is also not completely deposited. Accordingly, the present invention comprises a first step of depositing a first oxide film, a first metal barrier film, a first tungsten film, and a second oxide film on a semiconductor substrate on which a device is formed; A second step of forming a contact hole by etching a portion of the formed second oxide film, first tungsten film, first metal barrier film and first oxide film through a photolithography process; A third step of forming a second metal barrier film on an upper surface of the formed structure; And forming a second tungsten film on the entire upper surface of the formed second metal barrier film, and planarizing the second metal barrier film to expose the second metal barrier film, and then forming a metal wiring on the upper surface of the structure. Through deep contact hole formation, the bottom side of the contact is completely in contact with the bit line, so that even if there is an etching residue on the bottom of the contact, a complete electrical connection with the bit line can be prevented, thereby preventing open defects.
Description
본 발명은 반도체소자의 컨택 형성방법에 관한 것으로, 특히 금속배선과 비트라인을 연결하는 컨택형성에 있어서 비트라인과 컨택간의 오픈발생을 억제시키는데 적당하도록 한 반도체소자의 컨택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device, and more particularly, to a method for forming a contact in a semiconductor device suitable for suppressing open occurrence between a bit line and a contact in forming a contact connecting a metal wiring and a bit line.
종래 반도체소자의 컨택 형성방법을 도 1a 내지 도 1d의 수순단면도를 참고하여 설명하면 다음과 같다.A method of forming a contact of a conventional semiconductor device will be described below with reference to the procedure cross-sectional view of FIGS. 1A to 1D.
소자가 형성된 반도체기판(1) 상에 차례로 제 1산화막(2), 제 1금속 배리어막(3), 제 1텅스텐막(4), 제 2산화막(5)을 증착하는 제 1공정과; 상기 형성한 제 2산화막(5) 및 제 1텅스텐막(4)의 일부를 사진식각공정을 통해 식각하여 컨택홀을 형성하는 제 2공정과; 상기 형성한 구조물의 상부전면에 제 2금속 배리어막(7)을 형성하는 제 3공정과; 상기 형성한 제 2금속 배리어막(7)의 상부 전면에 제 2텅스텐막(8)을 형성하고 상기 제 2금속 배리어막(7)이 드러나도록 평탄화 한 후 그 구조물 상부 전면에 금속배선(9)을 형성하는 제 4공정으로 이루어진다.A first step of depositing a first oxide film (2), a first metal barrier film (3), a first tungsten film (4), and a second oxide film (5) on a semiconductor substrate (1) on which the device is formed; A second step of forming a contact hole by etching part of the formed second oxide film 5 and the first tungsten film 4 through a photolithography process; A third step of forming a second metal barrier film (7) on the upper surface of the formed structure; A second tungsten film 8 is formed on the entire upper surface of the formed second metal barrier film 7, and the planarized to expose the second metal barrier film 7, and then the metal wiring 9 is formed on the entire upper surface of the structure. The fourth step of forming a.
먼저, 도 1a에 도시한 바와 같이 소자가 형성된 반도체기판(1) 상에 차례로 제 1산화막(2), 제 1금속 배리어막(3), 제 1텅스텐막(4), 제 2산화막(5)을 증착한다.First, as shown in FIG. 1A, a first oxide film 2, a first metal barrier film 3, a first tungsten film 4, and a second oxide film 5 are sequentially formed on a semiconductor substrate 1 on which elements are formed. Deposit.
이때, 상기 제 1금속 배리어막(3)은 티타늄/티타늄질화막으로 이루어져 상기 제 1텅스텐막(4)이 제 1산화막(2)과 반응하는 것을 막아주고 접착력을 높인다.In this case, the first metal barrier layer 3 is made of titanium / titanium nitride layer to prevent the first tungsten layer 4 from reacting with the first oxide layer 2 and to increase adhesion.
그리고, 상기 제 2산화막(5)은 두껍게 증착한다.The second oxide film 5 is thickly deposited.
그 다음, 도 1b에 도시한 바와 같이 상기 형성한 제 2산화막(5) 및 제 1텅스텐막(4)의 일부를 사진식각공정을 통해 식각하여 컨택홀을 형성한다.Next, as shown in FIG. 1B, a part of the formed second oxide film 5 and the first tungsten film 4 is etched through a photolithography process to form a contact hole.
이때, 상기 두꺼운 제 2산화막(5)을 식각하면서 잔존폴리머(6)가 상기 형성하는 컨택홀의 하부에 쌓이게 되며 이는 세정공정 후에도 잔존하게 된다.At this time, while the thick second oxide film 5 is etched, the remaining polymer 6 accumulates in the lower portion of the contact hole to be formed, which remains even after the cleaning process.
그 다음, 도 1c에 도시한 바와 같이 상기 형성한 구조물의 상부전면에 제 2금속 배리어막(7)을 형성한다.Next, as illustrated in FIG. 1C, a second metal barrier layer 7 is formed on the upper front surface of the formed structure.
이때, 상기 제 2금속 배리어막(7)은 티타늄/티타늄질화막으로 형성되어 후속공정에서 형성될 제 2텅스텐막(8)이 제 2산화막(5)과 반응하는 것을 막아주며 접착력을 높인다.In this case, the second metal barrier layer 7 is formed of a titanium / titanium nitride layer to prevent the second tungsten layer 8 to be formed in a subsequent process from reacting with the second oxide layer 5 and to increase adhesion.
그 다음, 도 1d에 도시한 바와 같이 상기 형성한 제 2금속 배리어막(7)의 상부 전면에 제 2텅스텐막(8)을 형성하고 상기 제 2금속 배리어막(7)이 드러나도록 평탄화 한 후 그 구조물 상부 전면에 금속배선(9)을 형성한다.Next, as shown in FIG. 1D, a second tungsten film 8 is formed on the entire upper surface of the formed second metal barrier film 7 and planarized so that the second metal barrier film 7 is exposed. The metal wiring 9 is formed on the upper surface of the structure.
이때, 상기 금속배선(9)은 티타늄/알루미늄/티타늄/티타늄질화막으로 형성된다.In this case, the metal wiring 9 is formed of titanium / aluminum / titanium / titanium nitride film.
그리고, 상기 제 1텅스텐막(4)으로 이루어진 비트라인과 제 2텅스텐막(8)으로 이루어진 컨택과의 접합은 상기 컨택의 하부접촉면에 의지한다.The contact between the bit line made of the first tungsten film 4 and the contact made of the second tungsten film 8 relies on the bottom contact surface of the contact.
상기한 바와같은 종래 반도체소자의 컨택 형성방법은 비트라인과 컨택의 전기적 접합은 컨택 하부면과의 접촉에 의지하므로 제 2산화막을 식각하면서 컨택홀 하부에 잔류하는 잔존폴리머의 영향으로 그 상부에 제 2금속 배리어막이 완전하게 증착되지 않고, 그 상부에 증착되는 제 2텅스텐막 또한 완전하게 증착되지 않아 오픈이 발생하는 문제점이 있었다.In the method of forming a contact of a conventional semiconductor device as described above, since the electrical contact between the bit line and the contact depends on the contact with the contact lower surface, the second polymer layer is etched on the upper portion due to the residual polymer remaining under the contact hole while etching the second oxide film. The second metal barrier film is not completely deposited, and the second tungsten film deposited thereon is also not completely deposited, resulting in a problem of opening.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 컨택의 측면이 비트라인과 접촉하도록 함으로써 완전한 전기적 접합을 형성하여 오픈불량을 방지할 수 있는 반도체소자의 컨택 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to form a complete electrical junction by contacting the side of the contact with the bit line to form a contact between the semiconductor device that can prevent open defects It is to provide a formation method.
도 1은 종래 반도체소자의 컨택 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for forming a contact of a semiconductor device.
도 2는 본 발명의 수순단면도.2 is a cross-sectional view of the procedure of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 제 1산화막21 semiconductor substrate 22 first oxide film
23 : 제 1금속 배리어막 24 : 제 1텅스텐막23: first metal barrier film 24: first tungsten film
25 : 제 2산화막 26 : 잔존폴리머25: second oxide film 26: remaining polymer
27 : 제 2금속 배리어막 28 : 제 2텅스텐막27: second metal barrier film 28: second tungsten film
29 : 금속배선29 metal wiring
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 컨택 형성방법은 소자가 형성된 반도체기판 상에 차례로 제 1산화막, 제 1금속 배리어막, 제 1텅스텐막, 제 2산화막을 증착하는 제 1공정과; 상기 형성한 제 2산화막, 제 1텅스텐막, 제 1금속 배리어막 및 제 1산화막의 일부를 사진식각공정을 통해 식각하여 컨택홀을 형성하는 제 2공정과; 상기 형성한 구조물의 상부전면에 제 2금속 배리어막을 형성하는 제 3공정과; 상기 형성한 제 2금속 배리어막의 상부 전면에 제 2텅스텐막을 형성하고 상기 제 2금속 배리어막이 드러나도록 평탄화한 후 그 구조물 상부 전면에 금속배선을 형성하는 제 4공정으로 이루어진다.In order to achieve the object of the present invention as described above, a method for forming a contact of a semiconductor device includes a first method of depositing a first oxide film, a first metal barrier film, a first tungsten film, and a second oxide film on a semiconductor substrate on which the device is formed. Process; A second step of forming a contact hole by etching a portion of the formed second oxide film, first tungsten film, first metal barrier film and first oxide film through a photolithography process; A third step of forming a second metal barrier film on an upper surface of the formed structure; A fourth process is performed by forming a second tungsten film on the entire upper surface of the formed second metal barrier film, planarizing the second metal barrier film to be exposed, and forming a metal wiring on the entire upper surface of the structure.
상기한 바와 같은 본 발명에의한 반도체소자의 컨택 형성방법을 도 2a 내지 도 2d에 도시한 수순단면도를 일 실시예로하여 상세히 설명하면 다음과 같다.The method for forming a contact of a semiconductor device according to the present invention as described above will be described in detail with reference to a cross-sectional view of the procedure shown in FIGS. 2A to 2D as an example.
먼저, 도 2a에 도시한 바와 같이 소자가 형성된 반도체기판(21) 상에 차례로 제 1산화막(22), 제 1금속 배리어막(23), 제 1텅스텐막(24), 제 2산화막(25)을 증착한다.First, as shown in FIG. 2A, the first oxide film 22, the first metal barrier film 23, the first tungsten film 24, and the second oxide film 25 are sequentially formed on the semiconductor substrate 21 on which the elements are formed. Deposit.
이때, 상기 제 1금속 배리어막(23)은 티타늄/티타늄질화막으로 이루어져 상기 제 1텅스텐막(24)이 제 1산화막(22)과 반응하는 것을 막아주고 접착력을 높인다.In this case, the first metal barrier layer 23 is made of titanium / titanium nitride layer to prevent the first tungsten layer 24 from reacting with the first oxide layer 22 and to increase adhesion.
그리고, 상기 제 2산화막(25)은 두껍게 증착한다.The second oxide film 25 is thickly deposited.
그 다음, 도 2b에 도시한 바와 같이 상기 형성한 제 2산화막(25), 제 1텅스텐막(24), 제 1금속 배리어막(23) 및 제 1산화막(22)의 일부를 사진식각공정을 통해 식각하여 컨택홀을 형성한다.Subsequently, as shown in FIG. 2B, a part of the second oxide film 25, the first tungsten film 24, the first metal barrier film 23, and the first oxide film 22 formed thereon is subjected to a photolithography process. Etch through to form contact holes.
이때, 상기 두꺼운 제 2산화막(5)을 식각하면서 잔존폴리머(6)가 형성되는 컨택홀의 하부에 쌓이게 되며 이는 세정공정 후에도 잔존하게 되지만 이는 컨택홀의 하부가 위치한 제 1산화막(22) 부근에 위치한다.At this time, the thick second oxide film 5 is etched and accumulated in the lower portion of the contact hole where the remaining polymer 6 is formed, which remains after the cleaning process, but is located near the first oxide layer 22 where the lower portion of the contact hole is located. .
그 다음, 도 2c에 도시한 바와 같이 상기 형성한 구조물의 상부전면에 제 2금속 배리어막(27)을 형성한다.Next, as shown in FIG. 2C, a second metal barrier layer 27 is formed on the upper front surface of the formed structure.
이때, 상기 제 2금속 배리어막(27)은 티타늄/티타늄질화막으로 형성되어 후속공정에서 형성될 제 2텅스텐막(28)이 제 1,제 2산화막(22,25)과 반응하는 것을 막아주며 접착력을 높인다.At this time, the second metal barrier layer 27 is formed of a titanium / titanium nitride layer to prevent the second tungsten layer 28 to be formed in a subsequent process from reacting with the first and second oxide layers 22 and 25 and has an adhesive force. Increase
또한, 상기 제 2금속 배리어막(27)은 상기 제 1텅스텐막(24) 및 제 1금속 배리어막(23)과 완전하게 접촉한다.In addition, the second metal barrier layer 27 is completely in contact with the first tungsten layer 24 and the first metal barrier layer 23.
그 다음, 도 2d에 도시한 바와 같이 상기 형성한 제 2금속 배리어막(27)의 상부 전면에 제 2텅스텐막(28)을 형성하고 상기 제 2금속 배리어막(27)이 드러나도록 평탄화 한 후 그 구조물 상부 전면에 금속배선(29)을 형성한다.Next, as shown in FIG. 2D, a second tungsten film 28 is formed on the entire upper surface of the formed second metal barrier film 27 and planarized so that the second metal barrier film 27 is exposed. The metal wiring 29 is formed on the upper surface of the structure.
이때, 상기 금속배선(29)은 티타늄/알루미늄/티타늄/티타늄질화막으로 형성한다.In this case, the metal wire 29 is formed of a titanium / aluminum / titanium / titanium nitride film.
그리고, 상기 제 1텅스텐막(24)으로 이루어진 비트라인과 제 2텅스텐막(28)으로 이루어진 컨택과의 접합은 상기 컨택의 하부측면에서 전기적으로 완전하게 접합한다.The bit line formed of the first tungsten film 24 and the contact made of the second tungsten film 28 are electrically connected to each other at the lower side of the contact.
상기한 바와 같이 본 발명 반도체소자의 컨택 형성방법은 컨택홀을 깊이 형성하여 컨택의 하부 측면이 비트라인과 완전히 접촉하도록 함으로써 컨택 하부에 식각 잔류물이 있더라도 비트라인과 완전한 전기적 접합을 이룰 수 있어 오픈불량을 방지할 수 있는 효과가 있다.As described above, the method for forming a contact of the semiconductor device of the present invention forms a contact hole so that the bottom side of the contact is completely in contact with the bit line, so that even if there is an etch residue at the bottom of the contact, the electrical contact with the bit line is open. There is an effect that can prevent the defect.
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| KR1019990053457A KR100313529B1 (en) | 1999-11-29 | 1999-11-29 | Wiring forming method for semiconductor device |
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| KR1019990053457A KR100313529B1 (en) | 1999-11-29 | 1999-11-29 | Wiring forming method for semiconductor device |
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