KR100338941B1 - Contact forming method for semiconductor device - Google Patents
Contact forming method for semiconductor device Download PDFInfo
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- KR100338941B1 KR100338941B1 KR1019990052961A KR19990052961A KR100338941B1 KR 100338941 B1 KR100338941 B1 KR 100338941B1 KR 1019990052961 A KR1019990052961 A KR 1019990052961A KR 19990052961 A KR19990052961 A KR 19990052961A KR 100338941 B1 KR100338941 B1 KR 100338941B1
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- Prior art keywords
- film
- forming
- tungsten
- contact hole
- contact
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000000034 method Methods 0.000 title claims abstract description 19
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 53
- 239000010937 tungsten Substances 0.000 claims abstract description 53
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 51
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- 239000002184 metal Substances 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 238000009832 plasma treatment Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 abstract description 3
- 238000007796 conventional method Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 230000002401 inhibitory effect Effects 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- -1 tungsten nitride Chemical class 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
본 발명은 반도체소자의 컨택 형성방법에 관한 것으로, 종래 반도체소자의 컨택 형성방법은 상하부 금속배선을 전기적으로 연결하는 층간 컨택의 단차가 커질수록 그 기하학적 형상 때문에 컨택홀의 개구부에 텅스텐막이 우선적으로 성장함으로써 그 컨택홀의 개구부를 막아 컨택홀 내 텅스텐 매립율이 낮아져 평탄화 공정에서 텅스텐막이 과다식각되므로 상부 금속배선 형성시 평탄도 불량을 야기하고, 텅스텐막과 상부 금속배선과의 접합이 완전하지 못하게 되어 오픈 또는 높은 접촉저항을 유발하므로 제품에 치명적인 영향을 주는 문제점이 있었다. 따라서 본 발명은 소자가 형성된 반도체기판 상에 소자와 연결되는 도전막을 형성하고, 그 상부에 절연막을 증착한 후 상기 도전막의 일부가 드러나도록 식각하여 컨택홀을 형성한 다음 상기 구조물 상부전면에 금속배리어막을 형성하는 제 1공정과; 상기 형성한 금속배리어막 상부에 텅스텐의 성장을 억제할 수 있는 가스를 플라즈마처리하여 플라즈마처리막을 형성하는 제 2공정과; 상기 형성한 구조물의 상부 전면에 텅스텐막을 형성하는 제 3공정과; 상기 형성한 텅스텐막을 상기 플라즈마처리막이 드러나도록 에치백하여 평탄화하는 제 4공정과; 상기 형성한 구조물 상부 전면에 금속배선을 형성하는 제 5공정으로 이루어지는 반도체소자의 컨택 형성방법을 통해 컨택홀 내부의 텅스텐막 매립율을 높여 상부금속배선의 평탄도를 높일 수 있음과 아울러 텅스텐막과 상부 금속배선의 오픈을 방지하고 접촉저항을 줄여 제품의 신뢰성을 높일 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact of a semiconductor device. In the conventional method of forming a contact of a semiconductor device, a tungsten film is preferentially grown in an opening of a contact hole due to its geometric shape as the step height of an interlayer contact electrically connecting upper and lower metal interconnections increases. Tungsten buried in the contact hole is lowered by blocking the opening of the contact hole, and the tungsten film is excessively etched in the planarization process, resulting in poor flatness when forming the upper metal wiring, and incomplete bonding between the tungsten film and the upper metal wiring. Since it causes high contact resistance there was a problem that has a fatal effect on the product. Therefore, the present invention forms a conductive film connected to the device on the semiconductor substrate on which the device is formed, deposits an insulating film thereon, and forms a contact hole by etching a portion of the conductive film to expose the metal barrier on the upper surface of the structure. A first step of forming a film; A second step of forming a plasma treatment film by plasma treating a gas capable of suppressing tungsten growth on the formed metal barrier film; A third step of forming a tungsten film on the entire upper surface of the formed structure; A fourth step of etching and flattening the formed tungsten film so that the plasma treatment film is exposed; Through the method of forming a semiconductor device in the fifth step of forming a metal wiring on the upper surface of the structure, the filling rate of the tungsten film inside the contact hole can be increased to increase the flatness of the upper metal wiring and the tungsten film and It prevents the upper metal wiring from opening and reduces the contact resistance, which increases the reliability of the product.
Description
본 발명은 반도체소자의 컨택 형성방법에 관한 것으로, 특히 금속 배선간 연결을 위한 텅스텐 컨택을 형성함에 있어서 국부적으로 텅스텐의 성장을 억제하여 컨택홀 내부의 텅스텐 매립율(Step Coverage)을 향상시키기에 적당하도록 한 반도체소자의 컨택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact of a semiconductor device, and particularly suitable for improving tungsten embedding (Step Coverage) inside a contact hole by locally suppressing tungsten growth in forming a tungsten contact for connection between metal wires. A contact forming method of a semiconductor device is provided.
종래 반도체소자의 컨택 형성방법을 도 1a 내지 도 1d의 수순단면도를 참고하여 설명하면 다음과 같다.A method of forming a contact of a conventional semiconductor device will be described below with reference to the procedure cross-sectional view of FIGS. 1A to 1D.
소자가 형성된 반도체기판(1) 상에 소자와 연결되는 도전막(2)을 형성하고, 그 상부에 절연막(3)을 증착한 후 상기 도전막(2)의 일부가 드러나도록 식각하여 컨택홀을 형성한 다음 상기 구조물 상부전면에 금속배리어막(4)을 형성하는 제 1공정과; 상기 형성한 금속배리어막(4)의 상부 전면에 텅스텐막(5)을 형성하는 제 2공정과; 상기 형성한 텅스텐막(5)을 상기 금속배리어막(4)이 드러나도록 에치백하여 평탄화하는 제 3공정과; 상기 형성한 구조물 상부 전면에 금속배선(6)을 형성하는 제 4공정으로 이루어진다.A conductive film 2 is formed on the semiconductor substrate 1 on which the device is formed, and an insulating film 3 is deposited thereon, and then a portion of the conductive film 2 is etched to expose the contact hole. Forming a metal barrier film (4) on the upper surface of the structure; A second step of forming a tungsten film (5) on the entire upper surface of the formed metal barrier film (4); A third step of etching and flattening the formed tungsten film 5 so that the metal barrier film 4 is exposed; The fourth step of forming a metal wiring 6 on the upper surface of the formed structure.
먼저, 도 1a에 도시한 바와 같이 소자가 형성된 반도체기판(1) 상에 소자와 연결되는 도전막(2)을 형성하고, 그 상부에 절연막(3)을 증착한 후 상기 도전막(2)의 일부가 드러나도록 식각하여 컨택홀을 형성한 다음 상기 구조물 상부전면에 금속배리어막(4)을 형성한다.First, as shown in FIG. 1A, a conductive film 2 connected to the device is formed on the semiconductor substrate 1 on which the device is formed, and an insulating film 3 is deposited thereon. A portion of the structure is etched to expose the contact hole, and then a metal barrier film 4 is formed on the upper surface of the structure.
이때, 상기 도전막(2)은 도전성 폴리실리콘이거나 하부 금속배선이고, 상기 금속배리어막(4)은 텅스텐막(5)과 절연막(3)이 반응하는 것을 방지하며 접착성을 높이는 역할을 하고 티타늄질화막(TiN), 텅스텐질화막(WN), 탄탈륨질화막(TaN) 등의 질소계 금속을 이용한다.At this time, the conductive film 2 is conductive polysilicon or a lower metal wiring, and the metal barrier film 4 prevents the tungsten film 5 and the insulating film 3 from reacting, and increases the adhesiveness. Nitrogen-based metals such as nitride film (TiN), tungsten nitride film (WN), and tantalum nitride film (TaN) are used.
그 다음, 도 1b에 도시한 바와 같이 상기 형성한 금속배리어막(4)의 상부 전면에 텅스텐막(5)을 화학기상증착방식(CVD)으로 형성한다.Then, as shown in FIG. 1B, a tungsten film 5 is formed on the upper entire surface of the formed metal barrier film 4 by chemical vapor deposition (CVD).
이때, 상기 텅스텐막(5)을 화학기상증착방식으로 컨택홀에 채우는 방법은 스퍼터링(sputtering)방법등에 비해 매립율이 높고 열적안정성이 우수하지만 컨택홀의 기하학적 형상 때문에 텅스텐이 컨택홀의 개구부에 우선 성장하여 그 개구부를 막아버리기 때문에 컨택홀 내부에서 텅스텐막(5)의 매립율은 낮으며 보이드가 형성된다.In this case, the method of filling the contact hole with the chemical vapor deposition method has a higher filling rate and thermal stability than the sputtering method, but tungsten is first grown in the opening of the contact hole due to the geometric shape of the contact hole. Since the opening is blocked, the filling rate of the tungsten film 5 is low and voids are formed in the contact hole.
그 다음, 도 1c에 도시한 바와 같이 상기 형성한 텅스텐막(5)을 상기 금속배리어막(4)이 드러나도록 에치백하여 평탄화한다.Next, as shown in Fig. 1C, the formed tungsten film 5 is etched back to expose the metal barrier film 4 and planarized.
이때, 상기와 같이 에치백하면 컨택홀 내부에는 텅스텐막(5)의 밀도가 낮기 때문에 과다식각이 일어나 표면과의 단차가 커진다..At this time, when etched back as described above, since the density of the tungsten film 5 is low inside the contact hole, excessive etching occurs, thereby increasing the step difference from the surface.
그 다음, 도 1d에 도시한 바와 같이 상기 형성한 구조물 상부 전면에 금속배선(6)을 형성한다.Next, as shown in FIG. 1d, the metal wiring 6 is formed on the entire upper surface of the formed structure.
이때, 상기 표면과 단차가 큰 텅스텐막(5) 상부와 금속배선(6)과의 접합이 완전하지 못하게 되므로 오픈되거나 접촉저항이 커지고, 그 단차에 의해 상기 금속배선(6)은 평탄하지 못하게 형성된다.At this time, since the junction between the upper surface of the tungsten film 5 having a large step height and the metal wiring 6 is not completed, the contact resistance increases due to the step difference, and the metal wiring 6 is not formed flat. do.
상기한 바와같은 종래 반도체소자의 컨택 형성방법은 상하부 금속배선을 전기적으로 연결하는 층간 컨택의 단차가 커질수록 그 기하학적 형상 때문에 컨택홀의 개구부에 텅스텐막이 우선적으로 성장함으로써 그 컨택홀의 개구부를 막아 컨택홀 내 텅스텐 매립율이 낮아져 평탄화 공정에서 텅스텐막이 과다식각되므로 상부 금속배선 형성시 평탄도 불량을 야기하고, 텅스텐막과 상부 금속배선과의 접합이 완전하지 못하게 되어 오픈 또는 높은 접촉저항을 유발하므로 제품에 치명적인 영향을 주는 문제점이 있었다.According to the conventional method of forming a contact of a semiconductor device as described above, the tungsten film is preferentially grown in the opening of the contact hole due to its geometric shape as the step height of the interlayer contact electrically connecting the upper and lower metal wirings is increased, thereby blocking the opening of the contact hole and blocking the opening of the contact hole. The tungsten embedding rate is lowered and the tungsten film is overetched in the planarization process, causing flatness defects when forming the upper metal wiring, and incomplete bonding between the tungsten film and the upper metal wiring, causing open or high contact resistance. There was an issue that affected.
본 발명은 상기한 바와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 컨택홀을 텅스텐막으로 채우기 전에 웨이퍼 상부 및 컨택홀의 개구부에만 국부적으로 텅스텐성장을 억제시킴으로써 컨택홀 내부의 텅스텐막 매립율을 높일 수 있는 반도체소자의 컨택 형성방법을 제공하는데 있다.The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to prevent tungsten growth in the contact hole by locally suppressing tungsten growth only at the top of the wafer and the opening of the contact hole before filling the contact hole with the tungsten film. It is an object of the present invention to provide a method for forming a contact for a semiconductor device capable of increasing a film filling rate.
도 1은 종래 반도체소자의 컨택 형성방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for forming a contact of a semiconductor device.
도 2는 본 발명의 수순단면도.2 is a cross-sectional view of the procedure of the present invention.
*** 도면의 주요부분에 대한 부호의 설명 ****** Explanation of symbols for main parts of drawing ***
21 : 반도체기판 22 : 도전체층21 semiconductor substrate 22 conductor layer
23 : 절연막 24 : 금속배리어막23 insulating film 24 metal barrier film
25 : 플라즈마처리막 26 : 텅스텐막25 plasma treatment film 26 tungsten film
27 : 금속배선27 metal wiring
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 컨택 형성방법은 소자가 형성된 반도체기판 상에 소자와 연결되는 도전막을 형성하고, 그 상부에 절연막을 증착한 후 상기 도전막의 일부가 드러나도록 식각하여 컨택홀을 형성한 다음 상기 구조물 상부전면에 금속배리어막을 형성하는 제 1공정과; 상기 형성한 금속배리어막 상부에 텅스텐의 성장을 억제할 수 있는 가스를 플라즈마처리하여 플라즈마처리막을 형성하는 제 2공정과; 상기 형성한 구조물의 상부 전면에 텅스텐막을 형성하는 제 3공정과; 상기 형성한 텅스텐막을 상기 플라즈마처리막이 드러나도록에치백하여 평탄화하는 제 4공정과; 상기 형성한 구조물 상부 전면에 금속배선을 형성하는 제 5공정으로 이루어지는 것을 특징으로 한다.The contact forming method of a semiconductor device for achieving the object of the present invention as described above is to form a conductive film connected to the device on the semiconductor substrate on which the device is formed, so that a portion of the conductive film is exposed after depositing an insulating film thereon Forming a contact hole by etching and forming a metal barrier film on the upper surface of the structure; A second step of forming a plasma treatment film by plasma treating a gas capable of suppressing tungsten growth on the formed metal barrier film; A third step of forming a tungsten film on the entire upper surface of the formed structure; A fourth step of etching and flattening the formed tungsten film so that the plasma treatment film is exposed; Characterized in that the fifth step of forming a metal wiring on the upper surface of the formed structure.
상기한 바와 같은 본 발명에의한 반도체소자의 컨택 형성방법을 도 2a 내지 도 2e에 도시한 수순단면도를 일 실시예로하여 상세히 설명하면 다음과 같다.A method of forming a contact of a semiconductor device according to the present invention as described above will be described in detail with reference to a cross-sectional view of the procedure shown in FIGS. 2A to 2E as an example.
먼저, 도 2a에 도시한 바와 같이 소자가 형성된 반도체기판(21) 상에 소자와 연결되는 도전막(22)을 형성하고, 그 상부에 절연막(23)을 증착한 후 상기 도전막(22)의 일부가 드러나도록 식각하여 컨택홀을 형성한 다음 상기 구조물 상부전면에 금속배리어막(24)을 형성한다.First, as shown in FIG. 2A, a conductive film 22 connected to the device is formed on the semiconductor substrate 21 on which the device is formed, and an insulating film 23 is deposited thereon, and then the conductive film 22 is formed. A portion of the structure is etched to form a contact hole, and then a metal barrier layer 24 is formed on the upper surface of the structure.
이때, 상기 도전막(22)은 도전성 폴리실리콘이거나 하부 금속배선이고, 상기 금속배리어막(24)은 텅스텐막(26)과 절연막(23)이 반응하는 것을 방지하며 접착성을 높이는 역할을 하고 티타늄질화막(TiN), 텅스텐질화막(WN), 탄탈륨질화막(TaN) 등의 질소계 금속을 이용한다.In this case, the conductive film 22 is conductive polysilicon or a lower metal wiring, and the metal barrier film 24 prevents the tungsten film 26 and the insulating film 23 from reacting, and serves to improve adhesion and titanium. Nitrogen-based metals such as nitride film (TiN), tungsten nitride film (WN), and tantalum nitride film (TaN) are used.
그 다음, 도 2b에 도시한 바와 같이 상기 형성한 금속배리어막(24) 상부에 텅스텐의 성장을 억제할 수 있는 가스를 플라즈마처리하여 플라즈마처리막(25) 을 형성한다.Next, as shown in FIG. 2B, a plasma treatment film 25 is formed by plasma treatment of a gas capable of suppressing tungsten growth on the formed metal barrier film 24.
이때, 상기 텅스텐의 성장을 억제할 수 있는 가스는 질소(N2) 또는 산소(O2)를 사용하며 플라즈마 효과 때문에 컨택홀의 내부에는 N과 O가 침투하지 못하므로 상기 금속배리어막(24)의 상부 및 컨택홀의 개구부에 질소(N)농도가 높은 질화물이나 산소(O)의 농도가 높은 산화물을 형성한다.In this case, the gas capable of inhibiting the growth of tungsten uses nitrogen (N 2 ) or oxygen (O 2 ), and N and O do not penetrate the inside of the contact hole due to the plasma effect. Nitrogen having a high concentration of nitrogen (N) or oxide having a high concentration of oxygen (O) is formed in the upper portion and the opening of the contact hole.
상기 플라즈마처리막(25)은 질소(N) 또는 산소(O)가 다량 함유된 금속배리어막(24)을 의미한다.The plasma treatment film 25 refers to a metal barrier film 24 containing a large amount of nitrogen (N) or oxygen (O).
그 다음, 도 2c에 도시한 바와 같이 상기 형성한 구조물의 상부 전면에 텅스텐막(26)을 화학기상증착방식으로 형성한다.Next, as illustrated in FIG. 2C, a tungsten film 26 is formed on the upper front surface of the formed structure by chemical vapor deposition.
이때, 상기 플라즈마처리막(25)이 형성된 웨이퍼의 표면과 컨택홀의 개구부는 텅스텐의 성장이 늦어지고, 상대적으로 플라즈마 성장억제 물질이 적은 컨택홀의 내부에서는 텅스텐의 성장속도가 빠르므로 텅스텐막(26)의 매립율이 우수해진다.At this time, the surface of the wafer on which the plasma processing film 25 is formed and the opening of the contact hole are slow in tungsten growth, and the growth rate of tungsten is fast in the contact hole where the plasma growth inhibitory material is relatively low. The filling rate of becomes excellent.
그 다음, 도 2d에 도시한 바와 같이 상기 형성한 텅스텐막(26)을 상기 플라즈마처리막(25)이 드러나도록 에치백하여 평탄화한다.Next, as shown in Fig. 2D, the formed tungsten film 26 is etched back to expose the plasma processing film 25 and planarized.
이때, 상기 컨택홀을 채우고 있는 텅스텐막(26)의 매립율이 우수하여 그 밀도는 웨이퍼 표면에 노출된 텅스텐막(26)과 비슷하므로 에치백에 의한 과다식각은 발생하지 않는다.At this time, since the filling rate of the tungsten film 26 filling the contact hole is excellent, and the density thereof is similar to that of the tungsten film 26 exposed on the wafer surface, the overetching by the etch back does not occur.
그 다음, 도 2e에 도시한 바와 같이 상기 형성한 구조물 상부 전면에 금속배선(27)을 형성한다.Next, as shown in Figure 2e to form a metal wiring 27 on the upper surface of the formed structure.
이때, 상기 컨택을 형성하는 텅스텐막(26)은 매립율이 높아 상기 에치벡과정에서 높은 평탄도를 유지하므로 그 상부 금속배선(27)의 평탄도 역시 우수하고, 상기 텅스텐막(26)과 금속배선(27)은 완전하게 접촉하므로 접촉저항이 낮아진다.In this case, the tungsten film 26 forming the contact has a high filling rate and thus maintains high flatness in the etch back process, so that the flatness of the upper metal wiring 27 is also excellent, and the tungsten film 26 and the metal Since the wiring 27 is completely in contact, the contact resistance is lowered.
상기한 바와 같이 본 발명 반도체소자의 컨택 형성방법은 텅스텐막 증착 전 에 웨이퍼 상부를 텅스텐 성장억제 가스로 플라즈마 처리하여 웨이퍼 상부 및 컨택홀의 개구부에서 텅스텐의 성장이 둔화되도록 함으로써 컨택홀 내부의 텅스텐막 매립율을 높여 상부금속배선의 평탄도를 높일 수 있음과 아울러 텅스텐막과 상부 금속배선의 오픈을 방지하고 접촉저항을 줄여 제품의 신뢰성을 높일 수 있는 효과가 있다.As described above, in the method of forming a contact of the semiconductor device according to the present invention, the tungsten film is buried in the contact hole by slowing the growth of tungsten at the top of the wafer and the opening of the contact hole by plasma treatment of the top of the wafer with the tungsten growth inhibitory gas before the deposition of the tungsten film. By increasing the ratio, the flatness of the upper metal wiring can be increased, and the tungsten film and the upper metal wiring can be prevented from opening and the contact resistance is reduced to increase the reliability of the product.
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| KR1019990052961A KR100338941B1 (en) | 1999-11-26 | 1999-11-26 | Contact forming method for semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100757418B1 (en) * | 2006-09-05 | 2007-09-10 | 삼성전자주식회사 | Semiconductor device and methods of forming the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100457057B1 (en) * | 2002-09-14 | 2004-11-10 | 삼성전자주식회사 | Method for forming a metal layer in semiconductor fabricating |
| KR100457038B1 (en) * | 2002-09-24 | 2004-11-10 | 삼성전자주식회사 | Method for forming a self align contact in semiconductor device and manufacturing a semiconductor device using for same |
| US10256142B2 (en) | 2009-08-04 | 2019-04-09 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
| US11437269B2 (en) | 2012-03-27 | 2022-09-06 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
| JP6195898B2 (en) * | 2012-03-27 | 2017-09-13 | ノベラス・システムズ・インコーポレーテッドＮｏｖｅｌｌｕｓ Ｓｙｓｔｅｍｓ Ｉｎｃｏｒｐｏｒａｔｅｄ | Feature filling with tungsten with nucleation inhibition |
| KR102131581B1 (en) | 2012-03-27 | 2020-07-08 | 노벨러스 시스템즈, 인코포레이티드 | Tungsten feature fill |
| US9997405B2 (en) | 2014-09-30 | 2018-06-12 | Lam Research Corporation | Feature fill with nucleation inhibition |
| US10170320B2 (en) | 2015-05-18 | 2019-01-01 | Lam Research Corporation | Feature fill with multi-stage nucleation inhibition |
| US10573522B2 (en) | 2016-08-16 | 2020-02-25 | Lam Research Corporation | Method for preventing line bending during metal fill process |
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| JPH07115130A (en) * | 1993-10-14 | 1995-05-02 | Toshiba Corp | Manufacture of semiconductor device |
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| JPH07115130A (en) * | 1993-10-14 | 1995-05-02 | Toshiba Corp | Manufacture of semiconductor device |
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| KR100757418B1 (en) * | 2006-09-05 | 2007-09-10 | 삼성전자주식회사 | Semiconductor device and methods of forming the same |
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