JPS6072248A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain multilayer wiring of high reliability by a method wherein an insulation film on the lower layer wiring is provided with an aperture, an insulation film being superposed on the wiring, side wall, and upper peripheral edge via barrier metal, and the upper layer wiring being then applied by the opening of a through hole at the same position. CONSTITUTION:An SiO2 film 4 is superposed on the poly Si wiring 3 on the oxide film 2 on an Si substrate 1, and the through hole is provided. Then, a Ti film 7 is formed on the exposed wiring 3, hole side wall, and upper peripheral edge, and a CVDSiO2 film 5 are superposed; thereafter a through hole is provided at the same position as the first through hole, resulting in the formation of the Al upper layer wiring 8. In this construction, the barrier metal 7 serves as an etching stopper at the time of forming the second through hole, and eaves are not generated. Since the metal 7 is completely covered with an SiO2 film 5 and the upper layer wiring 8, it does not generate cavities by the etching in patterning the wiring 8. Therby, the multilayer wiring of high quality suitable for miniaturization and having high yield can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a multilayer wiring structure and a method for manufacturing the same.

[Prior art]

In order to increase the degree of integration of semiconductor devices and to increase the wiring density, it is necessary to perform multilayer wiring. However, in normal multilayer wiring, the upper layer wiring crosses the lower layer wiring, so the upper layer wiring may be disconnected due to the step difference in the lower layer wiring, or the thickness may become thinner at the stepped portion, which is a major hindrance to realizing multilayer wiring. Therefore, it is necessary to flatten the glabella insulating film formed on the lower wiring.

One of the planarization techniques is the silica coating method.By applying 7-liquid solution on the lower wiring and heat-treating it, it is possible to make the silicon oxide film in a state with good overall flatness. Since the film thickness of the first insulating film alone is insufficient, a method is known in which a silicon oxide film is further grown by vapor phase growth to form a two-layer structure and a flat and thick interlayer insulating film.

FIG. 1 is a cross-sectional view of a semiconductor device having a conventional multilayer interconnection structure during a manufacturing process.

An oxide film 2 and a lower wiring 3 are sequentially formed on a semiconductor substrate 1, and an interlayer insulating film consisting of two layers, a first insulating film 4 and a second insulating film 5, is formed. The first insulating film 4 is formed by applying the above-mentioned CRIKA solution and heat treatment, and the second insulating film 5 is formed by vapor phase growth. When forming through holes in this two-layered glabella insulating film by isotropic etching using hydrofluoric acid, etc., the first
When the eaves 6 is formed on the second insulating film 4 and the upper layer wiring is formed to pass through the surface of the second insulating film 5 and reach the through hole, a break in the upper layer wiring occurs.

If anisotropic etching is performed using a gas such as CF4 in order to prevent the formation of the eaves 6, no eaves will be formed in the through holes as shown in FIG.

However, even in the structure shown in Figure 2, if the lower layer wiring and the upper layer wiring are made of different wiring materials, it is necessary to form seven barrier metal layers between the two wirings, and as shown in Figure 3, barrier metal layers must be formed. In order to completely cover the through hole with layer 7, a pattern larger than the through hole is formed, and the barrier metal layer completely covers it, and upper layer wiring 8 is formed on it, so a large area is required for integration. This is causing a hindrance to development.

FIG. 4 is a cross-sectional view of an example in which the upper layer wiring 8 does not completely cover the barrier metal layer. In such a case, the etching speed of the barrier metal layer 7 is generally faster than that of the upper layer wiring 8, so when the upper layer wiring 8 is formed by etching, the barrier metal layer 7 is also etched together with the upper layer wiring, leaving a cavity. Part 9
This has the drawback of reducing yield or reliability.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor device having a multilayer wiring structure with high yield, high quality, and suitable for miniaturization, and a method for manufacturing the same.

[Structure of the invention]

A semiconductor device according to a first aspect of the present invention is a semiconductor device having a multilayer wiring structure, which includes at least a lower layer wiring made of a first material, a first insulating film covering the lower layer wiring, and a semiconductor device selectively disposed in the insulating film. a first through hole that is formed and reaches the lower wiring; a barrier metal layer that covers the side wall of the lower wiring part exposed by the first through hole and the upper peripheral edge of the through hole; le'
a second insulating film, a second through hole provided in the second insulating film at the same position as the first through hole and reaching the surface of the barrier metal layer;
and an upper layer wiring made of a second material formed on the surface including through holes.

A method for manufacturing a semiconductor device according to a second aspect of the present invention is a method for manufacturing a semiconductor device having a multilayer wiring/line structure, including the step of forming a lower layer wiring made of a first material on an insulating film;
forming a first insulating film on at least the entire surface of the lower wiring; forming a first through-pole in the first insulating film that reaches the surface of the lower wiring; and exposing through the first through-hole. a step of selectively forming a barrier metal layer to cover the lower wiring portion, a side wall of the through hole, and an upper peripheral edge of the through hole; a step of completely forming a second insulating film so as to cover at least the barrier metal layer; forming a second through hole reaching the surface of the barrier metal layer at the same position as the first through hole provided in the first insulating film in the insulating film; and a surface including the second through hole. and a step of forming an upper layer wiring υ of a second material.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a sectional view of an embodiment of the semiconductor device of the first invention.

A lower wiring 3 made of a first layer of polycrystalline silicon formed on an oxide film 2 on a semiconductor substrate 1, a first insulating film 4 made of, for example, a silica coating film covering the lower wiring 3, and a first insulating film 4 made of a silica coated film, for example. A first through hole reaching the lower layer wiring 3 selectively formed in the insulating film 4, the lower layer wiring portion exposed by the first through hole, the side wall of the through hole, and the first insulating film 4 at the periphery of the through hole. and a second layer of CVD5iO, for example, formed on the surface including the barrier metal layer 7.
an insulating film 5, a second through hole provided in the second insulating film 5 at the same position as the first through pole and reaching the surface of the barrier metal layer 7, and a surface including the second through hole. The upper layer wiring 8 is formed of a second material of aluminum.

In the above embodiment, polycrystalline silicon was used for the lower wiring 3 and aluminum was used for the upper wiring 8, but the first invention is not limited to the combination of this embodiment, and various wiring materials can be used. Further, as the barrier metal, although Ti is used, W or the like can be used in addition to Ti, and a material suitable for the above-mentioned combination wiring material can be used. Furthermore, although a silica coated film was used as the first insulating film and CVD8i02 was used as the second insulating film, the materials of the first insulating film and the second insulating film may be reversed, and other material combinations may be used as well. It can be effective.

As explained above, in the embodiment of the first invention, the first
After forming the insulating film 4, a through hole is formed, the through hole portion is covered with a barrier metal layer 7, and the barrier metal layer 7 is completely covered with the second insulating film. Provided so that the end portion of the barrier gold M layer 7O is not exposed,
The second through hole is covered with upper layer wiring. Therefore, when forming the second through-hole, the barrier metal layer 7 covers the side wall of the bottom wall portion of the first insulating film 4, and since the barrier metal layer 7 acts as an etching stopper, the eaves portion is covered. It never forms. In addition, the barrier metal layer 7
Since it is completely covered by the second insulating film 5 and the upper layer wiring 8, the barrier metal layer is etched during patterning of the upper layer wiring 8, resulting in a decrease in yield and quality due to the formation of a cavity. No.

Conventionally, in order to prevent the barrier metal layer 7 from being exposed, it was necessary to etch the upper layer wiring 8 at a position far away from the edge of the barrier metal layer, which made it impossible to miniaturize the device. Since the barrier metal layer 7 is under the second insulating film 5, the upper layer wiring can be formed in a range that covers the second through hole, so the degree of freedom in patterning the upper layer wiring is increased, which is effective for high integration. It's large.

Further, if a high melting point metal such as titanium or tungsten is used as the barrier metal layer and the barrier metal layer is not used for wiring but serves only as a barrier, the thickness may be about 100 OA. Therefore, after the formation of the second insulating film, there are few occurrences of undulations due to the barrier metal layer, and this does not cause a decrease in yield and reliability.

Next, an embodiment of the second aspect of the present invention will be described with reference to FIGS. 6 and 7.

As shown in FIG. 6, an oxide film 2 is formed on a semiconductor substrate l on which a semiconductor element region is formed, and a first
Polycrystalline 7 silicon, which is a material of the above, is deposited and patterned to form the lower layer wiring 3.

Next, a silica liquid is applied and baked to form the first insulating film 4. Since the first insulating film was formed by coating and baking, the stepped portion can be flattened as shown. Next, a strip line reaching the lower layer wiring 3 is formed.

Next, as shown in FIG.
Approximately 100% titanium film is applied as a barrier metal layer to the surface including the metal.
The barrier metal layer 7 is formed by depositing a layer of about 0^ and patterning it to sufficiently cover the first hole. Next, a CVD5 iOt film with a thickness of about 5,000 ml is deposited on the surface as a second insulating film 5.
Attach about A level. Next, using the photomask used to form the first through hole, a second through hole is formed at the same position where the first snort hole was formed by photoetching. At this time, since the barrier metal layer is also formed on the periphery of the upper surface of the through hole so as to sufficiently cover the first through hole, the second through hole is formed inside the outer periphery of the attached barrier metal/FJ 7. The outer periphery of the barrier metal is completely enclosed in the first insulating film 4 and the second insulating film 5, even though it is not formed. Therefore, when forming the second through hole, the barrier metal layer 7 acts as an etching stopper, and an appropriate through hole can be formed in the second insulating film. Therefore, naturally, the insulating film of box 1 is not etched.

Next, as shown in FIG. 5, an aluminum film is deposited on the surface including the second through hole and patterned to form the upper layer wiring 8. In this way, a semiconductor device having a multilayer wiring structure according to the first invention is obtained.

As explained above, the semiconductor device of the first invention can be obtained by the second invention, and the effects of the first invention and the effects explained in the process description can be obtained.

In addition, the photomask for forming the second droplet hole can be used as it is for forming the first droplet hole, making positioning easy and also effective in terms of cost reduction. be.

〔Effect of the invention〕

As described above, according to the present invention, a semiconductor device having a multilayer wiring made of two or more types of wiring materials that is high in yield, high in quality, and suitable for miniaturization can be obtained, and can be easily manufactured.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device having a conventional multilayer interconnection structure during a manufacturing process; FIGS. 2 and 3 are cross-sectional views of a semiconductor device having a conventional multilayer interconnection structure during another manufacturing process; The figure is a cross-sectional view showing a conventional semiconductor device in which part of the barrier metal is etched during upper layer wiring patterning, FIG. 5 is a cross-sectional view of an embodiment of the semiconductor device of the first invention, and FIG. 7 and 7 are cross-sectional views shown in the order of steps to explain an embodiment of the second fH, U semiconductor device manufacturing method. ...Oxide film, 3
... lower layer wiring, 4 ... first insulating film,
5...Second insulating film, 6...Eave portion, 7...Barrier metal layer, 8...Upper layer wiring, 9...・Cavity. Mei / Fig. 22 Fig. 3 Fig. Atsushi 4 z 6 5 Wa z 6 Fig. z 7 Fig. ke / 75 4

Claims (2)

[Claims] (1) A lower wiring made of a first material provided on a semiconductor substrate on which a semiconductor element region is formed via an oxide film, a first insulating film covering the lower wiring, and a first insulating film covering the lower wiring; a first through hole that is selectively formed in the insulating film and reaches the lower layer wiring; a barrier metal layer that covers the lower layer wiring portion exposed by the through holes w and l, the side wall of the through hole, and the upper peripheral edge of the through hole; , a second insulating film formed on a surface including the barrier metal layer; and a second insulating film provided in the second insulating film at the same position as the first through hole and reaching the surface of the barrier metal layer. a second through hole;
and an upper layer wiring made of a second material formed on a surface including through holes. (2) Forming a lower layer wiring made of a first material via an oxide film on a semiconductor substrate on which a semiconductor element region is formed, and forming a first insulating film that covers at least the entire surface of the lower layer wiring. a step of forming a first through hole different from the lower wiring surface in the first insulating film;
a step of selectively forming a through-hole metal layer, a step of forming a second insulating film to cover at least the barrier metal layer, and a step of forming a through-hole metal layer on the first insulating film in the second insulating film. forming a second through hole reaching the surface of the barrier metal layer at the same position as the first through hole; and forming an upper layer wiring made of a second material on the surface including the second through hole. A method for manufacturing a semiconductor device, comprising: