JPS63172445A - Method for forming multilayer interconnection - Google Patents

Abstract

PURPOSE:To prevent the disconnection of a second wiring metal, by forming a contact hole on an insulating layer which is formed on a lower wiring pattern, and forming a material which readily reacts with a growing gas for embedded metal in the contact hole. CONSTITUTION:A first insulating layer 2 and a second insulating layer 2' are formed on a semiconductor substrate 1, on which an element is formed. Then, a lift-off material 13 made of e.g., PSG, whose etching rate is faster than that of the insulating layer 2', is formed. An etching window 14' is formed. Then an oxide film 7 on a first wiring metal 3 is removed. For example a tungsten (W) film 15, which readily reacts with a growing gas for an embedded metal 9, is evaporated. The lift-off material 13 is removed, and an etching mask 14 and the film 15 on the insulating film layer 2' are lifted off. The embedded layer metal 9 is grown in a vapor phase by using WF6 gas. Even if the insulating layer 2 is exposed at the bottom surface of a contact hole 8 due to its deviation, the metal 9 grows from the entire bottom surface of the hole 8 since the film 15 is provided on the layer 2. The disconnection of a wiring metal 3' can be prevented.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a method for forming a multilayer wiring in which a buried metal is buried in a contact hole by selective growth. In order to prevent this, an insulating layer is formed directly on the lower wiring pattern, a contact hole is formed in the insulating layer, the oxide film of the lower wiring metal exposed inside the insulating layer is removed, and then the inner surface of the contact hole is This forms a material film that easily reacts with the growth gas of the buried metal.

[Industrial application field]

The present invention relates to a semiconductor device, a manufacturing method, and particularly a method for forming multilayer wiring thereof.

[Prior Art] An example of a conventional method for forming multilayer wiring will be explained with reference to FIG. 2. In this example, a buried metal is selectively buried in a contact hole by vapor phase growth. FIG. 2 is a sectional view showing the process in order.

The method for forming the multilayer wiring in this example is as shown in FIG. A buffer metal 4 made of, for example, tungsten (W) for reducing the contact resistance between this and a buried metal 9 formed in a later process, and a buffer metal from a later dry etching process. A protective film 5 made of Al, for example, for protecting each of the substrates 4 is formed by, for example, a normal sputtering process.

Next, as shown in FIG. 2(B), the wiring metal 3, buffer metal 4, and protective film 5 are patterned by a normal lithography process.

Next, as shown in FIG. 2C, a second insulating layer 2' made of, for example, PSG is formed by, for example, a normal vapor phase growth method. In this case, wiring metal 3. Buffer metal 4. An oxide film 7 is formed on the surface of the protective film 5.

Next, as shown in FIG. 2(D), an etching mask 6 made of, for example, a resist is formed and contact holes are patterned, and then dry etching is performed using, for example, a CFa-based gas to selectively form a second etching mask. The contact hole 8 is formed by removing the insulating layer 2' and then removing the oxide film 7 and the protective film 5 by, for example, HF-based wet etching as shown in FIG. 2(E).

Next, as shown in FIG. 2(F), a buried metal 9 made of, for example, tungsten (W) is grown in a vapor phase using, for example, a WF and gas system. In general, the second insulator N2' made of PSG, for example, has strong bonds between its constituent atoms and does not react with the growth gas of the buried metal 9, so it is actually exposed inside the contact hole 8. The embedded metal 9 can be selectively grown only on the buffer metal 4 that is present.

Next, as shown in FIG. 2(G), a second wiring metal 3' made of, for example, AI is formed on the second insulating layer 2', and then patterned by a normal lithography process. .

[Problem that the invention seeks to solve]

Normally, in multilayer wiring, as shown in FIG. 3A, a pad 11 having a width l is provided, for example, in order to provide alignment margin for a contact pattern IO having a width l'. However, it is conceivable that this will be abolished in the future due to miniaturization of wiring patterns as shown in FIG. 3(B).

However, when the pad 11 for alignment margin is eliminated, if the contact pattern 10 deviates from the wiring pattern 12, the conventional multilayer wiring method described above will cause
As shown in A), after the contact hole 8 is formed, the first insulating layer 2 made of, for example, PSG formed in the previous step is exposed on the bottom surface thereof. Like the second insulating layer 2', this first insulating layer 2 has strong bonds between its constituent atoms, so a buried metal 9 is grown in the vapor phase as shown in FIG. 4(B). However, no growth reaction occurs and the buried metal 9
can grow only on the surface of the buffer metal 4 exposed in the contact hole 8. As a result, the buried metal 9 cannot be completely buried in the contact hole 8 and defects occur, so a second wiring metal 3' is formed on the second insulating layer 2' as shown in FIG. 4(C). If formed, there is a risk that the second wiring metal 3' may be disconnected due to defects within the contact hole 8.

[Means for solving problems]

In view of the above problems, the present invention first forms an insulating layer on the lower wiring pattern, and then forms an insulating layer in order to prevent disconnection of the second wiring metal due to a defect in the buried metal in the contact hole. After forming a contact hole thereon, the oxide film of the lower wiring pattern exposed inside the contact hole is removed, and then a substance that easily reacts with the growth gas of the buried metal is formed inside the contact hole.

(Function) According to the above-described multilayer wiring method of the present invention, even if the insulating layer is exposed at the bottom surface due to the positional shift of the contact hole, a substance that easily reacts with the growth gas of the buried metal is formed on the top of the insulating layer. Therefore, the buried metal can be completely buried inside the contact hole.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG. This example shows a case where the contact hole 8 is misaligned as a result of eliminating the pad portion of the contact hole 8 due to miniaturization of the wiring pattern.
FIG. 1 is a sectional view showing this process in order.

In this embodiment, first, as shown in FIG. 1(A), a first insulating layer 2 made of, for example, PSG is formed on a semiconductor substrate 1 on which elements are formed by, for example, a normal vapor phase growth method. The first wiring metal 3 made of, for example, Ajl is formed by sputtering technology.

Next, as shown in FIG. 1(B), the first wiring metal 3 is patterned by a normal lithographic process, and then a second wiring metal 3 made of, for example, PSG is patterned by a normal vapor phase growth method.
After forming the second insulating layer 2', a lift-off material 13 made of, for example, PSG, which has a higher etching rate than the second insulating layer 2', is further formed on the second insulating layer 2' by a normal vapor phase growth method.

In this case, a metal oxide film 7 is formed on the surface of the first wiring metal 3 when the second insulating layer 2' is formed.

As shown in FIG. 1C, an etching mask 14 made of, for example, a resist is applied onto the second insulating layer 2', and an etching window 14' is formed by a photo-etching process. By etching, the lift-off material 13 inside the etching window 14' is removed.
and removing the second insulating layer 2'. In this case, in this embodiment, the first
The insulating layer 2 of is exposed.

Next, as shown in FIG. 1(D), after removing the oxide film 7 on the first wiring metal 3 exposed in the contact hole 8 by, for example, ordinary sputter etching,
Embedded metal 9 formed in a later process as shown in E)
For example, a tungsten (W) film 15 is deposited as a substance that easily reacts with the growth gas.

Next, by removing the lift-off material 13, the etching mask 14 and the tungsten (W)' film 15 on the second insulating layer 2' are lifted off as shown in FIG. 1(F).

Next, as shown in FIG. 1(G), a buried metal 9 made of, for example, tungsten (W) is grown in a vapor phase using, for example, a WF and gas system. In this case, even if the first insulating layer 2 is exposed on the bottom surface due to the positional shift of the contact hole 8 as in this embodiment, the tungsten layer (
W) Since the film 15 is formed, the buried metal 9 can be grown from the entire bottom surface of the contact hole 8, and the buried metal 9 can be almost completely buried in the contact hole 8.

Next, as shown in FIG. 1H, a second wiring metal 3' made of, for example, /l is formed by, for example, normal sputtering, and then patterned by a normal lithography process.

As a result of the above, according to this embodiment, the buried metal 9 can be almost completely buried in the contact hole 8, thereby preventing disconnection of the second wiring metal 3' formed on the contact hole 8. Can be done.

〔Effect of the invention〕

According to the present invention, within the contact hole, the
Since the buried metal 9 can be buried, disconnection of the upper layer wiring metal formed thereon can be prevented, and the wiring pattern can be miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an embodiment of the multilayer wiring method according to the present invention, FIG. 2 is a diagram for explaining a conventional multilayer wiring method, and FIG.
The figure is a diagram for explaining the miniaturization of the wiring pattern, and FIG. 4 is a diagram for explaining the problems of the prior art due to the miniaturization. In the figure, 1 is a semiconductor substrate, 2 and 2'' are insulating layers, and 3
and 3' is a wiring metal, 4 is a buffer metal, 5 is a protective film, 6°14 is an etching mask, 7 is an oxide film, 8 is a contact hole, 9 is a buried metal, 11 is a pad, 1
2 is a wiring pattern, 13 is a lift-off material, 14 is an etching window, and 15 is a tungsten (W) film. No. 711 Honkai to Kyoua I; Yorota-11 Biwa ni Awok) 4-Kai no Kase Shuryo 1 Item 2 Multi-layer Nishikowata Kankan I\7ヲmu寥 2 a (A> CB) with line pattern on two sides 3

Claims (1)

[Claims] In a method for forming a multilayer interconnection, the method includes the step of embedding at least a buried metal for connection between upper and lower interconnections inside a contact hole by selective growth, the step of forming an insulating layer on a lower interconnection pattern. a step of forming a contact hole in the insulating layer and then removing an oxide film formed on the surface of the lower wiring pattern inside the contact hole; 1. A method for forming a multilayer interconnection comprising the step of selectively growing the buried metal after forming a material film.