KR20030058853A - Method for Forming of Semiconductor Device - Google Patents

Method for Forming of Semiconductor Device Download PDF

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Publication number
KR20030058853A
KR20030058853A KR1020020000081A KR20020000081A KR20030058853A KR 20030058853 A KR20030058853 A KR 20030058853A KR 1020020000081 A KR1020020000081 A KR 1020020000081A KR 20020000081 A KR20020000081 A KR 20020000081A KR 20030058853 A KR20030058853 A KR 20030058853A
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South Korea
Prior art keywords
contact hole
adhesive layer
etching process
plug
forming
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KR1020020000081A
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Korean (ko)
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이상욱
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주식회사 하이닉스반도체
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Priority to KR1020020000081A priority Critical patent/KR20030058853A/en
Publication of KR20030058853A publication Critical patent/KR20030058853A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method of forming a plug in a semiconductor device is provided to improve device performance and reliability by depositing a tungsten layer in a fine contact hole having no voids by removing overhang of adhesive layer. CONSTITUTION: An interlayer dielectric(22) having a contact hole(23) to expose a lower conductive layer is formed on a semiconductor substrate(21). By an etching process of an adhesive layer(24), overhang generated at the adhesive layer in the beginning of the contact hole is removed. A contact plug is formed.

Description

반도체 소자의 플러그 형성 방법{Method for Forming of Semiconductor Device}Method for forming plug of semiconductor device {Method for Forming of Semiconductor Device}

본 발명은 반도체 소자에 관한 것으로 특히, 텅스텐(W) 플러그(Plug)의 증착 전에 형성하는 접착층의 오버행(Over-hang)을 제거하여 플러그에 보이드 발생을 최소화하기 위한 반도체 소자의 플러그 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a plug of a semiconductor device for minimizing voids in a plug by removing an overhang of an adhesive layer formed before deposition of a tungsten (W) plug. will be.

최근, 반도체 제조에서 소자의 집적도가 증가함에 따라 폴리 실리콘(Poly-Silicon)과 메탈(Metal) 혹은 액티브(Active)와 메탈을 연결해주는 콘택홀(Contact hole)의 크기가 비약적으로 줄어들고 있는 추세이다. 또한, 하부 메탈과 상부 메탈사이를 연결해 주는 비아홀(Via-hole)의 크기의 크기 또한 줄어들고 있다.Recently, as the integration of devices increases in semiconductor manufacturing, the size of contact holes connecting poly-silicon and metal, or active and metal, has decreased dramatically. In addition, the size of the via-hole connecting the lower metal and the upper metal is also decreasing.

이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 소자의 플러그 형성 방법을 설명하면 다음과 같다.Hereinafter, a plug forming method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

도 1a 내지 도 1c는 종래 기술에 따른 플러그 형성 공정 단면도이다.1A to 1C are cross-sectional views of a plug forming process according to the prior art.

우선, 도 1a에 도시된 바와 같이, 반도체 기판, 폴리 실리콘(Poly Silicon)막, 메탈(Metal)층 등의 하부층(11)상에 층간 절연막(12)을 형성한다.First, as shown in FIG. 1A, an interlayer insulating layer 12 is formed on a lower layer 11 such as a semiconductor substrate, a polysilicon film, and a metal layer.

이때, 상기 층간 절연막(12)으로는 옥사이드(Oxide) 계열의 물질을 이용한다.In this case, an oxide-based material is used as the interlayer insulating layer 12.

이어, 포토 및 식각 공정으로 상기 하부층(11)이 노출되도록 상기 층간 절연막(12)을 선택적으로 제거하여 콘택홀(13)을 형성한다.Subsequently, the interlayer insulating layer 12 is selectively removed to expose the lower layer 11 by photo and etching processes to form a contact hole 13.

이때, 상기 콘택홀(13)은 소자 집적도 증가에 따라서 큰 종횡비(Aspect-Ratio)를 갖는다.In this case, the contact hole 13 has a large aspect ratio as the device integration degree increases.

이어, 상기 콘택홀(13)에 텅스텐(W)막을 증착하기 전에 상기 텅스텐막과 층간 절연막(12)간의 접착성이 좋지 않음으로 인한 불량을 방지하기 위하여, 상기 콘택홀(13)을 포함한 전면에 박막의 접착층(14)을 증착한다. 상기 접착층(14)으로는 Ti/TiN막 또는 Ti막을 이용한다.Subsequently, in order to prevent a defect due to poor adhesion between the tungsten film and the interlayer insulating film 12 before depositing the tungsten (W) film on the contact hole 13, the entire surface including the contact hole 13 may be disposed on the front surface of the contact hole 13. A thin film adhesive layer 14 is deposited. As the adhesive layer 14, a Ti / TiN film or a Ti film is used.

이때, 상기 접착층(14)에는 도 1a의 A 영역에 도시된 바와 같이, 콘택홀(13)의 하부보다 콘택홀(13) 입구에서 더 두껍게 형성되는 오버행(Over-hang) 현상이 발생된다.In this case, as shown in region A of FIG. 1A, an overhang phenomenon occurs in the adhesive layer 14 that is formed thicker at the entrance of the contact hole 13 than at the bottom of the contact hole 13.

이어, 도 1b에 도시된 바와 같이, 상기 콘택홀(13)을 포함한 전면에 플러그용 텅스텐막(15)을 증착하면, 상기 접착층(14)의 오버행으로 인하여 상기 콘택홀(13) 내부가 완전히 채워지기 전에 콘택홀(13)의 입구가 닫히게 되어 상기 텅스텐막(15)은 보이드(Void)(16)가 발생된 상태로 증착되게 된다.Subsequently, as shown in FIG. 1B, when the plug tungsten film 15 is deposited on the entire surface including the contact hole 13, the inside of the contact hole 13 is completely filled due to the overhang of the adhesive layer 14. Before falling, the inlet of the contact hole 13 is closed so that the tungsten film 15 is deposited with the voids 16 being generated.

이후, 도면에는 도시하지 않았지만 CMP(Chemical Mechanical Polishing) 공정으로 상기 콘택홀(13) 내부에만 남도록 상기 텅스텐막(15)을 제거하여 플러그를 형성한다.Subsequently, although not shown in the drawing, the tungsten film 15 is removed to form a plug so as to remain only inside the contact hole 13 by a chemical mechanical polishing (CMP) process.

상기 도 1b에서와 같이, 콘택홀(13)의 크기가 클 경우에는 보이드(16)가 거의 발생하지 않은 상태로 텅스텐막(15)이 증착되지만, 도 1c에 도시된 바와 같이 콘택홀(16)의 크기가 작은 경우에는 텅스텐막(15)이 콘택홀(13) 내부에 증착되기 전에 상기 텅스텐막(15)에 의해 콘택홀(13)의 입구가 닫혀버려 상기 콘택홀(13) 내부는 거의 보이드(16)로 남게 되며, 이로 인하여 하부층(11)과 상부층이 전기적으로 연결되지 못하는 불량이 발생된다.As shown in FIG. 1B, when the size of the contact hole 13 is large, the tungsten film 15 is deposited while the void 16 is hardly generated. However, as shown in FIG. 1C, the contact hole 16 is formed. When the size of the is small, the inlet of the contact hole 13 is closed by the tungsten film 15 before the tungsten film 15 is deposited inside the contact hole 13, so that the inside of the contact hole 13 is almost voided. It remains as (16), which causes a failure that the lower layer 11 and the upper layer is not electrically connected.

그러나, 상기와 같은 종래의 반도체 소자의 플러그 형성 방법은 다음과 같은 문제점이 있다.However, the plug forming method of the conventional semiconductor device as described above has the following problems.

첫째, 접착층의 오버행으로 인하여 텅스텐막이 콘택홀 내부를 채우기 전에 콘택홀 입구가 닫히게 되므로 상부층과 하부층이 전기적으로 오픈되는 불량이 발생된다.First, since the contact hole inlet is closed before the tungsten film fills the contact hole due to the overhang of the adhesive layer, a defect occurs in that the upper layer and the lower layer are electrically opened.

둘째, 보이드로 인하여 플러그 저항이 증가되므로 소자의 성능 및 신뢰성이 저하된다.Second, the plug resistance increases due to the voids, which degrades the performance and reliability of the device.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 접착층의 오버행을 제거하여 초미세 콘택홀에 텅스텐막을 보이드 없이 증착하므로써 소자의 성능 및 신뢰성을 향상시킬 수 있는 반도체 소자의 플러그 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made in order to solve the above problems to provide a method for forming a plug of a semiconductor device that can improve the performance and reliability of the device by removing the overhang of the adhesive layer to deposit a tungsten film in the ultra-fine contact hole without voids. The purpose is.

도 1a 내지 도 1c는 종래 기술에 따른 플러그 형성 공정 단면도1A to 1C are cross-sectional views of a plug forming process according to the prior art.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 플러그 형성 공정 단면도2A through 2C are cross-sectional views of a plug forming process according to an exemplary embodiment of the present invention.

도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings

21 : 하부층 22 : 층간 절연막21: lower layer 22: interlayer insulating film

23 : 콘택홀 24 : 접착층23 contact hole 24 adhesive layer

25 : 플러그25: plug

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 플러그 형성 방법은 반도체 기판상에 하부 도전층을 노출하는 콘택홀을 갖는 층간 절연막을 형성하는 단계와, 상기 콘택홀을 포함한 반도체 기판의 표면상에 접착층을 형성하는 단계와, 상기 접착층에 대한 식각 공정을 실시하여 상기 콘택홀 입구의 접착층에 발생되는 오버행을 제거하는 단계와, 상기 콘택홀에 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 한다.The plug forming method of the semiconductor device according to the present invention for achieving the above object comprises the steps of forming an interlayer insulating film having a contact hole exposing a lower conductive layer on the semiconductor substrate, the surface of the semiconductor substrate including the contact hole Forming an adhesive layer on the adhesive layer, performing an etching process on the adhesive layer to remove an overhang generated in the adhesive layer of the contact hole inlet, and forming a plug in the contact hole. It is done.

이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 플러그 형성 방법을 설명하면 다음과 같다.Hereinafter, a plug forming method of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2c는 본 발명의 실시예에 따른 플러그 형성 공정 단면도이다.2A to 2C are cross-sectional views of a plug forming process according to an exemplary embodiment of the present invention.

우선, 도 2a에 도시된 바와 같이, 반도체 기판, 폴리 실리콘(Poly Silicon)막, 메탈(Metal)층 등의 하부층(21)상에 층간 절연막(22)을 형성한다.First, as shown in FIG. 2A, an interlayer insulating layer 22 is formed on a lower layer 21 such as a semiconductor substrate, a polysilicon film, and a metal layer.

이때, 상기 층간 절연막(22)으로는 옥사이드(Oxide) 계열의 물질을 이용한다.In this case, an oxide-based material is used as the interlayer insulating layer 22.

이어, 포토 및 식각 공정으로 상기 하부층(21)이 노출되도록 상기 층간 절연막(22)을 선택적으로 제거하여 콘택홀(23)을 형성한다.Subsequently, the interlayer insulating layer 22 is selectively removed to expose the lower layer 21 by photo and etching processes to form the contact hole 23.

이때, 상기 콘택홀(23)은 소자 집적도 증가에 따라서 큰 종횡비(Aspect-Ratio)를 갖는다.In this case, the contact hole 23 has a large aspect ratio as the device integration degree increases.

이어, 상기 콘택홀(23)에 텅스텐(W)막을 증착하기 전에 상기 텅스텐막과 층간 절연막(22)간의 접착성이 좋지 않음으로 인한 불량을 방지하기 위하여, 상기 콘택홀(23)을 포함한 전면에 박막의 접착층(24)을 증착한다. 상기 접착층(24)으로는 Ti/TiN막 또는 Ti막을 이용한다.Subsequently, in order to prevent a defect due to poor adhesion between the tungsten film and the interlayer insulating film 22 before depositing the tungsten (W) film on the contact hole 23, the entire surface including the contact hole 23 may be disposed on the front surface of the contact hole 23. A thin film adhesive layer 24 is deposited. As the adhesive layer 24, a Ti / TiN film or a Ti film is used.

이때, 상기 접착층(24)에는 도 2a의 B 영역에 도시된 바와 같이, 콘택홀(23)의 하부보다 콘택홀(23) 입구에서 더 두껍게 형성되는 오버행(Over-hang) 현상이 발생된다.In this case, as shown in region B of FIG. 2A, an overhang phenomenon occurs in the adhesive layer 24, which is formed thicker at the entrance of the contact hole 23 than at the bottom of the contact hole 23.

이어, 습식 식각 또는 건식 식각 공정 또는 건식 식각 공정과 습식 식각 공정을 혼용한 식각 공정 중 어느 하나를 이용하여 상기 접착층(24)에 대한 식각 공정을 실시한다.Subsequently, an etching process is performed on the adhesive layer 24 using any one of a wet etching process, a dry etching process, or an etching process that uses a dry etching process and a wet etching process.

이때, 상기 습식 식각 공정의 경우에는 과산화수소수(H2O2) 또는 불소산(HF)을 식각제로 이용하며, 건식 식각 공정의 경우에는 Cl2, BCl3등의 플라즈마(Plama)를 식각제로 이용한다.At this time, in the wet etching process, hydrogen peroxide (H 2 O 2 ) or hydrofluoric acid (HF) is used as an etchant, and in the dry etching process, plasma (Plama) such as Cl 2 and BCl 3 is used as an etchant. .

상기 오버행이 발생된 접착층(24)은 식각제와 접촉하는 면적이 다른 부분보다 넓기 때문에 보다 빨리 식각되게 되어 도 2b의 C 영역에 도시된 바와 같이, 상기 접착층(24)의 오버행이 제거되게 된다.Since the adhesive layer 24 in which the overhang is generated has a larger area in contact with the etchant than the other part, the adhesive layer 24 is etched faster, so that the overhang of the adhesive layer 24 is removed, as shown in region C of FIG. 2B.

이어, 도 2c에 도시된 바와 같이, 상기 콘택홀(23)을 포함한 전면에 텅스텐막(25)을 증착하면, 상기 콘택홀(23)은 보이드 없이 텅스텐막(25)으로 메워지거나 보이드를 갖더라도 소자 특성에 영향을 주지 않을 정도로 미세한 크기를 갖게 된다.Subsequently, as shown in FIG. 2C, when the tungsten film 25 is deposited on the entire surface including the contact hole 23, the contact hole 23 may be filled with the tungsten film 25 without voids or may have voids. The size is so small that it does not affect device characteristics.

이후, 도면에는 도시하지 않았지만 CMP 공정으로 상기 텅스텐막(25)을 평탄 제거하여 상기 콘택홀(23) 내부에 플러그를 형성하여 본 발명을 완성한다.Subsequently, although not shown in the drawing, the tungsten film 25 is removed by a CMP process to form a plug in the contact hole 23 to complete the present invention.

상기와 같은 본 발명의 반도체 소자의 플러그 형성방법은 다음과 같은 효과가 있다.The plug forming method of the semiconductor device of the present invention as described above has the following effects.

첫째, 플러그에 보이드 발생을 방지하여 소자 저항 증가를 방지할 수 있으므로 소자의 특성 및 신뢰성을 향상시킬 수 있다.First, it is possible to prevent the occurrence of voids in the plug to prevent the increase in device resistance, thereby improving the characteristics and reliability of the device.

둘째, 플러그에 보이드 발생을 방지하여 상부층과 하부층이 전기적으로 오픈(Open)되는 불량을 방지할 수 있으므로 소자의 수율을 향상시킬 수 있다.Second, it is possible to prevent the occurrence of voids in the plug to prevent the failure of the upper and lower layers electrically open (Open) can improve the yield of the device.

Claims (3)

반도체 기판상에 하부 도전층을 노출하는 콘택홀을 갖는 층간 절연막을 형성하는 단계;Forming an interlayer insulating film having a contact hole exposing a lower conductive layer on the semiconductor substrate; 상기 콘택홀을 포함한 반도체 기판의 표면상에 접착층을 형성하는 단계;Forming an adhesive layer on a surface of the semiconductor substrate including the contact hole; 상기 접착층에 대한 식각 공정을 실시하여 상기 콘택홀 입구의 접착층에 발생되는 오버행을 제거하는 단계;Performing an etching process on the adhesive layer to remove an overhang generated in the adhesive layer at the contact hole inlet; 상기 콘택홀에 플러그를 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 플러그 형성방법.And forming a plug in the contact hole. 제 1항에 있어서, 상기 접착층은 Ti/TiN막 또는 Ti막 중 어느 하나로 형성함을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the adhesive layer is formed of any one of a Ti / TiN film and a Ti film. 제 1항에 있어서, 상기 접착층에 대한 식각 공정으로는 과산화수소수(H2O2) 또는 불소(HF)를 식각제로 이용한 습식 식각 공정, 염소 계열(Cl2, BCL3)의 플라즈마를 이용한 건식 식각 공정, 또는 상기 습식 식각 공정과 건식 식각 공정이 혼용된 식각 공정 중 어느 하나를 이용하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, wherein the etching process for the adhesive layer is a wet etching process using hydrogen peroxide (H 2 O 2 ) or fluorine (HF) as an etchant, dry etching using a plasma of chlorine series (Cl 2 , BCL 3 ) A process, or a method for manufacturing a semiconductor device, characterized in that any one of the wet etching process and the dry etching process of the mixed etching process is used.
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US8501620B2 (en) 2008-12-10 2013-08-06 Novellus Systems, Inc. Method for depositing tungsten film having low resistivity, low roughness and high reflectivity
KR101327258B1 (en) * 2009-08-04 2013-11-08 노벨러스 시스템즈, 인코포레이티드 Depositing tungsten into high aspect ratio features
US8835317B2 (en) 2009-08-04 2014-09-16 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US9034768B2 (en) 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US9082826B2 (en) 2013-05-24 2015-07-14 Lam Research Corporation Methods and apparatuses for void-free tungsten fill in three-dimensional semiconductor features
US9240347B2 (en) 2012-03-27 2016-01-19 Novellus Systems, Inc. Tungsten feature fill
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US10566211B2 (en) 2016-08-30 2020-02-18 Lam Research Corporation Continuous and pulsed RF plasma for etching metals

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9589835B2 (en) 2008-12-10 2017-03-07 Novellus Systems, Inc. Method for forming tungsten film having low resistivity, low roughness and high reflectivity
US8501620B2 (en) 2008-12-10 2013-08-06 Novellus Systems, Inc. Method for depositing tungsten film having low resistivity, low roughness and high reflectivity
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR101327258B1 (en) * 2009-08-04 2013-11-08 노벨러스 시스템즈, 인코포레이티드 Depositing tungsten into high aspect ratio features
US10103058B2 (en) 2009-08-04 2018-10-16 Novellus Systems, Inc. Tungsten feature fill
US9653353B2 (en) 2009-08-04 2017-05-16 Novellus Systems, Inc. Tungsten feature fill
US9548228B2 (en) 2009-08-04 2017-01-17 Lam Research Corporation Void free tungsten fill in different sized features
US8835317B2 (en) 2009-08-04 2014-09-16 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US9034768B2 (en) 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US9240347B2 (en) 2012-03-27 2016-01-19 Novellus Systems, Inc. Tungsten feature fill
US9082826B2 (en) 2013-05-24 2015-07-14 Lam Research Corporation Methods and apparatuses for void-free tungsten fill in three-dimensional semiconductor features
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
US11069535B2 (en) 2015-08-07 2021-07-20 Lam Research Corporation Atomic layer etch of tungsten for enhanced tungsten deposition fill
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance
US10395944B2 (en) 2015-08-21 2019-08-27 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance
US10566211B2 (en) 2016-08-30 2020-02-18 Lam Research Corporation Continuous and pulsed RF plasma for etching metals

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