KR100701779B1 - Method for fabricating contact of semiconductor device - Google Patents
Method for fabricating contact of semiconductor device Download PDFInfo
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- KR100701779B1 KR100701779B1 KR1020050130808A KR20050130808A KR100701779B1 KR 100701779 B1 KR100701779 B1 KR 100701779B1 KR 1020050130808 A KR1020050130808 A KR 1020050130808A KR 20050130808 A KR20050130808 A KR 20050130808A KR 100701779 B1 KR100701779 B1 KR 100701779B1
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 15
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000011065 in-situ storage Methods 0.000 claims abstract description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 38
- 229910052786 argon Inorganic materials 0.000 claims description 19
- 239000007789 gas Substances 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 description 12
- 239000010936 titanium Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 2
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
도 1은 아르곤 스퍼터링 전의 콘택홀을 촬영한 사진이다.1 is a photograph of a contact hole before argon sputtering.
도 2는 아르곤 스퍼터링 후의 콘택홀을 촬영한 사진이다.2 is a photograph of a contact hole after argon sputtering.
도 3은 본 발명의 실시예에 따른 콘택 형성 방법의 공정 블록도이다.3 is a process block diagram of a contact forming method according to an embodiment of the present invention.
도 4는 도 3의 방법에 따라 형성한 콘택홀의 단면 분석 사진이다.4 is a cross-sectional analysis photograph of a contact hole formed according to the method of FIG. 3.
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 상세하게는 금속 배선간 및 금속 배선과 반도체 소자의 전극간 연결에 사용되는 콘택을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact used for connection between metal wirings and electrodes between metal wirings and semiconductor devices.
최근, 반도체 집적회로가 고집적화 됨에 따라 제한된 면적 내에서 배선과 배선을 효과적으로 연결하는 방법들이 제시되고 있다. 그 중, 집적회로에서의 배선을 다층화 하는 다층 배선 방법이 주로 사용되고 있는데, 상기한 다층 배선 방법을 적용하면 반도체 소자간에 배선이 통과되는 공간을 고려할 필요가 없기 때문에 반도체 칩의 크기를 작게 제조할 수 있다.Recently, as semiconductor integrated circuits are highly integrated, methods for effectively connecting wirings and wirings within a limited area have been proposed. Among them, a multilayer wiring method for multilayering wiring in an integrated circuit is mainly used. Since the above-described multilayer wiring method does not need to consider a space through which wiring passes between semiconductor elements, the size of a semiconductor chip can be made small. have.
이하, 종래 기술에 따른 콘택 형성 방법을 설명하면 다음과 같다.Hereinafter, a method for forming a contact according to the prior art will be described.
먼저, 금속 배선층이 제공된 반도체 기판 상부에 TEOS(thetraethyle orthosilicate)막 또는 BPSG(boron phosphorus silicate glass)막 등으로 이루어진 층간 절연막을 증착한다.First, an interlayer insulating film made of a tetraethyle orthosilicate (TEOS) film or a boron phosphorus silicate glass (BPSG) film is deposited on a semiconductor substrate provided with a metal wiring layer.
그리고, 층간 절연막 위에 식각 마스크를 형성한 후, 이 마스크를 이용하여 층간 절연막을 선택적으로 식각하여 콘택홀을 형성하고, 애싱(ashing) 및 습식 세정(wet cleaning) 공정을 이용하여 식각 마스크를 제거한다.After the etching mask is formed on the interlayer insulating film, the interlayer insulating film is selectively etched using the mask to form contact holes, and the etching mask is removed using ashing and wet cleaning processes. .
이후, 스퍼터링 방법으로 티타늄(Ti)막 또는 티타늄(Ti)/질화티타늄(TiN)막 등을 증착하여 배리어막을 형성한다. 그리고, 화학 기상 증착(CVD ; chemical vapor deposition) 방식으로 텅스텐막을 증착한 후, 화학 기계적 연마(CMP ; chemical mechanical polishing) 공정에 의해 평탄화 함으로써, 금속 배선간 및 금속 배선과 반도체 소자의 전극간을 연결하기 위한 콘택을 완성한다.Subsequently, a barrier film is formed by depositing a titanium (Ti) film or a titanium (Ti) / titanium nitride (TiN) film by a sputtering method. After the deposition of a tungsten film by chemical vapor deposition (CVD), the planarization is performed by a chemical mechanical polishing (CMP) process, thereby connecting the metal wires and the metal wires to the electrodes of the semiconductor device. Complete the contact to
그런데, 이러한 구성의 콘택 형성 방법을 이용하여 콘택을 형성할 때, 상기 식각 마스크를 제거하는 동안에는 콘택홀 내부의 질화티타늄막이 노출되어 있는 상태이므로, 상기 질화티타늄막의 표면이 산화되어 표면 산화막이 발생된다.However, when forming a contact using the contact formation method having such a configuration, the titanium nitride film inside the contact hole is exposed while the etching mask is removed, so that the surface of the titanium nitride film is oxidized to generate a surface oxide film. .
따라서, 통상적으로는 식각 마스크 제거 공정과 배리어막 증착 공정 사이에 표면 산화막 제거 공정을 더 실시하고 있는데, 종래에는 아르곤 스퍼터링을 이용하여 표면 산화막 제거 공정을 실시하고 있다.Therefore, although the surface oxide film removal process is normally performed between an etching mask removal process and a barrier film deposition process, the surface oxide film removal process is conventionally performed using argon sputtering.
그러나, 아르곤 스퍼터링을 이용하여 표면 산화막을 제거하는 종래의 방법에 의하면, 상기한 아르곤 스퍼터링으로 인해 콘택홀이 손상 및 왜곡되는 문제점이 있 다.However, according to the conventional method of removing the surface oxide film using argon sputtering, there is a problem that the contact hole is damaged and distorted due to the argon sputtering.
도 1은 아르곤 스퍼터링 전의 콘택홀을 촬영한 사진이며, 도 2는 아르곤 스퍼터링 후의 콘택홀을 촬영한 사진으로, 상기 도 2를 참조하면 콘택홀이 손상 및 왜곡된 것을 알 수 있다.FIG. 1 is a photograph of a contact hole before argon sputtering, and FIG. 2 is a photograph of a contact hole after argon sputtering. Referring to FIG. 2, it can be seen that the contact hole is damaged and distorted.
또한 상기한 아르곤 스퍼터링의 경우 저압 공정이므로 공정 단가가 비싸고, 배리어막 증착 챔버와는 별도로 구비된 챔버에서 아르곤 스퍼터링을 실시해야 하므로, 산화막 제거 공정과 배리어막 증착 공정 사이에 공정 지연 시간이 존재하여 공정 지연으로 인한 수율 저하의 문제점이 있다.In addition, in the case of argon sputtering, the process cost is high because it is a low pressure process, and argon sputtering should be performed in a chamber provided separately from the barrier film deposition chamber. There is a problem of a decrease in yield due to delay.
본 발명은 상기한 문제점을 해결하기 위한 것으로, 콘택홀의 손상 및 왜곡과, 공정 지연으로 인한 수율 저하를 방지할 수 있으며, 제조 원가를 절감할 수 있는 반도체 소자의 콘택 형성 방법을 제공함을 목적으로 한다.The present invention is to solve the above problems, an object of the present invention is to provide a method for forming a contact of a semiconductor device that can prevent the damage and distortion of the contact hole, the yield decrease due to the process delay, and can reduce the manufacturing cost .
상기한 본 발명의 목적은,The object of the present invention described above,
반도체 기판의 상부에 형성된 층간 절연막에 식각 마스크를 형성하는 단계;Forming an etching mask on the interlayer insulating film formed on the semiconductor substrate;
상기 식각 마스크를 이용하여 층간 절연막을 선택적으로 식각함으로써 콘택홀을 형성하는 단계;Forming a contact hole by selectively etching the interlayer insulating layer using the etching mask;
상기 식각 마스크를 제거하는 단계;Removing the etch mask;
SF6 또는 CF4와 아르곤 가스를 이용하여 상기 콘택홀의 내부에 노출된 질화티타늄막의 표면 산화막을 제거하는 단계;Removing the surface oxide film of the titanium nitride film exposed inside the contact hole using SF6 or CF4 and argon gas;
배리어막을 형성하는 단계;Forming a barrier film;
도전막으로 상기 콘택홀을 갭필하는 단계; 및Gap-filling the contact hole with a conductive film; And
도전막을 평탄화하는 단계Planarizing the conductive film
를 포함하는 반도체 소자의 콘택 형성 방법에 의해 달성할 수 있다.It can achieve by the contact formation method of the semiconductor element containing.
본 발명을 실시함에 있어서, 상기 표면 산화막 제거 단계와 배리어막 형성 단계를 인시튜로 진행하는 것이 바람직하며, 표면 산화막 제거 단계에서는 챔버 내부를 50 내지 100mTorr의 압력으로 유지하고, 300 내지 500W의 고주파 전력을 사용하며, 10 내지 30 sccm의 CF4(또는 SF6) 및 100 내지 300sccm의 아르곤을 세정 가스로 사용한다.In the practice of the present invention, it is preferable to proceed with the surface oxide film removing step and the barrier film forming step in situ, and in the surface oxide film removing step, the inside of the chamber is maintained at a pressure of 50 to 100 mTorr, and a high frequency power of 300 to 500 W. 10 to 30 sccm of CF4 (or SF6) and 100 to 300 sccm of argon are used as cleaning gases.
이하, 첨부도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명의 실시예에 따른 콘택 형성 방법의 공정 블록도를 도시한 것이고, 도 4는 도 3의 방법에 따라 형성한 콘택홀의 단면 분석 사진을 도시한 것이다.3 illustrates a process block diagram of a contact forming method according to an exemplary embodiment of the present invention, and FIG. 4 illustrates a cross-sectional analysis photograph of a contact hole formed according to the method of FIG. 3.
반도체 기판의 상부에는 층간 절연막(10)이 형성되어 있고, 층간 절연막(10)의 하부에는 하부 금속 배선 또는 트랜지스터 구조물이 형성되어 있다.An
여기에서, 상기 층간 절연막(10)은 TEOS(thetraethyle orthosilicate)막 또는 BPSG(boron phosphorus silicate glass)막으로 이루어질 수 있다.Here, the
층간 절연막(10)에 콘택을 형성하기 위해, 상기 층간 절연막(10)의 상부에 식각 마스크를 형성하고, 이 마스크를 이용한 식각 공정을 진행하여 층간 절연막(10)을 선택적으로 제거함으로써 콘택홀(20)을 형성한다.In order to form a contact on the
이후, 애싱(ashing) 및 습식 세정(wet cleaning) 공정을 이용하여 식각 마스크를 제거한다.The etch mask is then removed using ashing and wet cleaning processes.
그런데, 식각 마스크를 제거하는 동안에 콘택홀(20) 내부에 노출된 질화티타늄막(30)의 표면이 산화되어 표면 산화막이 형성된다.However, the surface of the
여기에서, 상기 질화티타늄막(30)은 금속 배선층일 수도 있고, 게이트 또는 소스/드레인에 형성된 샐리사이드(salicide: self aligned silicide)일 수도 있다.Here, the
이에, 본 발명의 실시예에서는 상기한 표면 산화막을 제거하기 위하여 식각 공정을 실시한다.Thus, in the embodiment of the present invention, an etching process is performed to remove the surface oxide film.
상기한 식각 공정은 SF6 또는 CF4와 아르곤 가스를 이용하여 실시하는데, 보다 구체적으로는 반도체 기판이 배치된 공정 챔버 내부를 50 내지 100mTorr의 압력으로 유지하면서 300 내지 500W의 고주파 전력을 인가하고, 10 내지 30 sccm의 CF4 또는 SF6와 100 내지 300sccm의 아르곤을 세정 가스로 주입하면서 질화티타늄막(30)을 식각한다.The etching process is performed using SF6 or CF4 and argon gas. More specifically, high frequency power of 300 to 500 W is applied while maintaining the inside of the process chamber where the semiconductor substrate is disposed at a pressure of 50 to 100 mTorr, and 10 to The
이러한 구성의 표면 산화막 제거 공정에 의하면, 아르곤 스퍼터링을 이용하여 표면 산화막을 제거하던 종래에 비해 콘택홀(20)의 왜곡 및 손상을 감소시킬 수 있다.According to the surface oxide film removal process having such a configuration, the distortion and damage of the
표면 산화막을 제거한 후에는 배리어막(미도시함)을 형성한다. 이때, 상기 배리어막을 형성하는 공정은 표면 산화막 제거 공정과 인시튜로 진행할 수 있다.After removing the surface oxide film, a barrier film (not shown) is formed. In this case, the process of forming the barrier film may be performed in situ with the surface oxide film removing process.
예를 들면, 상기 표면 산화막 제거 공정과 배리어막 형성 공정은 식각 및 증착이 모두 가능한 고밀도 플라즈마 장치에서 실시할 수 있다.For example, the surface oxide film removing step and the barrier film forming step may be performed in a high density plasma apparatus capable of both etching and deposition.
이러한 구성에 의하면, 표면 산화막 제거 공정과 배리어막 형성 공정 사이의 공정 지연 시간이 종래보다 줄어들게 되므로, 공정 지연으로 인한 수율 저하의 문제점을 해결할 수 있다.According to this configuration, the process delay time between the surface oxide film removal process and the barrier film formation process is shorter than before, and thus the problem of yield reduction due to the process delay can be solved.
물론, 표면 산화막 제거 공정과 배리어막 형성 공정을 별도로 구비된 식각 챔버와 증착 챔버에서 실시하는 것도 가능하며, 이 경우에는 식각 챔버와 증착 챔버를 연결하는 연결 통로를 형성하는 것이 바람직하다.Of course, the surface oxide film removal process and the barrier film formation process may be performed in an etching chamber and a deposition chamber separately provided. In this case, it is preferable to form a connection passage connecting the etching chamber and the deposition chamber.
상기 배리어막은 티타늄(Ti)막 또는 티타늄(Ti)/질화티타늄(TiN)막으로 형성할 수 있다.The barrier film may be formed of a titanium (Ti) film or a titanium (Ti) / titanium nitride (TiN) film.
배리어막을 형성한 후, 콘택 형성 물질, 예컨대 텅스텐을 증착하여 콘택홀을 갭필(gap fill)하는 도전막을 형성하고, 이후, 평탄화 공정을 실시하여 도전막을 평탄화하면 콘택홀(20)에 매립된 콘택(미도시함)이 형성된다.After the barrier film is formed, a contact forming material such as tungsten is deposited to form a conductive film that gap fills the contact hole. Then, when the conductive film is flattened by performing a planarization process, the contact buried in the contact hole 20 ( Not shown) is formed.
여기에서, 상기 평탄화 공정으로는 화학기계적 연마 공정을 이용할 수 있다.Here, the chemical mechanical polishing process may be used as the planarization process.
상기에서는 본 발명의 바람직한 실시예에 대하여 설명하였지만, 본 발명은 이에 한정되는 것이 아니고 특허청구범위와 발명의 상세한 설명 및 첨부한 도면의 범위 안에서 여러 가지로 변형하여 실시하는 것이 가능하고 이 또한 본 발명의 범위에 속하는 것은 당연하다.Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications and changes can be made within the scope of the claims and the detailed description of the invention and the accompanying drawings. Naturally, it belongs to
이상에서 살펴본 바와 같이 본 발명은 SF6 또는 CF4와 아르곤 가스를 이용한 식각 공정으로 표면 산화막을 제거함으로써, 아르곤 스퍼터링을 이용하여 표면 산화막을 제거하는 종래에 비해 제조 원가를 절감할 수 있으며, 콘택홀의 왜곡 및 손 상을 방지할 수 있다.As described above, according to the present invention, by removing the surface oxide film by an etching process using SF6 or CF4 and argon gas, manufacturing cost can be reduced compared to the conventional method of removing the surface oxide film by argon sputtering, and the distortion of contact holes and Damage can be prevented.
또한, 표면 산화막 제거 공정과 배리어막 형성 공정을 인시튜로 진행함으로써, 공정 지연으로 인한 수율 저하를 방지할 수 있는 효과가 있다.In addition, by performing the surface oxide film removing step and the barrier film forming step in situ, there is an effect of preventing the yield decrease due to the process delay.
Claims (4)
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| CN102427037A (en) * | 2011-07-22 | 2012-04-25 | 上海华力微电子有限公司 | Method for solving problem of over-slow speed ratio of dry etching of porous low-k medium |
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| KR890004396A (en) * | 1987-08-06 | 1989-04-21 | 강진구 | Electrode Formation Method in Manufacturing Semiconductor Integrated Circuits |
| KR19980038845A (en) * | 1996-11-26 | 1998-08-17 | 김영환 | Metal contact method of semiconductor device |
| KR20020002960A (en) * | 2000-06-30 | 2002-01-10 | 박종섭 | Method for forming metal line |
| KR20030002119A (en) * | 2001-06-30 | 2003-01-08 | 주식회사 하이닉스반도체 | Method for forming via hole by dual damascene process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR890004396A (en) * | 1987-08-06 | 1989-04-21 | 강진구 | Electrode Formation Method in Manufacturing Semiconductor Integrated Circuits |
| KR19980038845A (en) * | 1996-11-26 | 1998-08-17 | 김영환 | Metal contact method of semiconductor device |
| KR20020002960A (en) * | 2000-06-30 | 2002-01-10 | 박종섭 | Method for forming metal line |
| KR20030002119A (en) * | 2001-06-30 | 2003-01-08 | 주식회사 하이닉스반도체 | Method for forming via hole by dual damascene process |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102427037A (en) * | 2011-07-22 | 2012-04-25 | 上海华力微电子有限公司 | Method for solving problem of over-slow speed ratio of dry etching of porous low-k medium |
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