KR100593210B1 - Method of fabricating contact hole of semiconductor device - Google Patents
Method of fabricating contact hole of semiconductor device Download PDFInfo
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- KR100593210B1 KR100593210B1 KR1020030102008A KR20030102008A KR100593210B1 KR 100593210 B1 KR100593210 B1 KR 100593210B1 KR 1020030102008 A KR1020030102008 A KR 1020030102008A KR 20030102008 A KR20030102008 A KR 20030102008A KR 100593210 B1 KR100593210 B1 KR 100593210B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 21
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 16
- 150000004767 nitrides Chemical class 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims description 8
- 239000010410 layer Substances 0.000 claims description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 239000007789 gas Substances 0.000 claims description 4
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 10
- 230000007547 defect Effects 0.000 abstract description 5
- 239000011800 void material Substances 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 239000005360 phosphosilicate glass Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000001000 micrograph Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000012421 spiking Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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Abstract
본 발명은 반도체 소자의 컨택 홀 형성방법에 관한 것으로, 보다 자세하게는 이종의 층간절연막을 적층하여 그 식각율의 차이를 이용해 컨택 홀을 형성함으로써 자기정렬 컨택을 이룰 수 있는 방법에 관한 것이다. The present invention relates to a method of forming a contact hole in a semiconductor device, and more particularly, to a method of forming a self-aligned contact by stacking heterogeneous interlayer insulating films and forming a contact hole using a difference in etching rate.
본 발명의 반도체 소자의 컨택 홀 형성방법은 소정의 구조물이 형성된 반도체 기판의 상부에 라이너 질화막을 형성하는 단계; 상기 라이너 질화막의 상부에 이종의 물질로 구성된 층간절연막을 적층하는 단계; 상기 층간절연막을 평탄화한 후 컨택 홀이 형성될 영역을 개방하는 패턴을 형성하는 단계; 및 상기 패턴을 식각마스크로 하여 이종의 층간절연막을 식각하여 컨택 홀을 형성하는 단계로 이루어짐에 기술적 특징이 있다.A method of forming a contact hole in a semiconductor device of the present invention includes forming a liner nitride film on an upper portion of a semiconductor substrate on which a predetermined structure is formed; Stacking an interlayer insulating film made of different materials on top of the liner nitride film; Forming a pattern for opening the region where a contact hole is to be formed after planarizing the interlayer insulating film; And forming contact holes by etching heterogeneous interlayer insulating films using the pattern as an etching mask.
따라서, 본 발명의 반도체 소자의 컨택 홀 형성방법은 이종의 층간절연막을 적층하여 그 식각율의 차이를 이용해 컨택 홀을 형성함으로써 자기정렬 컨택을 이룰 수 있는 효과가 있다. 또한 HDP를 적용함으로써 공간이 좁은 영역에서 매립특성의 저하로 인해 나타나는 보이드 결함의 발생을 억제할 수 있다.Accordingly, the method for forming a contact hole in the semiconductor device of the present invention has the effect of forming a self-aligned contact by stacking heterogeneous interlayer insulating films and forming contact holes using a difference in etching rate. In addition, by applying the HDP, it is possible to suppress the occurrence of void defects caused by the reduction of the buried characteristics in a narrow space.
층간절연막, HDP, TEOS, ME-RIEInterlayer Insulation, HDP, TEOS, ME-RIE
Description
도 1a는 종래기술에 의해 컨택 스파이킹이 발생한 모습을 보여주는 현미경 사진.Figure 1a is a micrograph showing the appearance of contact spiking by the prior art.
도 1b 내지 도 1e는 종래기술에 의한 컨택 홀 형성방법의 단면도.1B to 1E are cross-sectional views of a conventional method for forming a contact hole.
도 2a 내지 도 2d는 본 발명에 의한 컨택 홀 형성방법의 단면도.2A to 2D are cross-sectional views of a method for forming a contact hole according to the present invention.
도 2e는 본 발명에 의해 자기정렬 컨택이 이루어진 모습을 보여주는 현미경 사진.Figure 2e is a micrograph showing a state in which a self-aligned contact made by the present invention.
본 발명은 반도체 소자의 컨택 홀(contact hole) 형성방법에 관한 것으로, 보다 자세하게는 이종의 층간절연막(Pre Metal Dielectric; PMD)을 적층하여 그 식각율의 차이를 이용해 컨택 홀을 형성함으로써 자기정렬(self-aligned) 컨택을 이룰 수 있는 방법에 관한 것이다. The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to form a contact hole using a difference in etching rate by stacking heterogeneous interlayer dielectric films (PMDs). self-aligned).
종래 공정에서는 PMD 물질로 주로 BPSG(Boron Phosphorus Spin-On-Glass), PSG(Phospho-Silicate Glass), TEOS(Tetraethyl Ortho-silicate), HDP(High Density Plasma) 등 소자의 특성에 맞게 적용되어 사용되었다.In the conventional process, PMD materials were mainly applied to the characteristics of devices such as BPSG (Boron Phosphorus Spin-On-Glass), PSG (Phospho-Silicate Glass), TEOS (Tetraethyl Ortho-silicate), and HDP (High Density Plasma). .
기존에 주로 사용 되고 있는 BPSG 나 PSG 등을 PMD 물질로 사용할 경우에는 실리콘(Si) 혹은 티타늄(Ti)이나 코발트(Co) 실리사이드(Silicide)의 상부에 TEOS나 PMD 라이너(liner) 질화막(Nitride)을 얇게 사용하여 인(Phosphorus)의 침투(Penetration)를 막고, 사용하는 물질간의 서로 다른 식각 선택비를 이용해서 컨택의 마진(margin)이 없는 부분에서의 컨택 홀 형성을 보완해 주는 방법을 주로 이용해 왔다.In case of using BPSG or PSG, which is mainly used as a PMD material, TEOS or PMD liner nitride is applied on top of silicon (Si) or titanium (Ti) or cobalt (Co) silicide. Thin layers have been used to prevent the penetration of Phosphorus and complement the formation of contact holes in non-margin areas by using different etch selectivity between materials. .
하지만 이러한 기술들은 컨택 홀 형성을 식각공정의 마진을 확보하는데 한계가 있고 최악의 경우 컨택 스파이킹(Spiking)이 발생하여 누설전류 등이 발생하는 문제점이 나타나기도 한다. However, these techniques are limited in securing the contact hole formation margin of the etching process, and in the worst case, there may be a problem in that contact spike occurs and leakage current occurs.
도 1a는 컨택 스파이킹(점선의 내부)이 발생한 경우를 보여주는 현미경 사진이다.1A is a micrograph showing the case where contact spiking (inside the dotted line) occurs.
도 1b 내지 도 1e는 종래의 PMD 라이너 질화막을 적용하여 컨택 홀을 형성하는 방법을 보여주는 단면도이다.1B to 1E are cross-sectional views illustrating a method of forming contact holes by applying a conventional PMD liner nitride film.
먼저, 도 1b는 소자분리막(1)과 소오스/드레인 영역(2) 및 스페이서(spacer, 3)가 구비된 복수개의 게이트(4)가 형성된 실리콘 기판(5)의 상부에 PMD 라이너 질화막(6)을 증착하는 단계이다. 이때 상기 라이너 질화막은 300Å의 두께로 증착한다.First, FIG. 1B illustrates a PMD liner nitride film 6 on a silicon substrate 5 on which a plurality of gates 4 including a device isolation film 1, a source /
다음, 도 1c는 BPSG 혹은 PSG 물질의 층간절연막(7)을 증착한 후 CMP(chemical mechanical polishing)을 진행하는 단계이다. 상기 CMP에 의한 평탄화 후에 6500Å 두께의 PMD가 형성된다. 상기 층간절연막을 증착할 때 BPSG 혹은 PSG 물질의 낮은 매립특성(step coverage)에 의해 게이트 전극사이의 좁은 공간에 보이드 결함(20)이 발생한다.Next, Figure 1c is a step of performing a chemical mechanical polishing (CMP) after depositing the interlayer insulating film 7 of BPSG or PSG material. After planarization by the CMP, a PMD having a thickness of 6500 mV is formed. When depositing the interlayer dielectric layer,
다음, 도 1d는 컨택 홀을 소정의 전도성 금속으로 매립한 후 평탄화 공정을 실시할 때 발생할 수 있는 BPSG나 PSG의 손실을 최소화하기 위해 캡핑막의 역할을 하는 TEOS막(8)을 증착하는 단계이다. 이때 상기 TEOS는 약 1000Å의 두께로 증착하여 전체 PMD의 두께는 7500Å이 된다.Next, FIG. 1D is a step of depositing a TEOS
다음, 도 1e는 컨택 홀(9) 형성을 위한 식각을 진행하는 단계이다. 이때 실리사이드가 형성된 소오스/드레인 영역의 상부에 형성되는 컨택 홀은 그 컨택영역의 크기가 부족하여 컨택 스파이킹(10)이 발생한다. Next, FIG. 1E is a step of etching to form the
하지만 이러한 기술들은 상술한 바와 같이 컨택 홀 형성을 식각공정의 마진을 확보하는데 한계가 있고 최악의 경우 컨택 스파이킹(Spiking)이 발생하여 누설전류 등이 발생하는 문제점이 나타나기도 한다.However, these techniques are limited in securing the contact hole formation margin of the etching process as described above, and in the worst case, there is a problem in that contact spike occurs and leakage current occurs.
따라서, 본 발명은 상기와 같은 종래 기술의 문제점을 해결하기 위한 것으로, 이종의 층간절연막을 적층하여 그 식각율의 차이를 이용해 컨택 홀을 형성함으로써 자기정렬 컨택을 이룰 수 있는 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the problems of the prior art as described above, to provide a method for forming a self-aligned contact by forming a contact hole using a difference in the etch rate by stacking different interlayer insulating films. There is a purpose.
본 발명의 상기 목적은 소정의 구조물이 형성된 반도체 기판의 상부에 라이너 질화막을 형성하는 단계; 상기 라이너 질화막의 상부에 이종의 물질로 구성된 층간절연막을 적층하는 단계; 상기 층간절연막을 평탄화한 후 컨택 홀이 형성될 영역을 개방하는 패턴을 형성하는 단계; 및 상기 패턴을 식각마스크로 하여 이종의 층간절연막을 식각하여 컨택 홀을 형성하는 단계로 이루어진 반도체 소자의 컨택 홀 형성방법에 의해 달성된다.The above object of the present invention comprises the steps of forming a liner nitride film on the upper portion of the semiconductor substrate having a predetermined structure; Stacking an interlayer insulating film made of different materials on top of the liner nitride film; Forming a pattern for opening the region where a contact hole is to be formed after planarizing the interlayer insulating film; And forming a contact hole by etching heterogeneous interlayer insulating films using the pattern as an etching mask.
본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration of the present invention and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.
먼저, 도 2a는 소자분리막(30)과 소오스/드레인 영역(31) 및 스페이서(32)가 구비된 복수개의 게이트(33)가 형성된 실리콘 기판(34)의 상부에 PMD 라이너 질화막(35)을 증착하는 단계이다. 이때 상기 라이너 질화막은 300Å의 두께로 증착한다.First, FIG. 2A illustrates the deposition of a PMD
다음, 도 2b는 HDP(36)를 증착하는 단계이다. 상기 HDP는 제 1 층간절연막의 역할을 하며 그 두께는 2600Å으로 형성한다. Next, FIG. 2B is a step of depositing
다음, 도 2c는 TEOS(37)를 증착하는 단계이다. 상기 TEOS는 제 2 층간절연막의 역할을 하며 그 두께는 10000Å으로 형성한다. 이후 전체 PMD의 두께가 7500Å이 되도록 CMP를 진행하여 평탄화 한다. 이후 도시되지는 않았지만 컨택 홀이 형성 될 영역을 개방하는 패턴을 형성한다.Next, FIG. 2C is a step of depositing TEOS 37. The TEOS serves as a second interlayer insulating film and has a thickness of 10000 GPa. After that, the planarizing process is performed by the CMP so that the thickness of the entire PMD is 7500Å. Although not shown, a pattern is formed to open the area where the contact hole is to be formed.
다음, 도 2d는 컨택 홀(38)을 형성하는 단계이다. 상기 패턴을 식각마스크로 하여 식각을 진행하여 TEOS와 HDP 및 라이너 질화막을 순차적으로 제거하고 소오스/드레인 영역의 상부 및 게이트 전극의 상부에 형성된 실리사이드층을 개방한다. 이후 도시되지는 않았지만 상기 컨택 홀을 소정의 전도성 금속으로 매립하여 컨택 플러그(contact plug) 내지 비아(via) 형성을 완료한다. Next, FIG. 2D is a step of forming the contact hole 38. Etching is performed using the pattern as an etching mask to sequentially remove TEOS, HDP, and liner nitride, and to open the silicide layer formed on the top of the source / drain region and on the gate electrode. Although not shown, the contact hole is filled with a predetermined conductive metal to complete contact plugs or vias.
컨택 홀을 형성하기 위한 식각공정은 ME-RIE(magnetically enhanced - reactive ion etching) 장비에서 진행한다. 이때 층간절연막으로 작용하는 산화막의 물질은 그 물질의 밀도에 따라 식각율의 차이를 보이는데 일반적으로는 다음과 같다. The etching process for forming the contact hole is performed in a magnetically enhanced-reactive ion etching (ME-RIE) apparatus. In this case, the material of the oxide film serving as the interlayer insulating film shows a difference in etching rate according to the density of the material.
HDP, USG(Undoped Silica Glass), FSG(Fluorinated Silica Glass)〈 TEOS 〈 BPSG, PSGHDP, Undoped Silica Glass (USG), Fluorinated Silica Glass (FSG) 〈TEOS 〈BPSG, PSG
즉, BPSG 또는 PSG가 식각율이 가장 크고, 다음으로 TEOS 그리고 식각율이 가장 작은 물질은 HDP, USG 또는 FSG 이다.That is, BPSG or PSG has the largest etch rate, followed by TEOS and the smallest etch rate is HDP, USG or FSG.
상기 컨택 홀의 식각이 진행되는 ME-RIE 장비에서는 C4F8와 O2 가스를 이용하는데 본 발명에서는 상기 두 가스의 혼합비를 조절하여 물질에 따른 식각율의 차이를 도모하였다. 보다 자세하게는 25 내지 30mTorr의 압력에서 1700W 파워와 8 내지 10sccm의 C4F8, 3 내지 5sccm의 O2, 30 내지 50sccm CO 그리고 150 내지 250sccm의 아르곤(Ar) 가스를 흘려주면서 식각을 진행한다. In the ME-RIE apparatus in which the contact hole is etched, C 4 F 8 and O 2 gases are used. In the present invention, the mixing ratio of the two gases is adjusted to achieve a difference in etching rate according to the material. More specifically, the etching is performed while flowing 1700 W power and 8-10 sccm C 4 F 8 , 3-5 sccm O 2 , 30-50 sccm CO, and 150-250 sccm argon (Ar) gas at a pressure of 25-30 mTorr.
상기의 조건으로 식각을 진행하면 TEOS와 HDP의 식각률 차이에 의해 형성되는 컨택 홀의 프로필(profile)이 변화하게 된다. 즉, 식각률이 높은 TEOS층이 넓은 단면적을 가지고 먼저 식각되다가, 식각률이 낮은 HDP층을 만나면 형성되는 컨택 홀의 단면적이 줄어듬으로서 컨택홀의 프로필은 하부로 갈수록 좁아지는 형상을 가지게 된다. 따라서 컨택 홀 하부의 컨택영역 면적이 좁더라도 상기와 같은 컨택 홀 프로필의 차이에 의해 자기정렬 컨택을 이룰 수 있게 된다. When etching is performed under the above conditions, the profile of the contact hole formed by the difference in the etching rate between TEOS and HDP is changed. That is, the TEOS layer having a high etch rate is etched first with a large cross-sectional area, and the cross-sectional area of the contact hole formed when the HDP layer having a low etch rate is reduced is reduced so that the profile of the contact hole becomes narrower toward the bottom. Therefore, even if the area of the contact area under the contact hole is narrow, self-aligned contact can be achieved by the difference in the contact hole profile as described above.
도 2e는 본 발명에 의해 자기정렬 컨택(점선의 내부)이 이루어진 컨택 홀의 현미경 사진이다. 컨택 홀의 하부폭이 상부에 비해 좁으며, 비아홀이 STI 소자분리막으로 침범하지 않고 소오스/드레인 영역에 정렬되어 있음을 확인할 수 있다.2E is a micrograph of a contact hole in which a self-aligned contact (inside of a dashed line) is made according to the present invention. The bottom width of the contact hole is narrower than the top, and the via hole is aligned in the source / drain region without invading the STI device.
또한 HDP를 적용할 경우 기존에 발생하는 폭이 좁은 영역에서의 갭필(gap fill)특성 저하에 의한 보이드(void) 형성을 억제할 수 있다. 즉, 소자의 고집적화에 따라 게이트 간의 공간도 좁아져서 높은 종횡비(aspect ratio)을 가지게 된다. 이러한 영역은 절연막의 매립특성이 저하되어 보이드 결함이 발생하게 된다. 하지만 본 발명에서는 라이너 질화막을 형성한 후에 매립특성이 양호한 HDP를 적용함으로써 종래의 BPSG 또는 PSG를 사용할 때 발생하는 보이드 결함을 방지할 수 있다.In addition, when the HDP is applied, it is possible to suppress the formation of voids due to the deterioration of the gap fill characteristic in a narrow area that is generated. In other words, the space between the gates is narrowed according to the high integration of the device to have a high aspect ratio. In such a region, the buried property of the insulating film is lowered and void defects are generated. However, in the present invention, after forming the liner nitride film, by applying HDP having good embedding characteristics, it is possible to prevent void defects occurring when using a conventional BPSG or PSG.
상세히 설명된 본 발명에 의하여 본 발명의 특징부를 포함하는 변화들 및 변형들이 당해 기술 분야에서 숙련된 보통의 사람들에게 명백히 쉬워질 것임이 자명하다. 본 발명의 그러한 변형들의 범위는 본 발명의 특징부를 포함하는 당해 기술 분야에 숙련된 통상의 지식을 가진 자들의 범위 내에 있으며, 그러한 변형들은 본 발명의 청구항의 범위 내에 있는 것으로 간주된다.It will be apparent that changes and modifications incorporating features of the invention will be readily apparent to those skilled in the art by the invention described in detail. It is intended that the scope of such modifications of the invention be within the scope of those of ordinary skill in the art including the features of the invention, and such modifications are considered to be within the scope of the claims of the invention.
따라서, 본 발명의 반도체 소자의 컨택 홀 형성방법은 이종의 층간절연막을 적층하여 그 식각율의 차이를 이용해 컨택 홀을 형성함으로써 자기정렬 컨택을 이룰 수 있는 효과가 있다.Accordingly, the method for forming a contact hole in the semiconductor device of the present invention has the effect of forming a self-aligned contact by stacking heterogeneous interlayer insulating films and forming contact holes using a difference in etching rate.
또한 HDP를 적용함으로써 공간이 좁은 영역에서 매립특성의 저하로 인해 나타나는 보이드 결함의 발생을 억제할 수 있다.
In addition, by applying the HDP, it is possible to suppress the occurrence of void defects caused by the reduction of the buried characteristics in a narrow space.
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