KR0172785B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
- Publication number
- KR0172785B1 KR0172785B1 KR1019950006822A KR19950006822A KR0172785B1 KR 0172785 B1 KR0172785 B1 KR 0172785B1 KR 1019950006822 A KR1019950006822 A KR 1019950006822A KR 19950006822 A KR19950006822 A KR 19950006822A KR 0172785 B1 KR0172785 B1 KR 0172785B1
- Authority
- KR
- South Korea
- Prior art keywords
- conductive line
- contact
- insulating layer
- forming
- insulating film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 접속장치 및 그 제조방법에 관한 것으로, 반도체 기판 상부에 제1전도선마스크 및 제2전도선마스크를 이용하여 제1절연막, 제1전도선, 제2절연막, 제2전도선 및 제3절연막을 순차적으로 형성하고 콘택마스크를 이용하여 상기 제1전도선을 노출시키는 제1,2콘택홀을 형성한 다음, 상기 제1,2콘택홀에 제1,2콘택플러그를 형성하여 상기 제1전도선과 제2전도선이 접속되는 일측을 형성하고 제3전도선마스크를 이용한 식각공정으로 상기 제1전도선과 상기 제3전도선이 접속되는 타측을 형성함으로써 한번의 콘택공정으로 반도체 접속장치를 형성하여 제조공정을 단축시키고 그에 따른 제조단가를 감소시켜 반도체 소자의 생산성 및 수율을 향상시킬 수 있는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor connecting device and a method for manufacturing the same, wherein a first insulating film, a first conductive line, a second insulating film, a second conductive line, and the like are formed by using a first conductive line mask and a second conductive line mask on a semiconductor substrate. A third insulating layer is sequentially formed, and first and second contact holes are formed to expose the first conductive line by using a contact mask, and then first and second contact plugs are formed in the first and second contact holes. The semiconductor connection device is formed in one contact process by forming one side to which the first conductive line and the second conductive line are connected and forming the other side to which the first conductive line and the third conductive line are connected by an etching process using a third conductive line mask. It is a technology that can improve the productivity and yield of semiconductor devices by forming a shortening the manufacturing process and thereby reducing the manufacturing cost.
Description
제1a도 및 제1b도는 종래기술에 따른 반도체 접속장치의 레이아웃도 및 단면도.1A and 1B are a layout view and a cross-sectional view of a semiconductor connection device according to the prior art.
제2도는 본 발명의 실시예에 따른 반도체 접속장치의 레이아웃도.2 is a layout diagram of a semiconductor connection device according to an embodiment of the present invention.
제3a도 내지 제3e도는 상기 제2도의 절단면에 따른 반도체 접속장치 제조공정을 도시한 단면도.3A to 3E are sectional views showing the semiconductor connection device manufacturing process along the cut surface of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11, 41 : 제1절연막 13, 43 : 제1전도선11, 41: first insulating film 13, 43: first conductive line
15, 45 : 제2절연막 17, 49 : 제2전도선15, 45: second insulating film 17, 49: second conductive line
19, 51 : 제3절연막 21 : 제1감광막패턴19, 51: third insulating film 21: first photosensitive film pattern
23, 47 : 제1콘택홀 25, 53 : 제2콘택홀23, 47: 1st contact hole 25, 53: 2nd contact hole
27 : 콘택플러그 29, 55: 제3전도선27: contact plug 29, 55: third conductive line
31 : 제2감광막패턴 A,AA : 제1전도선마스크31: second photosensitive film pattern A, AA: first conductive line mask
B,BB : 제2전도선마스크 CC : 콘택마스크B, BB: Conductor mask 2 CC: Contact mask
C1 : 제1콘택마스크 C2 : 제2콘택마스크C1: first contact mask C2: second contact mask
D,DD : 제3전도선마스크D, DD: Third Conductor Mask
본 발명은 반도체 접속장치 및 그 제조방법에 관한 것으로, 특히 중첩된 다수의 전도층을 한번의 콘택공정으로 연결함으로써 반도체소자의 공정을 단순화시켜 반도체소자의 생산성 및 수율을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor connecting device and a method of manufacturing the same, and more particularly, to a technology capable of improving the productivity and yield of a semiconductor device by simplifying the process of the semiconductor device by connecting a plurality of overlapping conductive layers in a single contact process. will be.
일반적으로, 반도체소자가 고집적화됨에 따라 전도선의 층수가 증가되었다.In general, as semiconductor devices have been highly integrated, the number of layers of conductive lines has increased.
제1a도 및 제1b도는 종래 기술에 따른 반도체 접속장치를 도시한 레이아웃도 및 단면도이다. 이때, 상기 제1b도의 일측은 상기 제1a도의 ⓒ-ⓒ의 절단면을 따라 형성되고, 타측은 ⓓ-ⓓ의 절단면을 따라 도시한 것이다.1A and 1B are a layout view and a cross-sectional view showing a semiconductor connection device according to the prior art. At this time, one side of FIG. 1b is formed along the cutting surface of ⓒ-ⓒ of FIG. 1a, and the other side is shown along the cutting surface of ⓓ-ⓓ.
제1a도를, 제1전도선마스크(a)와 제2전도선마스크(b), 제1전도선마스크(a)와 제3전도선마스크(d)의 콘택을 각각의 콘택마스크(c1, c2)로 콘택할 때의 레이아웃을 도시한다.FIG. 1A shows contacts of the first conductive line mask (a) and the second conductive line mask (b), the first conductive line mask (a), and the third conductive line mask (d), respectively. The layout when contacting with c2) is shown.
제1b도를 참조하면, 제1절연막(41)이 형성된 반도체기판(도시안됨)에 제1전도선마스크(a)를 이용하여 제1전도선(43)을 형성한다.Referring to FIG. 1B, the first conductive line 43 is formed on the semiconductor substrate (not shown) on which the first insulating layer 41 is formed using the first conductive line mask a.
그리고, 전체표면상부를 평탄화시키는 제2절연막(45)을 형성하고, 제1콘택마스크(c1)를 이용한 식각공정으로 상기 제1전도선(45)을 노출시키는 제1콘택홀(47)을 형성한다.Then, the second insulating layer 45 is formed to planarize the entire upper surface, and the first contact hole 47 is formed to expose the first conductive line 45 by an etching process using the first contact mask c1. do.
그 다음에, 상기 제1콘택홀(47)을 통하여 상기 제1전도선(43)에 접속되는 제2전도선(49)을 형성한다. 이때, 상기 제2전도선(49)은 상기 제1콘택홀(47)을 매립하는 콘택플러그를 형성하고 이에 접속되도록 형성할 수도 있다.Next, a second conductive line 49 is formed to be connected to the first conductive line 43 through the first contact hole 47. In this case, the second conductive line 49 may be formed to form a contact plug for filling the first contact hole 47 and to be connected thereto.
그리고, 제2전도선마스크(b)를 이용하여 상기 제2전도선(49)을 패터닝한다.The second conductive line 49 is patterned by using a second conductive line mask b.
그 다음에, 전체표면상부를 평탄화시키는 제3절연막(51)을 형성하고, 제2콘택마스크(c2)를 이용한 식각공정으로 상기 제1전도선(43)을 노출시키는 제2콘택홀(53)을 형성한다. 그리고, 상기 제2콘택홀(53)을 통하여 상기 제1전도선(43)에 접속되는 제3전도선(55)을 형성한다. 이때, 상기 제3전도선(55)은 상기 제2콘택홀(53)을 매립하는 콘택플러그를 형성하고 이에 접속되도록 형성할 수 있다.Next, a second insulating layer 51 is formed to planarize the entire upper surface, and the second contact hole 53 exposing the first conductive line 43 by an etching process using a second contact mask c2. To form. A third conductive line 55 is formed to be connected to the first conductive line 43 through the second contact hole 53. In this case, the third conductive line 55 may be formed to form a contact plug for filling the second contact hole 53 and to be connected thereto.
그 다음에, 제3전도선마스크(d)를 이용한 식각공정으로 제3전도선(55)을 패터닝한다.Next, the third conductive line 55 is patterned by an etching process using the third conductive line mask d.
상기한 바와같이 종래 기술에 따른 반도체 접속장치 및 그 제조방법은, 각각의 층을 연결할 때 콘택공정을 각각 별도로 실시하기 때문에 제조 원가가 증가하고 공정이 복잡하여 반도체소자의 생산성 및 수율을 저하시키는 문제점이 있다.As described above, the semiconductor connection apparatus and its manufacturing method according to the prior art have a problem in that the manufacturing cost is increased and the process is complicated because the contact process is performed separately when connecting the respective layers, thereby decreasing the productivity and yield of the semiconductor device. There is this.
따라서, 본 발명은 종래기술의 문제점을 해결하기 위하여, 제1전도선과 제2전도선을 형성하고 콘택마스크를 이용한 한번의 식각공정으로 상기 제1전도선에 콘택된 제2전도선을 형성하거나 상기 제1전도선에 콘택된 제3전도선을 형성함으로써 제조공정을 간단하게 하여 단가를 감소시킴으로써 반도체소자의 생산성 및 수율을 향상시킬 수 있는 반도체 접속장치를 제공하는 목적과, 반도체 접속장치 제조방법을 제공하는데 그 목적이 있다.Accordingly, in order to solve the problems of the prior art, the first conductive line and the second conductive line are formed and a second conductive line contacted to the first conductive line is formed in one etching process using a contact mask, or The purpose of the present invention is to provide a semiconductor connection device capable of improving the productivity and yield of a semiconductor device by simplifying the manufacturing process by reducing the unit cost by forming a third conductive wire contacted with the first conductive wire, and a method for manufacturing the semiconductor connection device. The purpose is to provide.
이상의 목적을 달성하기위한 본 발명인 반도체 접속장치의 특징은, 제1절연막 상부에 제1전도선이 형성되고 상기 제1전도선 상부에 제2절연막이 형성되고 상기 제2전도선 상부에 제3절연막이 구비된 후에, 상기 제1전도선에 제2전도선과 제3전도선이 각각 연결되는 반도체 접속장치에 있어서, 상기 반도체 접속장치의 일측은 상기 제3절연막과 제2전도선 그리고 제2절연막의 예정된 부분이 관통되어 상기 제1전도선과 상기 제2전도선을 접속시키는 제1콘택플러그가 구비되고, 상기 반도체 접속장치의 타측은 상기 제2전도선이 없는 예정된 부분의 제3절연막과 제2절연막이 관통되어 상기 제1전도선에 접속된 제2콘택플러그에 제3전도선이 접속되어 구비된 것이다.A feature of the semiconductor connection device of the present invention for achieving the above object is that the first conductive line is formed on the first insulating film, the second insulating film is formed on the first conductive line, and the third insulating film is formed on the second conductive line. And a second conductive line and a third conductive line are respectively connected to the first conductive line, wherein one side of the semiconductor connecting device is formed of the third insulating layer, the second conductive line and the second insulating layer. A first contact plug penetrates a predetermined portion to connect the first conductive line and the second conductive line, and the other side of the semiconductor connection device has a third insulating layer and a second insulating layer of the predetermined portion without the second conductive line. The third conductive wire is connected to the second contact plug which is penetrated and connected to the first conductive wire.
이상의 목적을 달성하기위한 본 발명인 반도체 접속장치 제조방법의 특징은, 제1전도선에 제2전도선과 제3전도선을 각각 접속시킬 수 있는 반도체 접속장치 제조방법에 있어서, 반도체기판 상부에 제1절연막을 형성하는 공정과, 상기 제1절연막 상부에 제1전도선을 형성하는 공정과, 상기 제1전도선 상부에 제2절연막을 형성하는 공정과 상기 제2절연막 상부에 제2전도선을 형성하는 공정과, 상기 제2전도선 상부에 제3절연막을 형성하는 공정과, 콘택마스크를 이용한 식각공정으로 제1,2콘택홀을 형성하는 공정과, 상기 제1,2콘택홀에 제1,2콘택플러그를 형성하는 공정과, 상기 제1전도선에 접속되는 제3전도선을 형성하는 공정을 포함하는 것이다. 또한, 상기 제1,2,3 전도선은 주성분이 알루미늄인 금속으로 형성되는 것과, 상기 제1,2,3 전도선은 Ti/Al의 이중구조로 형성되는 것과, 상기 제1,2,3 전도선은 Ti/TiN/Al의 삼중구조로 형성되는 것과, 상기 제1콘택홀은 상기 제3절연막, 제2전도선 및 제2절연막을 관통하여 형성되는 것과, 상기 제2콘택홀은 상기 제3절연막과 제2절연막을 관통하여 형성되는 것과, 상기 제1,2 콘택플러그는 텅스텐으로 형성된 것과, 상기 제1콘택플러그는 상기 제1전도선과 제2전도선을 접속시키는 것과, 상기 제2콘택플러그는 상기 제1전도선과 제3전도선을 콘택시키는 것이다.A semiconductor connecting device manufacturing method according to the present invention for achieving the above object is a semiconductor connecting device manufacturing method capable of connecting a second conductive line and a third conductive line to a first conductive line, respectively, wherein the first upper portion of the semiconductor substrate is provided. Forming an insulating film, forming a first conductive line over the first insulating film, forming a second insulating film over the first conductive line, and forming a second conductive line over the second insulating film Forming a third insulating layer on the second conductive line; forming a first and second contact holes by an etching process using a contact mask; and forming first and second contact holes in the first and second contact holes. And a step of forming a second contact plug, and a step of forming a third conductive line connected to the first conductive line. In addition, the first, second, and third conductive wires are formed of a metal whose main component is aluminum, the first, second, and third conductive wires are formed of a dual structure of Ti / Al, and the first, second, and third conductive wires The conductive line is formed of a triple structure of Ti / TiN / Al, the first contact hole is formed through the third insulating layer, the second conductive line, and the second insulating layer, and the second contact hole is the second contact hole. A third insulating film and a second insulating film formed therethrough, the first and second contact plugs are formed of tungsten, the first contact plug connecting the first conductive line and the second conductive line, and the second contact. The plug contacts the first conductive line and the third conductive line.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제2도, 제3a도 내지 제3e도는 본 발명의 실시예에 따른 반도체 접속장치의 평면도 및 그 제조공정을 도시한 단면도이다.2 and 3A to 3E are sectional views showing a plan view and a manufacturing process of the semiconductor connecting apparatus according to the embodiment of the present invention.
제2도는, 제1전도선마스크(aa)와 제2전도선마스크(bb), 제1전도선마스크(aa)와 제3전도선마스크(dd)의 콘택을 하나의 콘택마스크(cc)로 콘택할 때의 레이아웃을 도시한다.2 shows contact of the first conductive line mask (aa), the second conductive line mask (bb), the first conductive line mask (aa) and the third conductive line mask (dd) as one contact mask (cc). The layout at the time of contact is shown.
제3a도 내지 제3e도는 상기 제2도의 절단면을 따라 형성된 반도체 접속장치를 도시한 단면도로서, 일측은 ⓐ-ⓐ의 절단면을 따라 형성되고 타측은 ⓑ-ⓑ의 절단면을 따라 형성된 것이다.3A to 3E are cross-sectional views illustrating a semiconductor connection device formed along the cutting plane of FIG. 2, one side of which is formed along a cutting plane of ⓐ-ⓐ and the other side of which is formed along the cutting plane of ⓑ-ⓑ.
제3a도를 참조하면, 반도체기판(도시안됨) 상부에 형성된 제1절연막(11) 상부에 제1전도선(13)을 형성한다. 이때, 상기 제1전도선(13)은 상기 제1전도선마스크(aa)를 이용한 식각공정으로 형성된 것이다. 그리고, 상기 제1전도선(13)은 주성분이 알루미늄인 금속, Ti/Al의 이중구조 또는 Ti/TiN/Al의 삼중구조가 사용된 것이다. 그 다음에, 전체표면상부를 평탄화시키는 제2절연막(15)을 형성한다. 그리고, 상기 제2절연막(15) 상부에 제2전도선(17)을 형성한다. 이때, 상기 제2전도선(17)은 상기 제2전도선마스크(bb)를 이용한 식각공정으로 형성된 것이다. 그리고, 상기 제2전도선(17)은 주성분이 알루미늄인 금속, Ti/Al의 이중구조 또는 Ti/TiN/Al의 삼중구조가 사용된 것이다. 그 다음에, 전체표면상부를 평탄화시키는 제3절연막(19)을 형성한다. 그리고, 콘택마스크(c)를 이용한 식각공정으로 제1감광막패턴(21)을 형성한다.Referring to FIG. 3A, a first conductive line 13 is formed on the first insulating layer 11 formed on the semiconductor substrate (not shown). In this case, the first conductive line 13 is formed by an etching process using the first conductive line mask (aa). In addition, the first conductive line 13 is a metal whose main component is aluminum, a dual structure of Ti / Al, or a triple structure of Ti / TiN / Al. Next, a second insulating film 15 is formed to planarize the entire upper surface portion. The second conductive line 17 is formed on the second insulating layer 15. In this case, the second conductive line 17 is formed by an etching process using the second conductive line mask bb. The second conductive line 17 is made of a metal having a main component of aluminum, a double structure of Ti / Al, or a triple structure of Ti / TiN / Al. Next, a third insulating film 19 is formed to planarize the entire upper surface portion. Then, the first photoresist pattern 21 is formed by an etching process using the contact mask c.
제3b도를 참조하면, 상기 제1감광막패턴(21)을 마스크로 하여 상기 제2전도선(17)을 노출시키는 동시에 상기 제2절연막(15)을 노출시킨다. 이때, 상기 일측은 상기 제3절연막(19)이 식각된 것이다. 그리고, 상기 타측은 상기 제3절연막(19)과 제2절연막(15)이 식각된 것이다.Referring to FIG. 3B, the second conductive line 17 is exposed and the second insulating layer 15 is exposed using the first photoresist pattern 21 as a mask. In this case, one side of the third insulating layer 19 is etched. In the other side, the third insulating layer 19 and the second insulating layer 15 are etched.
제3c도를 참조하면, 상기 제1감광막패턴(21)을 마스크로하여 상기 제1전도선(13)을 노출시키는 제1콘택홀(23)과 제2콘택홀(25)을 형성한다. 그리고, 상기 제1감광막패턴(21)을 제거한다.Referring to FIG. 3C, the first contact hole 23 and the second contact hole 25 exposing the first conductive line 13 are formed using the first photoresist pattern 21 as a mask. Then, the first photoresist pattern 21 is removed.
제3d도를 참조하면, 상기 제1,2콘택홀(23, 25)에 콘택플러그(27)를 형성한다. 이때, 상기 콘택플러그(27)는 텅스텐으로 형성된 것이다. 여기서, 상기 콘택플러그(27)는 상기 제1전도선(13)과 제2전도선(17)을 연결한다. 그 다음에, 전체표면상부에 일정두께 제3전도물질(29)을 형성한다. 그리고, 상기 제3전도선마스크(dd)를 이용하여 제2감광막패턴(31)을 형성한다.Referring to FIG. 3D, contact plugs 27 are formed in the first and second contact holes 23 and 25. In this case, the contact plug 27 is formed of tungsten. Here, the contact plug 27 connects the first conductive line 13 and the second conductive line 17. Next, a third thickness of the third conductive material 29 is formed on the entire surface. In addition, the second photosensitive layer pattern 31 is formed using the third conductive line mask dd.
제3e도를 참조하면, 상기 제2감광막패턴(31)을 마스크로 하여 제3전도선(29)을 형성한다. 이때, 상기 제3전도선(29)은 상기 제1전도선(13)과 접속되되, 상기 제2전도선(17)과는 접속되지 않은 것이다. 그리고, 상기 제3전도선(29)은 주성분이 알루미늄인 금속, Ti/Al의 이중구조 또는 Ti/TiN/Al의 삼중구조가 사용된 것이다.Referring to FIG. 3E, a third conductive line 29 is formed using the second photosensitive film pattern 31 as a mask. In this case, the third conductive line 29 is connected to the first conductive line 13, but not to the second conductive line 17. In addition, the third conductive line 29 is made of a metal whose main component is aluminum, a dual structure of Ti / Al, or a triple structure of Ti / TiN / Al.
이상에서 설명한 바와같이 본 발명에 따른 반도체 접속장치 및 그 제조방법은, 한번의 콘택공정으로 다중의 전도선을 콘택시킬 수 있어 공정을 간단하게 하여 제조원가를 감소시킴으로써 반도체소자의 신뢰성 및 수율을 향상시킬 수 있는 잇점이 있다.As described above, the semiconductor connection device and the method of manufacturing the same according to the present invention can contact multiple conductive lines in one contact process, thereby simplifying the process and reducing the manufacturing cost, thereby improving the reliability and yield of the semiconductor device. There is an advantage to this.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006822A KR0172785B1 (en) | 1995-03-29 | 1995-03-29 | Method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006822A KR0172785B1 (en) | 1995-03-29 | 1995-03-29 | Method of manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960035823A KR960035823A (en) | 1996-10-28 |
| KR0172785B1 true KR0172785B1 (en) | 1999-03-30 |
Family
ID=19410777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950006822A KR0172785B1 (en) | 1995-03-29 | 1995-03-29 | Method of manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0172785B1 (en) |
-
1995
- 1995-03-29 KR KR1019950006822A patent/KR0172785B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960035823A (en) | 1996-10-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR970018091A (en) | Semiconductor device and manufacturing method | |
| KR970077744A (en) | Thin film transistor and manufacturing method thereof | |
| KR950011555B1 (en) | Contact structure and manufacturing method thereof | |
| KR100526059B1 (en) | Method of forming self-aligned contact in fabricating semiconductor devices | |
| KR0172785B1 (en) | Method of manufacturing semiconductor device | |
| CN112825315B (en) | Semiconductor structure and forming method thereof | |
| KR100245091B1 (en) | Process for forming interconnector of semiconductor device | |
| KR100347243B1 (en) | Method for forming metal line in semiconductor device | |
| KR910000277B1 (en) | Multilayer semiconductor | |
| JPH11186386A (en) | Semiconductor device and manufacture thereof | |
| KR100866115B1 (en) | Method for forming MIM capacitor | |
| KR100265990B1 (en) | Method for fabricating metal interconnector of semiconductor device | |
| KR100725086B1 (en) | Method for forming pad layer in process for forming multi layer line | |
| KR100196421B1 (en) | A semiconductor device and a method of fabricating the same | |
| KR0135046B1 (en) | Selective connection method of semiconductor circuit | |
| KR100447982B1 (en) | Method for forming metal interconnection of semiconductor device using buffer layer | |
| KR0166488B1 (en) | Fine contact forming method in the semiconductor device | |
| KR0161421B1 (en) | Formation method of contact hole in semiconductor device | |
| JPH02111052A (en) | Formation of multilayer interconnection | |
| KR20010004008A (en) | Method for forming metal wiring of semiconductor device having Air-gap | |
| KR100273677B1 (en) | Method for forming semiconductor device having multi layer metalization | |
| KR970003633A (en) | Method of forming a metal interlayer insulating film of a semiconductor device | |
| KR100198635B1 (en) | Fabricating method of interconnector in semiconductor device | |
| KR100398585B1 (en) | Method for connecting lead wire of semconductor device | |
| KR100227071B1 (en) | Method of forming metal wiring using antifuse |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20060920 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |