CN117012833A - Transistor structure, manufacturing method thereof and chip - Google Patents

Transistor structure, manufacturing method thereof and chip Download PDF

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Publication number
CN117012833A
CN117012833A CN202311135831.5A CN202311135831A CN117012833A CN 117012833 A CN117012833 A CN 117012833A CN 202311135831 A CN202311135831 A CN 202311135831A CN 117012833 A CN117012833 A CN 117012833A
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layer
gate
substrate
via hole
hetero
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杨航
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Innoscience Suzhou Semiconductor Co Ltd
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Innoscience Suzhou Semiconductor Co Ltd
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Priority to CN202311135831.5A priority Critical patent/CN117012833A/en
Publication of CN117012833A publication Critical patent/CN117012833A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The application provides a transistor structure, a manufacturing method thereof and a chip thereof, relates to the technical field of semiconductors, and aims to solve the problem that in the process of forming a grid electrode, the grid electrode is affected by various aspects such as a manufacturing process and the like, and the damage phenomenon of the grid electrode can occur, so that the connection characteristic between the grid electrode and a conductive structure is abnormal, the characteristic of a device is affected, and the reliability risk is brought. The transistor structure comprises a substrate, a hetero-conjunctiva layer, a gate structure and a gate connecting electrode; the hetero-conjunctiva layer, the gate structure and the gate connection electrode are sequentially stacked on the substrate along the direction away from the substrate; the gate structure comprises a first gate layer and a second gate layer, the first gate layer is positioned between the second gate layer and the hetero-conjunctiva layer, the second gate layer comprises a target part, and the orthographic projection of the target part on the substrate is not overlapped with the orthographic projection of the first gate layer on the substrate; the gate connection electrode is in contact with the target portion.

Description

Transistor structure, manufacturing method thereof and chip
Technical Field
The present application relates to the field of semiconductor technologies, and in particular, to a transistor structure, a method for manufacturing the transistor structure, and a chip.
Background
With the increasing demands of efficient and complete power conversion circuits and systems, power devices with low power consumption and high speed characteristics have attracted more and more attention. And the corresponding semiconductor devices to meet the above-mentioned demands are increasingly used in the above-mentioned circuits and systems.
Taking a semiconductor transistor as an example, a semiconductor transistor device generally includes a gate, a source, and a drain, where the gate is further led out through a conductive structure to electrically connect with an external structure. However, during the process of forming the gate, the gate may be damaged due to various aspects such as a manufacturing process, which may cause abnormal connection characteristics between the gate and the conductive structure, thereby affecting the characteristics of the device and bringing reliability risks.
Disclosure of Invention
The application aims to provide a transistor structure, a manufacturing method thereof and a chip thereof, which are used for solving the problem that the gate is possibly damaged due to the influence of various aspects such as manufacturing process and the like in the process of forming the gate, and the connection characteristic between the gate and a conductive structure is abnormal, so that the characteristic of a device is influenced and the reliability risk is brought.
In order to achieve the above object, the present application provides the following technical solutions:
a first aspect of the present application provides a transistor structure comprising: a substrate, a hetero-conjunctiva layer, a gate structure and a gate connection electrode; the hetero-conjunctiva layer, the gate structure and the gate connection electrode are sequentially stacked on the substrate along the direction away from the substrate;
the gate structure comprises a first gate layer and a second gate layer, the first gate layer is positioned between the second gate layer and the hetero-conjunctiva layer, the second gate layer comprises a target part, and the orthographic projection of the target part on the substrate is not overlapped with the orthographic projection of the first gate layer on the substrate;
the gate connection electrode is in contact with the target portion.
Optionally, the transistor structure further includes a first dielectric layer and a second dielectric layer;
the first dielectric layer is positioned on one side of the heterojunction film layer, which is away from the substrate, and comprises a first via hole, at least part of the first gate layer is positioned in the first via hole, and the part of the first gate layer positioned in the first via hole is in contact with the heterojunction film layer;
at least part of the second dielectric layer is positioned on one side of the gate structure, which is away from the substrate, the second dielectric layer comprises a second via hole, at least part of the gate connecting electrode is positioned in the second via hole, and the part of the gate connecting electrode positioned in the second via hole is in contact with the target part.
Optionally, in a direction perpendicular to the substrate, a thickness of the first gate layer is greater than a thickness of the first dielectric layer; at least a portion of the first dielectric layer is located between the second gate layer and the hetero-conjunctiva layer.
Optionally, the target portion includes at least one end of the second gate layer along a first direction, the first direction including an extension direction of the second gate layer.
Optionally, the hetero-conjunctiva layer includes a gallium nitride layer and an aluminum gallium nitride layer, the gallium nitride layer being located between the substrate and the aluminum gallium nitride layer; and/or the number of the groups of groups,
the first gate layer comprises a P-type gallium nitride layer; and/or the number of the groups of groups,
the second gate layer includes a titanium nitride layer.
Optionally, the transistor structure further includes a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively in contact with the hetero-conjunctiva layer.
Based on the technical scheme of the transistor structure, a second aspect of the application provides a chip, which comprises the transistor structure.
Based on the technical scheme of the transistor structure, a third aspect of the present application provides a method for manufacturing a transistor structure, which is used for manufacturing the transistor structure, and the manufacturing method includes:
manufacturing a hetero-conjunctiva layer on a substrate;
a grid structure is manufactured on one side, facing away from the substrate, of the hetero-conjunctiva layer, the grid structure comprises a first grid layer and a second grid layer, the first grid layer is located between the second grid layer and the hetero-conjunctiva layer, the second grid layer comprises a target portion, and orthographic projection of the target portion on the substrate does not overlap with orthographic projection of the first grid layer on the substrate;
and manufacturing a gate connecting electrode on one side of the gate structure, which is opposite to the substrate, wherein the gate connecting electrode is contacted with the target part.
Optionally, the step of fabricating the gate structure specifically includes:
manufacturing a first dielectric layer on one side of the heterojunction film layer, which is opposite to the substrate, and forming a first via hole on the first dielectric layer, wherein part of the heterojunction film layer is exposed by the first via hole;
manufacturing a first gate layer, wherein at least part of the first gate layer is positioned in the first via hole, and the part of the first gate layer positioned in the first via hole is in contact with the heteroconjunctival layer;
a second gate layer is fabricated, the second gate layer covering at least a portion of the first gate layer.
Optionally, the step of fabricating the gate connection electrode specifically includes:
manufacturing a second dielectric layer on one side of the grid structure, which is opposite to the substrate, and forming a second via hole on the second dielectric layer, wherein at least part of the target part is exposed by the second via hole;
and manufacturing a gate connecting electrode, wherein at least part of the gate connecting electrode is positioned in the second via hole, and the part of the gate connecting electrode positioned in the second via hole is contacted with the target part.
In the technical scheme provided by the application, the grid structure comprises a first grid layer and a second grid layer, the first grid layer is positioned between the second grid layer and the hetero-conjunctiva layer, the second grid layer comprises a target part, the orthographic projection of the target part on the substrate is not overlapped with the orthographic projection of the first grid layer on the substrate, and the grid connecting electrode is in contact with the target part. This arrangement is such that even if a gap is present in the non-target portion, the gate connection electrode does not contact the first gate layer at the gap. Moreover, the arrangement is such that even if a gap is present in the target portion, the gap does not expose the first gate layer, so that the gate connection electrode does not contact the first gate layer when it contacts the target portion. Therefore, in the technical scheme provided by the application, the gate connecting electrode is only in contact with the second gate layer in the gate structure, but not in contact with the first gate layer in the gate structure, so that the characteristics of the transistor structure are ensured, and the reliability risk of the transistor structure is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
fig. 1 is a schematic diagram of forming a hetero-junction film layer and a first gate material layer in a transistor structure according to the present application;
fig. 2 is a schematic diagram of forming a second gate material layer on the basis of fig. 1 according to the present application;
FIG. 3 is a schematic diagram of forming a gate structure according to the present application;
fig. 4 is a schematic cross-sectional view of a transistor structure according to the present application;
FIG. 5 is a schematic diagram of particle defects generated during the fabrication of a gate structure according to the present application;
fig. 6 is a second cross-sectional schematic diagram of a transistor structure provided by the present application;
FIG. 7 is a schematic diagram of forming a hetero-conjunctiva layer and a first dielectric material layer on a substrate according to an embodiment of the present application;
fig. 8 is a schematic diagram illustrating formation of a first via hole on a first dielectric material layer according to an embodiment of the present application;
fig. 9 is a schematic diagram of forming a first gate layer according to an embodiment of the present application;
fig. 10 is a schematic diagram illustrating formation of a second gate layer according to an embodiment of the present application;
FIG. 11 is a schematic cross-sectional view taken along the direction A1A2 in FIG. 15;
FIG. 12 is a schematic diagram of particle defects generated during the fabrication of a gate structure according to an embodiment of the present application;
fig. 13 is a schematic third cross-sectional view of a transistor structure according to an embodiment of the present application;
FIG. 14 is a schematic cross-sectional view taken along the direction A3A4 in FIG. 15;
fig. 15 is a schematic top view of a gate structure and source and drain electrodes in a transistor structure according to an embodiment of the present application.
Detailed Description
In order to further explain the transistor structure, the manufacturing method and the chip provided by the embodiment of the application, the following detailed description is made with reference to the accompanying drawings.
Based on the problems existing in the background technology, the inventor of the present application finds that the process flow for manufacturing the transistor structure is as follows:
as shown in fig. 1, a hetero-conjunctiva layer 20 and a first gate material layer 31 are sequentially formed on a substrate 10.
As shown in fig. 2, the sputter growth of the second gate material layer 32 is continued on the side of the first gate material layer 31 facing away from the substrate 10.
As shown in fig. 3, the first gate material layer 31 and the second gate material layer 32 are subjected to a patterning process to form a first gate layer 301 and a second gate layer 302.
As shown in fig. 4, the dielectric layer 50 and the gate connection electrode 40 continue to be formed.
In the above manufacturing process, as shown in fig. 5, particle defects (i.e., particlefect) are easily present on the first gate layer 301, such as the black pattern in fig. 5. Such particle defects may cause the second gate material layer 32 to be deposited at a position where the particle defect is located, so that when the second gate layer 302 formed by the second gate material layer 32 is led out upwards through the gate connection electrode 40, the etching process directly etches the first gate layer 301, as shown in fig. 6, resulting in damage to the first gate layer 301, and the subsequently formed gate connection electrode 40 directly contacts the first gate layer 301, thereby affecting the characteristics of the device and bringing a reliability risk.
Referring to fig. 10 to 15, an embodiment of the present application provides a transistor structure, including: a substrate 10, a hetero-conjunctiva layer 20, a gate structure 30 and a gate connection electrode 40; the hetero-conjunctiva layer 20, the gate structure 30 and the gate connection electrode 40 are sequentially stacked on the substrate 10 in a direction away from the substrate 10;
the gate structure 30 comprises a first gate layer 301 and a second gate layer 302, the first gate layer 301 being located between the second gate layer 302 and the hetero-conjunctiva layer 20, the second gate layer 302 comprising a target portion 3021, an orthographic projection of the target portion 3021 onto the substrate 10 not overlapping with an orthographic projection of the first gate layer 301 onto the substrate 10;
the gate connection electrode 40 is in contact with the target portion 3021.
The substrate 10 may be exemplified by, but not limited to, a SiC substrate or a Si substrate.
Illustratively, the hetero-conjunctival layer 20 includes a buffer layer and a barrier layer disposed in a stack, the buffer layer being located between the substrate 10 and the barrier layer. The buffer layer includes a gallium nitride layer (GaN layer) and the barrier layer includes an aluminum gallium nitride layer (AlGaN layer), but is not limited thereto.
Illustratively, the hetero-conjunctival layer 20 has a relatively large area and may be fabricated entirely on the substrate 10, but is not limited thereto.
As shown in fig. 10, the second gate layer 302 includes a target portion 3021 and a non-target portion 3022, the target portion 3021 and the non-target portion 3022 are formed as a unitary structure, an orthographic projection of the target portion 3021 on the substrate 10 does not overlap with an orthographic projection of the first gate layer 301 on the substrate 10, and an orthographic projection of the non-target portion 3022 on the substrate 10 overlaps with an orthographic projection of the first gate layer 301 on the substrate 10.
Illustratively, the first gate layer 301 includes a P-type gallium nitride layer and the second gate layer 302 includes a titanium nitride layer, but is not limited thereto.
Illustratively, after forming the gate structure 30, a dielectric layer may be continuously formed, and then a via hole is formed on the dielectric layer, through which the gate connection electrode 40 contacts the target portion 3021 of the gate structure 30; alternatively, after the gate structure 30 is formed, the gate connection electrode 40 is directly formed, and the gate connection electrode 40 is directly overlapped on the target portion 3021. The gate connection electrode 40 is equivalent to the extraction of the gate structure 30, and electrically connects to an external structure.
It should be noted that, during the process of forming the gate structure 30, particle defects may cause defects in the second gate layer 302, so that a gap exists in the second gate layer 302, and the gap exposes the first gate layer 301.
In the above case, if the gate connection electrode 40 is formed in the via hole of the dielectric layer to achieve the connection between the gate connection electrode 40 and the gate structure 30, the etching process involved in the via hole manufacturing process may form a notch in the second gate layer 302, and etch the first gate layer 301, so as to cause damage to the first gate layer 301, so that the via hole formed on the dielectric layer may expose a portion of the first gate layer 301, which may cause the gate connection electrode 40 to contact with the first gate layer 301, and such contact may affect the characteristics of the transistor structure, and increase the leakage risk of the transistor structure.
In the above case, if the connection between the gate connection electrode 40 and the gate structure 30 is implemented in such a manner that the gate connection electrode 40 is directly overlapped with the gate structure 30, the gate connection electrode 40 may contact the first gate layer 301 at a notch formed by the second gate layer 302, resulting in affecting the characteristics of the transistor structure and increasing the leakage risk of the transistor structure.
As can be seen from the specific structure of the transistor structure described above, in the transistor structure provided in the embodiment of the present application, the gate structure 30 includes the first gate layer 301 and the second gate layer 302, the first gate layer 301 is located between the second gate layer 302 and the hetero-conjunctiva layer 20, the second gate layer 302 includes the target portion 3021, the front projection of the target portion 3021 on the substrate 10 and the front projection of the first gate layer 301 on the substrate 10 do not overlap, and the gate connection electrode 40 is in contact with the target portion 3021. As shown in fig. 12 and 13, this arrangement is such that even if a gap exists in the non-target portion 3022, the gate connection electrode 40 does not contact the first gate layer 301 at the gap. Moreover, the arrangement is such that even if a gap is present in the target portion 3021, the gap does not expose the first gate layer 301, and thus the gate connection electrode 40 does not contact the first gate layer 301 when it contacts the target portion 3021. Therefore, in the transistor structure provided by the embodiment of the application, the gate connection electrode 40 is only in contact with the second gate layer 302 in the gate structure 30, but not in contact with the first gate layer 301 in the gate structure 30, so that the characteristics of the transistor structure are ensured, and the reliability risk of the transistor structure is reduced.
As shown in fig. 8-11, in some embodiments, the transistor structure further includes a first dielectric layer 51 and a second dielectric layer 52;
the first dielectric layer 51 is located on the side of the hetero-conjunctiva layer 20 facing away from the substrate 10, the first dielectric layer 51 comprises a first Via1, at least a portion of the first gate layer 301 is located within the first Via1, and a portion of the first gate layer 301 located within the first Via1 is in contact with the hetero-conjunctiva layer 20;
at least a portion of the second dielectric layer 52 is located on a side of the gate structure 30 facing away from the substrate 10, the second dielectric layer 52 includes a second Via2, at least a portion of the gate connection electrode 40 is located within the second Via2, and a portion of the gate connection electrode 40 located within the second Via2 is in contact with the target portion 3021.
Illustratively, the first dielectric layer 51 and the second dielectric layer 52 each include an insulating layer. The first dielectric layer 51 includes a nitride insulating layer or an oxide insulating layer. The second dielectric layer 52 includes a nitride insulating layer or an oxide insulating layer.
Illustratively, the thickness of the first gate layer 301 is greater than the thickness of the first dielectric layer 51 in a direction perpendicular to the substrate 10. At least a portion of the first dielectric layer 51 is located between the second gate layer 302 and the hetero-conjunctiva layer 20. For example: at least a portion of the first dielectric layer 51 is located between the target portion 3021 and the hetero-conjunctiva layer 20. This arrangement is such that the first gate layer 301 protrudes from the first dielectric layer 51 in a direction away from the substrate 10. In this way, the second gate layer 302 can not only contact the surface of the first gate layer 301 facing away from the substrate 10, but also contact the side surface of the first gate layer 301 located outside the first Via hole Via1, so as to increase the contact area between the second gate layer 302 and the first gate layer 301, which is beneficial to improving the device performance of the transistor structure.
Illustratively, the thickness of the first gate layer 301 is equal to the thickness of the first dielectric layer 51 in a direction perpendicular to the substrate 10. In this case, the second gate layer 302 can be in contact with the surface of the first gate layer 301 facing away from the substrate 10. The second gate layer 302 is located outside the first Via 1.
Illustratively, the thickness of the first gate layer 301 is less than the thickness of the first dielectric layer 51 in a direction perpendicular to the substrate 10. In this case, the second gate layer 302 can be in contact with the surface of the first gate layer 301 facing away from the substrate 10. A portion of the second gate layer 302 is located outside the first Via hole Via1, and another portion of the second gate layer 302 is located inside the first Via hole Via 1.
Illustratively, the second dielectric layer 52 includes at least one second Via Via2, the transistor structure includes at least one gate connection electrode 40, at least a portion of the gate connection electrode 40 is located in the corresponding second Via hole Via2, and a portion of the gate connection electrode 40 located in the second Via hole Via2 is in contact with the target portion 3021.
Illustratively, the second dielectric layer 52 includes two of the second vias Via2, and the transistor structure includes two of the gate connection electrodes 40.
In the transistor structure provided in the foregoing embodiment, at least a portion of the gate connection electrode 40 is disposed in the second Via hole Via2 formed by the second dielectric layer 52, and is in contact with the gate structure 30 through the second Via hole Via2, so as to facilitate improving the connection performance between the gate connection electrode 40 and the gate structure 30, and improving the reliability of the transistor structure in the application process.
In the transistor structure provided in the foregoing embodiment, the second Via hole Via2 exposes the target portion 3021, and the orthographic projection of the target portion 3021 on the substrate 10 does not overlap with the orthographic projection of the first gate layer 301 on the substrate 10, so that the etching process for forming the second Via hole Via2 does not etch the first gate layer 301, thereby avoiding damage to the first gate layer 301, and well ensuring the device performance of the transistor structure.
As shown in fig. 11 and 15, in some embodiments, the target portion 3021 includes at least one end of the second gate layer 302 along a first direction including an extension direction of the second gate layer 302.
Illustratively, the target portion 3021 includes, but is not limited to, two opposite ends of the second gate layer 302 along the first direction.
The arrangement mode is beneficial to reducing the volume of the transistor structure and enhancing the practicability of the transistor structure on the basis of ensuring the characteristics of the transistor structure.
As shown in fig. 14, in some embodiments, the transistor structure further includes a source electrode S and a drain electrode D, which are respectively in contact with the hetero-conjunctiva layer 20.
The source electrode S and the drain electrode D may be, for example, but not limited to, a stacked structure of metallic aluminum and metallic titanium.
Illustratively, the transistor structure further includes a third dielectric layer 53, the source electrode S is in contact with the hetero-conjunctiva layer 20 through a via penetrating the first dielectric layer 51 and the third dielectric layer 53, and the drain electrode D is in contact with the hetero-conjunctiva layer 20 through a via penetrating the first dielectric layer 51 and the third dielectric layer 53.
Illustratively, the transistor structure further includes a source connection electrode 41 and a drain connection electrode 42, where the source connection electrode 41 is coupled to the source electrode S through a via penetrating the second dielectric layer 52, and can electrically connect the source electrode S to an external structure. The drain electrode connection electrode is coupled with the drain electrode D through a via hole penetrating through the second dielectric layer 52, so that the drain electrode D can be led out and electrically connected with an external structure.
The transistor structure provided by the embodiment can be formed into a gallium nitride transistor structure, and has the advantages of high frequency, high power, high temperature, high reliability and the like.
The embodiment of the application also provides a chip, which comprises the transistor structure provided by the embodiment.
In the transistor structure provided in the foregoing embodiment, the gate structure 30 is provided to include the first gate layer 301 and the second gate layer 302, the first gate layer 301 is located between the second gate layer 302 and the hetero-conjunctiva layer 20, the second gate layer 302 includes the target portion 3021, the orthographic projection of the target portion 3021 on the substrate 10 does not overlap with the orthographic projection of the first gate layer 301 on the substrate 10, and the gate connection electrode 40 is in contact with the target portion 3021. This arrangement is such that even if a gap exists in the non-target portion 3022, the gate connection electrode 40 does not contact the first gate layer 301 at the gap. Moreover, the arrangement is such that even if a gap is present in the target portion 3021, the gap does not expose the first gate layer 301, and thus the gate connection electrode 40 does not contact the first gate layer 301 when it contacts the target portion 3021. Therefore, in the transistor structure provided in the above embodiment, the gate connection electrode 40 is only in contact with the second gate layer 302 in the gate structure 30, but not in contact with the first gate layer 301 in the gate structure 30, so that the characteristics of the transistor structure are ensured, and the reliability risk of the transistor structure is reduced.
The chip provided by the embodiment of the application has the same beneficial effects when the transistor structure is included, and the description is omitted here.
The embodiment of the application also provides a manufacturing method of the transistor structure, which is characterized by comprising the following steps of:
fabricating a hetero-conjunctiva layer 20 on the substrate 10;
a gate structure 30 is fabricated on a side of the hetero-conjunctiva layer 20 facing away from the substrate 10, the gate structure 30 includes a first gate layer 301 and a second gate layer 302, the first gate layer 301 is located between the second gate layer 302 and the hetero-conjunctiva layer 20, the second gate layer 302 includes a target portion 3021, and an orthographic projection of the target portion 3021 on the substrate 10 does not overlap with an orthographic projection of the first gate layer 301 on the substrate 10;
a gate connection electrode 40 is fabricated on a side of the gate structure 30 facing away from the substrate 10, the gate connection electrode 40 being in contact with the target portion 3021.
In the transistor structure manufactured by the manufacturing method provided by the embodiment of the present application, the gate structure 30 includes a first gate layer 301 and a second gate layer 302, the first gate layer 301 is located between the second gate layer 302 and the hetero-conjunctiva layer 20, the second gate layer 302 includes a target portion 3021, an orthographic projection of the target portion 3021 on the substrate 10 and an orthographic projection of the first gate layer 301 on the substrate 10 do not overlap, and the gate connection electrode 40 is in contact with the target portion 3021. This structure makes the gate connection electrode 40 not to contact the first gate layer 301 at the notch even if the notch exists on the non-target portion 3022. Moreover, the arrangement is such that even if a gap is present in the target portion 3021, the gap does not expose the first gate layer 301, and thus the gate connection electrode 40 does not contact the first gate layer 301 when it contacts the target portion 3021. Therefore, in the transistor structure manufactured by the manufacturing method provided by the embodiment of the application, the gate connection electrode 40 is only in contact with the second gate layer 302 in the gate structure 30, but not in contact with the first gate layer 301 in the gate structure 30, so that the characteristics of the transistor structure are ensured, and the reliability risk of the transistor structure is reduced.
As shown in fig. 8 to 10, in some embodiments, the step of fabricating the gate structure 30 specifically includes:
a first dielectric layer 51 is manufactured on one side of the heterojunction film layer 20, which is away from the substrate 10, and a first Via hole Via1 is formed on the first dielectric layer 51, wherein a part of the heterojunction film layer 20 is exposed by the first Via hole Via 1;
fabricating a first gate layer 301, wherein at least part of the first gate layer 301 is located in the first Via hole Via1, and the part of the first gate layer 301 located in the first Via hole Via1 is in contact with the hetero-conjunctiva layer 20;
a second gate layer 302 is fabricated, said second gate layer 302 covering at least part of said first gate layer 301.
As shown in fig. 11, in some embodiments, the step of fabricating the gate connection electrode 40 specifically includes:
a second dielectric layer 52 is manufactured on one side of the gate structure 30 facing away from the substrate 10, and a second Via hole Via2 is formed on the second dielectric layer 52, wherein at least part of the target portion 3021 is exposed by the second Via hole Via 2;
a gate connection electrode 40 is fabricated, at least a portion of the gate connection electrode 40 is located in the second Via hole Via2, and a portion of the gate connection electrode 40 located in the second Via hole Via2 is in contact with the target portion 3021.
More specifically, the specific process for fabricating the transistor structure is as follows:
as shown in fig. 7, a hetero-conjunctiva layer 20 and a first dielectric material layer 5 are sequentially formed on a substrate 10. The first dielectric material layer 5 may be formed by deposition. The hetero-conjunctival layer 20 may be formed as a large-area whole-surface structure.
As shown in fig. 8, the first dielectric material layer 5 is subjected to a patterning process, which may include a photolithography process, to form a first dielectric layer 51 including a first Via hole Via1, where the first Via hole Via1 exposes a portion of the hetero-conjunctiva layer 20. The orthographic projection of the first Via1 on the substrate 10 includes a stripe pattern.
As shown in fig. 9, an exemplary first gate material layer is formed, and a patterning process is performed on the first gate material layer to form a first gate layer 301, at least a portion of the first gate layer 301 is located in the first Via hole Via1, and a portion of the first gate layer 301 located in the first Via hole Via1 is in contact with the hetero-conjunctiva layer 20. The first gate material layer may be formed by deposition.
As shown in fig. 10, an exemplary second gate material layer is formed, and a patterning process is performed on the second gate material layer to form a second gate layer 302, where the second gate layer 302 covers at least a portion of the first gate layer 301. The second gate layer 302 comprises a target portion 3021 and a non-target portion 3022, the front projection of the target portion 3021 onto the substrate 10 does not overlap with the front projection of the first gate layer 301 onto the substrate 10, and the front projection of the non-target portion 3022 onto the substrate 10 overlaps with the front projection of the first gate layer 301 onto the substrate 10. The second gate material layer may be formed by sputtering. And along the extending direction of the second gate pattern, the length of the second gate pattern is longer than that of the first gate pattern.
As shown in fig. 11 and 14, the third dielectric layer 53 is illustratively deposited, and a surface of the third dielectric layer 53 facing away from the substrate 10 may be flush with a surface of the second gate layer 302 facing away from the substrate 10. Then, a Via hole penetrating the first dielectric layer 51 and the third dielectric layer 53 is formed, then a source electrode S and a drain electrode D are formed, then a second dielectric layer 52 is formed, a plurality of Via holes are formed on the second dielectric layer 52, a part of the Via holes are the second Via holes Via2, at least a part of the target portion 3021 can be exposed, and another part of the Via holes can expose the source electrode S and the drain electrode D. Finally, the gate connection electrode 40, the source connection electrode 41 and the drain connection electrode 42 are simultaneously formed through the same patterning process. At least a portion of the gate connection electrode 40 is located within the second Via2, and a portion of the gate connection electrode 40 located within the second Via2 is in contact with the target portion 3021. The source connection electrode 41 and the drain connection electrode 42 are located in the other part of the via hole to achieve contact with the respective source electrode S and drain electrode D.
It should be noted that "same layer" in the embodiments of the present application may refer to a film layer on the same structural layer. Or, for example, the film layers in the same layer may be a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process and then patterning the film layer by one patterning process using the same mask plate. Depending on the particular pattern, a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.
In the method embodiments of the present application, the serial numbers of the steps are not used to define the sequence of the steps, and it is within the scope of the present application for those skilled in the art to change the sequence of the steps without performing any creative effort.
In this specification, all embodiments are described in a progressive manner, and identical and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in a different way from other embodiments. In particular, for the method embodiments, since they are substantially similar to the product embodiments, the description is relatively simple, and reference is made to the section of the product embodiments for relevant points.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may also include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A transistor structure, comprising: a substrate, a hetero-conjunctiva layer, a gate structure and a gate connection electrode; the hetero-conjunctiva layer, the gate structure and the gate connection electrode are sequentially stacked on the substrate along the direction away from the substrate;
the gate structure comprises a first gate layer and a second gate layer, the first gate layer is positioned between the second gate layer and the hetero-conjunctiva layer, the second gate layer comprises a target part, and the orthographic projection of the target part on the substrate is not overlapped with the orthographic projection of the first gate layer on the substrate;
the gate connection electrode is in contact with the target portion.
2. The transistor structure of claim 1, further comprising a first dielectric layer and a second dielectric layer;
the first dielectric layer is positioned on one side of the heterojunction film layer, which is away from the substrate, and comprises a first via hole, at least part of the first gate layer is positioned in the first via hole, and the part of the first gate layer positioned in the first via hole is in contact with the heterojunction film layer;
at least part of the second dielectric layer is positioned on one side of the gate structure, which is away from the substrate, the second dielectric layer comprises a second via hole, at least part of the gate connecting electrode is positioned in the second via hole, and the part of the gate connecting electrode positioned in the second via hole is in contact with the target part.
3. The transistor structure of claim 2, wherein a thickness of the first gate layer is greater than a thickness of the first dielectric layer in a direction perpendicular to the substrate; at least a portion of the first dielectric layer is located between the second gate layer and the hetero-conjunctiva layer.
4. The transistor structure of claim 1, wherein the target portion comprises at least one end of the second gate layer along a first direction, the first direction comprising an extension direction of the second gate layer.
5. The transistor structure of claim 2, wherein the hetero-conjunctiva layer comprises a gallium nitride layer and an aluminum gallium nitride layer, the gallium nitride layer being located between the substrate and the aluminum gallium nitride layer; and/or the number of the groups of groups,
the first gate layer comprises a P-type gallium nitride layer; and/or the number of the groups of groups,
the second gate layer includes a titanium nitride layer.
6. The transistor structure of claim 1, further comprising a source electrode and a drain electrode, the source electrode and the drain electrode being in contact with the hetero-conjunctiva layer, respectively.
7. A chip comprising a transistor structure according to any one of claims 1 to 6.
8. A method of fabricating a transistor structure according to any one of claims 1 to 6, the method comprising:
manufacturing a hetero-conjunctiva layer on a substrate;
a grid structure is manufactured on one side, facing away from the substrate, of the hetero-conjunctiva layer, the grid structure comprises a first grid layer and a second grid layer, the first grid layer is located between the second grid layer and the hetero-conjunctiva layer, the second grid layer comprises a target portion, and orthographic projection of the target portion on the substrate does not overlap with orthographic projection of the first grid layer on the substrate;
and manufacturing a gate connecting electrode on one side of the gate structure, which is opposite to the substrate, wherein the gate connecting electrode is contacted with the target part.
9. The method of fabricating a transistor structure according to claim 8, wherein the step of fabricating the gate structure comprises:
manufacturing a first dielectric layer on one side of the heterojunction film layer, which is opposite to the substrate, and forming a first via hole on the first dielectric layer, wherein part of the heterojunction film layer is exposed by the first via hole;
manufacturing a first gate layer, wherein at least part of the first gate layer is positioned in the first via hole, and the part of the first gate layer positioned in the first via hole is in contact with the heteroconjunctival layer;
a second gate layer is fabricated, the second gate layer covering at least a portion of the first gate layer.
10. The method of fabricating a transistor structure according to claim 8, wherein the step of fabricating the gate connection electrode comprises:
manufacturing a second dielectric layer on one side of the grid structure, which is opposite to the substrate, and forming a second via hole on the second dielectric layer, wherein at least part of the target part is exposed by the second via hole;
and manufacturing a gate connecting electrode, wherein at least part of the gate connecting electrode is positioned in the second via hole, and the part of the gate connecting electrode positioned in the second via hole is contacted with the target part.
CN202311135831.5A 2023-09-05 2023-09-05 Transistor structure, manufacturing method thereof and chip Pending CN117012833A (en)

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Application Number Priority Date Filing Date Title
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