JP3247729B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to manufacturing methods around the contact hole in a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art FIG. 2 is a process sectional view showing a method of forming a contact in the case of a three-layer wiring in a conventional semiconductor device.

First, an insulating film A12 is formed on a Si substrate 1, and a contact hole is formed at a predetermined position by using a known photolithography (photolithography) etching technique. Then, a wiring material A13 is formed and patterned. (Figure 2
(A)).

Next, in order to connect the first-layer wiring 13 and the second-layer wiring 15 (or to connect the Si substrate 1 and the second-layer wiring 15), a first-layer wiring is further provided. A13
An insulating film B14 is formed thereon, and a contact hole is formed in the insulating film B14 using a photolithography etching technique.
5 is formed and patterned (FIG. 2B).

Next, in order to connect the wiring 15 of the second layer and the wiring 17 of the third layer, an insulating film C16 is similarly formed to form a contact hole, and a wiring material C17 is formed and patterned. (FIG. 2C).

That is, an intermediate insulating film is formed for each wiring layer, a contact hole is formed in the intermediate insulating film, and electrical connection between the wiring layers is made by the wiring layer formed in the contact hole. Had formed. Needless to say, there is no need for a contact hole in the insulating film between the wiring layers that does not require the connection.

[0007]

However, in the above-described method for forming a contact hole for a multilayer wiring, in the case of a three-layer wiring, the photolithographic etching step is performed for the first contact hole,
The first wiring, the second contact hole, the second wiring, the third contact hole, and the third wiring must be performed six times in total (four times in the case of two layers). Was.

According to the present invention, as described above, in order to eliminate the problem that the number of steps is large and the production time is long, for example, in the case of three-layer wiring, three contact holes are formed by photolithography. An object of the present invention is to perform an etching step only once, to shorten a product creation time, and to easily form a contact hole excellent in miniaturization.

[0009]

SUMMARY OF THE INVENTION The present invention relates to a method for forming a connection hole in a region of a semiconductor substrate where connection between the semiconductor substrate and a wiring layer is unnecessary in the formation of a semiconductor device having a multilayer wiring.
After forming a layer that inhibits electrical connection as an etching stopper , generate and pattern multiple layers of wiring, pattern the uppermost wiring, generate an insulating film, and then remove each wiring layer that needs connection. A contact hole that penetrates and reaches the semiconductor substrate and a contact hole that does not reach the semiconductor substrate are formed, a conductive material is buried, and a plurality of wiring layers are connected. -Can be created by an etching process.

[0010]

As described above, according to the present invention, after a plurality of wiring layers are formed, a contact hole reaching a semiconductor substrate is formed.
The contact holes that do not reach the conductive substrate are formed at once, and the contact holes are filled with a conductive material to connect the wiring of each layer, so that the number of photolithography and etching steps for contact formation is one. Therefore, it is possible to reduce the time required for product creation.

[0011]

1 is a manufacturing process diagram showing an embodiment of the present invention.

This embodiment also exemplifies a case of a three-layer wiring structure.

First, a nitride film 2 for use as an etching stopper is formed on a Si substrate 1 by a CVD (Chemical Vapor Deposition) method at about 2000.degree.
Using an etching technique, patterning is performed so as to remain at a predetermined position described later.

Next, an insulating oxide film A (SiO ₂ ) is formed thereon.
3 is formed by CVD at about 5000 to 8000 °, and a wiring material A (for example, Al is used,
000-9000 °) 4 is generated and patterned as wiring (FIG. 1A).

Further, similarly, an insulating oxide film B (CVD Si
A film pressure of 5000 to 8000 °) 5 is formed with O ₂ , and a wiring material B (film pressure of 5000 to 9000 °) such as Al is generated and patterned. Furthermore, the insulating oxide film C 7 thereon, thereon generate three-layer wiring C8, and patterned to produce an insulating oxide film D9 thereon after (FIG. 1 (b)), known Using the resist pattern 11 as a mask by photolithographic etching, a contact hole 10 is formed so as to penetrate the wiring layers 4, 6, 8 up to the Si substrate 1 or at least contact the wiring layer (so that the side walls of the wiring layer are exposed). I do. However, in the portion where the etching stopper nitride film 2 is present on the Si substrate 1, the etching stops on the nitride film 2 due to the difference in the etching conditions, and the etching stops.
The contact hole 10 does not reach this point (FIG. 1C).
A diffusion layer or the like is formed on the substrate 1, and the etching stopper layer 2 is not provided at a place where connection with the diffusion layer is required (the contact hole on the left side of FIG. 1B is an example).

Next, a conductive material (for example, tungsten or polysilicon) 19 is generated to be buried in the contact hole 10 using an existing filling technique (FIG. 1D), and a conductive material (wiring material D) is formed. The etch back is performed so that 19 remains only in the contact hole 10. By this embedding, the wiring layers 4, 6, and 8 of each layer can be electrically connected (FIG. 1E).

In this embodiment, all the wiring layers need to be connected. Needless to say, no contact holes are provided between wiring layers that do not require connection, or the wiring layers are formed so as to avoid the contact holes. You should keep it.

Further, in this embodiment, the wiring material is Al, but it is also possible to use PolySi (polycrystalline silicon) or W / Six. In this case, the film thickness is 1500-4000 ° and the interlayer insulating film is 1500-4000 ° I do.

[0019]

As described above, according to the present invention, in the formation of a semiconductor device having a multilayer wiring structure , a contact hole reaching a semiconductor substrate after forming a wiring of each layer , and
A contact hole that does not reach the conductor substrate is formed in the same step, and the contact hole is buried with a conductive material to connect the wiring of each layer, so that the contact-type photolithography / etching step is completed only once. Therefore, it is possible to reduce the time required for product creation.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 Conventional example

[Explanation of symbols]

Reference Signs List 1 Si substrate 2 Etching stopper nitride film 3 Insulating oxide film A 4 Wiring material A 5 Insulating oxide film B 6 Wiring material B 7 Insulating oxide film C 8 Wiring material C 9 Insulating oxide film D 10 Contact hole 19 Wiring material D

Claims (2)

(57) [Claims] In a method of manufacturing a semiconductor device having a multilayer wiring structure , an etching stopper is formed when a connection hole is formed in a region of the semiconductor substrate where connection between the semiconductor substrate and a wiring layer is unnecessary.
Forming a layer prohibiting electrical connection to be formed, and at least a first insulating film and a first insulating film on the semiconductor substrate .
A wiring layer, a second insulating film, a second wiring layer, a third insulating film,
When sequentially forming the third wiring layer, in a region where a connection hole is formed, a wiring layer that is to be electrically connected to each other extends to a region where the connection hole is formed, and the other wiring layers are connected to the connection hole. Forming each wiring layer so as not to extend to a region where the connection hole is formed; and penetrating each wiring layer in a region where the connection hole where the layer for inhibiting electrical connection is not formed is formed. Forming a connection hole reaching the semiconductor substrate, in a region where the connection hole is formed in which a layer for inhibiting the electrical connection is formed,
A method of manufacturing a semiconductor device, comprising: forming a connection hole penetrating through each of the wiring layers and not reaching the semiconductor substrate; and embedding a conductive material in the connection hole. 2. A method for manufacturing a semiconductor device having a multi-layer wiring structure, comprising: forming an etching stopper in a region of the semiconductor substrate where connection between the semiconductor substrate and a wiring layer is not required ;
Forming a layer for inhibiting the electrical connection to be, on the semiconductor substrate, at least a first insulating film, a first wiring layer, a second insulating film, when the second wiring layer are sequentially formed In a region where a connection hole is formed, a wiring layer to be electrically connected to each other extends to a region where the connection hole is formed, and other wiring layers do not extend to a region where the connection hole is formed. A step of forming each wiring layer, and forming a connection hole penetrating through each wiring layer and reaching the semiconductor substrate in a region where the connection hole not forming the layer for inhibiting electrical connection is formed. A region where the connection hole in which the layer for inhibiting the electrical connection is formed is formed,
A method of manufacturing a semiconductor device, comprising: forming a connection hole penetrating through each of the wiring layers and not reaching the semiconductor substrate; and embedding a conductive material in the connection hole.